 josh
|
8f5171133e
|
add dj_47dr_lmx vivado project
|
2024-07-04 20:25:32 +08:00 |
|
|
josh
|
5a9cb91186
|
update dj_47dr_ibert vivado project, will not affect vitis project
update some paths to current ones
|
2024-07-02 16:10:06 +08:00 |
|
|
josh
|
86ccfd5cc6
|
git add dr_47dr_ibert vitis project, with basic rfdc function
boot image is created, and start-up test is passed
|
2024-07-02 14:15:33 +08:00 |
|
|
josh
|
c2e411b8fb
|
add dj_47dr vivado ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
|
2024-07-02 14:14:35 +08:00 |
|
|
josh
|
9ac4c532f3
|
add dj_47dr_z7045 vitis fsbl project
boot image is created, and start-up test is passed
|
2024-07-02 14:13:03 +08:00 |
|
|
josh
|
3aac7f01b6
|
add dj_47dr_z7045 ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
|
2024-07-02 14:10:41 +08:00 |
|
|
josh
|
47a1b38997
|
update dj_47dr ps project, add tcp performance server project
refer to readme.md for details
|
2024-07-01 19:27:23 +08:00 |
|
|
josh
|
0dcb823314
|
add ax7020 pl project, including mpsoc bd core only
|
2024-07-01 19:26:17 +08:00 |
|
|
josh
|
66f574fef7
|
update dj_47dr pl, add ttc to mpsoc bd core
|
2024-07-01 19:14:06 +08:00 |
|
|
josh
|
6a4af4fb55
|
add rfsoc_eval vitis project, refer to readme for details
|
2024-07-01 14:31:21 +08:00 |
|
|
josh
|
fad0306d82
|
add rfsoc_eval pl project
|
2024-06-29 00:11:59 +08:00 |
|
|
josh
|
cec690b984
|
add dj_47dr vitis projects, refer to readme within each project for details
|
2024-06-28 23:06:09 +08:00 |
|
|
josh
|
0eead518df
|
add dj_47dr pl project, set .dcp as large file type
|
2024-06-28 22:24:04 +08:00 |
|
|
josh
|
8c68cb519e
|
add xilinx spi examlpe with ax7020
refer to projects/ax7020/ax7020_spi_loopback/README.md for detailed information
|
2024-01-24 20:14:55 +08:00 |
|