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base: josh/vivado_pub:5a9cb911860d407502c978aef444d88b5cca339a
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josh/vivado_pub:master josh/vivado_pub:tx_qpsk_poly
josh/vivado_pub:xc7k410tffg900-2_ad9361_mapping josh/vivado_pub:dj_47dr_20240711
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compare: josh/vivado_pub:c4b23c89edc4562294a52c1481000aef851c4434
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josh/vivado_pub:master josh/vivado_pub:tx_qpsk_poly
josh/vivado_pub:xc7k410tffg900-2_ad9361_mapping josh/vivado_pub:dj_47dr_20240711
5 Commits
5a9cb91186 ... c4b23c89ed
Author SHA1 Message Date
josh c4b23c89ed update dj_47dr_demo, including lmx constraints and axi spi engine miso line number 2024-07-05 15:00:07 +08:00
josh bbc5e544a1 update dj_47dr_lmx vitis project 
decrease spi speed to garantee valid readback, disable lmx2594 ramp config, update some comments
 2024-07-05 11:39:44 +08:00
josh 5f6348942f update dj_47dr_lmx vivado project 
change axi spi engine miso line number to 1, miso is now selected based on cs
 2024-07-05 11:35:10 +08:00
josh 81467ace82 add dj_47dr_lmx vitis project 
refer to readme for details
 2024-07-04 20:32:14 +08:00
josh 8f5171133e add dj_47dr_lmx vivado project 2024-07-04 20:25:32 +08:00
4865 changed files with 1655100 additions and 53 deletions
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projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.runs/impl_1/system_top.bit
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projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/constrs_1/new/dj_47dr.xdc
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@@ -6,15 +6,15 @@ set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports lmk_spi
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_mosi ] ;# LMK_SPI_SDI set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_mosi ] ;# LMK_SPI_SDI
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_sck ] ;# LMX_RF_ADC_SCK set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_sck ] ;# LMX_RF_ADC_SCK
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_cs ] ;# LMX_RF_ADC_CS set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_cs ] ;# LMX_RF_ADC_CS
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_mosi ] ;# LMX_RF_ADC_SDI set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_mosi ] ;# LMX_RF_ADC_SDI
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_miso ] ;# LMX_RF_ADC_SDO set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_miso ] ;# LMX_RF_ADC_SDO
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_sck ] ;# LMX_RF_DAC_SCK set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_sck ] ;# LMX_RF_DAC_CLK
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_cs ] ;# LMX_RF_DAC_CS set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_cs ] ;# LMX_RF_DAC_CS
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO
# Route HDGC clock through BUFG to adjacent CMT # Route HDGC clock through BUFG to adjacent CMT
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+4 -4
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@@ -128,13 +128,13 @@
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci
+4 -4
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@@ -12,7 +12,7 @@
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -23,7 +23,7 @@
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ] "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
@@ -66,14 +66,14 @@
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], "sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ], "sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
"sdi_data_valid": [ { "direction": "out" } ], "sdi_data_valid": [ { "direction": "out" } ],
"sdi_data": [ { "direction": "out", "size_left": "23", "size_right": "0" } ], "sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sync_ready": [ { "direction": "in" } ], "sync_ready": [ { "direction": "in" } ],
"sync_valid": [ { "direction": "out" } ], "sync_valid": [ { "direction": "out" } ],
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], "sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sclk": [ { "direction": "out" } ], "sclk": [ { "direction": "out" } ],
"sdo": [ { "direction": "out" } ], "sdo": [ { "direction": "out" } ],
"sdo_t": [ { "direction": "out" } ], "sdo_t": [ { "direction": "out" } ],
"sdi": [ { "direction": "in", "size_left": "2", "size_right": "0" } ], "sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], "cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"three_wire": [ { "direction": "out" } ] "three_wire": [ { "direction": "out" } ]
}, },
projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/system_bd.bd
+3 -3
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@@ -1,7 +1,7 @@
{ {
"design": { "design": {
"design_info": { "design_info": {
"boundary_crc": "0xF2A321F5CFA5E97D", "boundary_crc": "0x15EB8843C4739D6C",
"device": "xczu47dr-ffve1156-2-i", "device": "xczu47dr-ffve1156-2-i",
"gen_directory": "../../../../dj_47dr_demo.gen/sources_1/bd/system_bd", "gen_directory": "../../../../dj_47dr_demo.gen/sources_1/bd/system_bd",
"name": "system_bd", "name": "system_bd",
@@ -50,7 +50,7 @@
"sdi": { "sdi": {
"physical_name": "spi_sdi", "physical_name": "spi_sdi",
"direction": "I", "direction": "I",
"left": "2", "left": "0",
"right": "0" "right": "0"
}, },
"sdo": { "sdo": {
@@ -3173,7 +3173,7 @@
"value": "3" "value": "3"
}, },
"NUM_OF_SDI": { "NUM_OF_SDI": {
"value": "3" "value": "1"
} }
} }
} }
projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/new/system_top.v
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@@ -113,7 +113,7 @@ wire sys_rstn;
// spi interface // spi interface
wire spi_sclk ; wire spi_sclk ;
wire [2:0] spi_cs ; wire [2:0] spi_cs ;
wire [2:0] spi_sdi ; reg spi_sdi ;
wire spi_sdo ; wire spi_sdo ;
wire spi_sdo_t ; wire spi_sdo_t ;
wire spi_three_wire; wire spi_three_wire;
@@ -121,19 +121,25 @@ wire spi_active ;
assign lmk_spi_sck = spi_sclk; assign lmk_spi_sck = spi_sclk;
assign lmk_spi_cs = spi_cs[0]; assign lmk_spi_cs = spi_cs[0];
assign spi_sdi[0] = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_adc_spi_sck = spi_sclk; assign lmx_adc_spi_sck = spi_sclk;
assign lmx_adc_spi_cs = spi_cs[1]; assign lmx_adc_spi_cs = spi_cs[1];
assign spi_sdi[1] = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_dac_spi_sck = spi_sclk; assign lmx_dac_spi_sck = spi_sclk;
assign lmx_dac_spi_cs = spi_cs[2]; assign lmx_dac_spi_cs = spi_cs[2];
assign spi_sdi[2] = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
always @(*) begin
case (spi_cs)
3'b110: spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
3'b101: spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
3'b011: spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
default: spi_sdi = 1'bz;
endcase
end
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
// ADC Tile & Channel Mapping (Dual RF-ADC) // ADC Tile & Channel Mapping (Dual RF-ADC)
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/utils_1/imports/synth_1/system_top.dcp
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projects/dj_47dr/dj_47dr_demo/system_top.xsa
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projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/_ide/bitstream/system_top.bit
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projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/_ide/hwspec.checksum
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@@ -1 +1 @@
1826953298 168373126
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/dj_47dr_basic.prj
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@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="ASCII"?> <?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_basic" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_basic_system" sysConfig="dj_47dr_platform" runtime="cpp" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0"> <sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_basic" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_basic_system" sysConfig="dj_47dr_platform" runtime="cpp" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0">
<configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.2086016496"> <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.2086016496" dirty="true">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/> <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/> <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration> </configuration>
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/src/dev_profile/lmk04828_profile.c
+2 -1
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@@ -17,8 +17,9 @@ struct lmk04828_init_param lmk04828_default_init_param = {
.spi_init = &lmk04828_spi_init .spi_init = &lmk04828_spi_init
}; };
const uint32_t lmk04828_default_config_len = 136; const uint32_t lmk04828_default_config_len = 137;
const struct lmk04828_config lmk04828_default_config[] = { const struct lmk04828_config lmk04828_default_config[] = {
{0x0000, 0x90}, // [7] reset; [4] 3-wire mode disabled
{0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled {0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled
{0x0002, 0x00}, // [0] normal operation {0x0002, 0x00}, // [0] normal operation
{0x0003, 0x06}, // [7-0] product device type, read only, default: 6 {0x0003, 0x06}, // [7-0] product device type, read only, default: 6
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic_system/_ide/scripts/debugger_dj_47dr_basic-default.tcl
+4 -3
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@@ -24,11 +24,12 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"} targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
set bp_54_45_fsbl_bp [bpadd -addr &XFsbl_Exit] set bp_20_42_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60 con -block -timeout 60
bpremove $bp_54_45_fsbl_bp bpremove $bp_20_42_fsbl_bp
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"} targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/Debug/dj_47dr_basic.elf dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/Debug/dj_47dr_basic.elf
configparams force-mem-access 0 configparams force-mem-access 0
bpadd -addr &main targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
con
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/_ide/bitstream/system_top.bit
LFS
BIN
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projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/_ide/hwspec.checksum
+1 -1
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@@ -1 +1 @@
1826953298 168373126
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/src/dev_profile/lmk04828_profile.c
+2 -1
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@@ -17,8 +17,9 @@ struct lmk04828_init_param lmk04828_default_init_param = {
.spi_init = &lmk04828_spi_init .spi_init = &lmk04828_spi_init
}; };
const uint32_t lmk04828_default_config_len = 136; const uint32_t lmk04828_default_config_len = 137;
const struct lmk04828_config lmk04828_default_config[] = { const struct lmk04828_config lmk04828_default_config[] = {
{0x0000, 0x90}, // [7] reset; [4] 3-wire mode disabled
{0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled {0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled
{0x0002, 0x00}, // [0] normal operation {0x0002, 0x00}, // [0] normal operation
{0x0003, 0x06}, // [7-0] product device type, read only, default: 6 {0x0003, 0x06}, // [7-0] product device type, read only, default: 6
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts_system/_ide/scripts/debugger_dj_47dr_mts-default.tcl
+4 -3
View File
@@ -24,11 +24,12 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"} targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
set bp_0_12_fsbl_bp [bpadd -addr &XFsbl_Exit] set bp_22_58_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60 con -block -timeout 60
bpremove $bp_0_12_fsbl_bp bpremove $bp_22_58_fsbl_bp
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"} targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/Debug/dj_47dr_mts.elf dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/Debug/dj_47dr_mts.elf
configparams force-mem-access 0 configparams force-mem-access 0
bpadd -addr &main targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
con
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/hw/system_top.bit
LFS
BIN
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Binary file not shown.
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/hw/system_top.xsa
LFS
BIN
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projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/platform.spr
+1 -1
View File
@@ -1 +1 @@
{"platformName":"dj_47dr_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"dj_47dr_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynqMP","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","platFsblTarget":"psu_cortexa53_0","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects ","pmufwExtraCompilerFlags":"-MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -Os -flto -ffat-lto-objects ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"dj_47dr_platform","systems":[{"systemName":"dj_47dr_platform","systemDesc":"dj_47dr_platform","sysIsBootAutoGen":"true","systemDispName":"dj_47dr_platform","sysActiveDom":"standalone_psu_cortexa53_0","sysDefaultDom":"standalone_psu_cortexa53_0","domains":[{"domainName":"zynqmp_fsbl","domainDispName":"zynqmp_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"34f9144051f817f481e1243bae5bfc58","compatibleApp":"zynqmp_fsbl","domType":"bootDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilsecure:5.3","xilpm:5.2"],"libOptions":{"standalone":{"zynqmp_fsbl_bsp":"true","libOptionNames":["zynqmp_fsbl_bsp"]},"xilffs":{"read_only":"true","use_mkfs":"false","libOptionNames":["read_only","use_mkfs"]},"xilsecure":{"tpm_support":"true","libOptionNames":["tpm_support"]},"libsContainingOptions":["standalone","xilffs","xilsecure"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"zynqmp_pmufw","domainDispName":"zynqmp_pmufw","domainDesc":"PMUFW Application BSP - Auto Generated.","processors":"psu_pmu_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"021024173153c25a215a10b82acc64cf","compatibleApp":"zynqmp_pmufw","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilfpga:6.6","xilsecure:5.3","xilskey:7.6"],"libOptions":{"psu_pmu_0":{"extra_compiler_flags":"-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns -Os -flto -ffat-lto-objects","libOptionNames":["extra_compiler_flags"]},"libsContainingOptions":["psu_pmu_0"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_psu_cortexa53_0","domainDispName":"standalone_psu_cortexa53_0","domainDesc":"standalone_psu_cortexa53_0","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu_args.txt","qemuData":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu","pmuQemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/pmu_args.txt","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"8c89b0a93ea1628441ce7dd0fae33ed2","compatibleApp":"","domType":"mssDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilpm:5.2","xilsecure:5.3","lwip220:1.0"],"libOptions":{"lwip220":{"lwip_dhcp":"true","mem_size":"524288","memp_n_pbuf":"2048","memp_n_tcp_pcb":"1024","memp_n_tcp_seg":"1024","pbuf_pool_size":"4096","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","libOptionNames":["lwip_dhcp","mem_size","memp_n_pbuf","memp_n_tcp_pcb","memp_n_tcp_seg","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd"]},"psu_cortexa53_0":{"extra_compiler_flags":"-g -Wall -Wextra -Os","libOptionNames":["extra_compiler_flags"]},"standalone":{"stdin":"psu_coresight_0","stdout":"psu_coresight_0","libOptionNames":["stdin","stdout"]},"libsContainingOptions":["lwip220","psu_cortexa53_0","standalone"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]} {"platformName":"dj_47dr_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"dj_47dr_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynqMP","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","platFsblTarget":"psu_cortexa53_0","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects ","pmufwExtraCompilerFlags":"-MMD -MP -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -Os -flto -ffat-lto-objects ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"dj_47dr_platform","systems":[{"systemName":"dj_47dr_platform","systemDesc":"dj_47dr_platform","sysIsBootAutoGen":"true","systemDispName":"dj_47dr_platform","sysActiveDom":"standalone_psu_cortexa53_0","sysDefaultDom":"standalone_psu_cortexa53_0","domains":[{"domainName":"zynqmp_fsbl","domainDispName":"zynqmp_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"34f9144051f817f481e1243bae5bfc581","compatibleApp":"zynqmp_fsbl","domType":"bootDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilsecure:5.3","xilpm:5.2"],"libOptions":{"standalone":{"zynqmp_fsbl_bsp":"true","libOptionNames":["zynqmp_fsbl_bsp"]},"xilffs":{"read_only":"true","use_mkfs":"false","libOptionNames":["read_only","use_mkfs"]},"xilsecure":{"tpm_support":"true","libOptionNames":["tpm_support"]},"libsContainingOptions":["standalone","xilffs","xilsecure"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"zynqmp_pmufw","domainDispName":"zynqmp_pmufw","domainDesc":"PMUFW Application BSP - Auto Generated.","processors":"psu_pmu_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"021024173153c25a215a10b82acc64cf1","compatibleApp":"zynqmp_pmufw","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilfpga:6.6","xilsecure:5.3","xilskey:7.6"],"libOptions":{"psu_pmu_0":{"extra_compiler_flags":"-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns -Os -flto -ffat-lto-objects","libOptionNames":["extra_compiler_flags"]},"libsContainingOptions":["psu_pmu_0"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_psu_cortexa53_0","domainDispName":"standalone_psu_cortexa53_0","domainDesc":"standalone_psu_cortexa53_0","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu_args.txt","qemuData":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu","pmuQemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/pmu_args.txt","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"8c89b0a93ea1628441ce7dd0fae33ed2","compatibleApp":"","domType":"mssDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilpm:5.2","xilsecure:5.3","lwip220:1.0"],"libOptions":{"lwip220":{"lwip_dhcp":"true","mem_size":"524288","memp_n_pbuf":"2048","memp_n_tcp_pcb":"1024","memp_n_tcp_seg":"1024","pbuf_pool_size":"4096","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","libOptionNames":["lwip_dhcp","mem_size","memp_n_pbuf","memp_n_tcp_pcb","memp_n_tcp_seg","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd"]},"psu_cortexa53_0":{"extra_compiler_flags":"-g -Wall -Wextra -Os","libOptionNames":["extra_compiler_flags"]},"standalone":{"stdin":"psu_coresight_0","stdout":"psu_coresight_0","libOptionNames":["stdin","stdout"]},"libsContainingOptions":["lwip220","psu_cortexa53_0","standalone"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/platform.tcl
+5
View File
@@ -84,3 +84,8 @@ bsp write
bsp reload bsp reload
catch {bsp regenerate} catch {bsp regenerate}
platform generate -domains standalone_psu_cortexa53_0 platform generate -domains standalone_psu_cortexa53_0
platform active {dj_47dr_platform}
platform generate
platform active {dj_47dr_platform}
platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa}
platform generate -domains
projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/system_1.mss
+636
View File
@@ -0,0 +1,636 @@
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 9.1
PARAMETER PROC_INSTANCE = psu_cortexa53_0
PARAMETER stdin = psu_coresight_0
PARAMETER stdout = psu_coresight_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu_cortexa53
PARAMETER DRIVER_VER = 2.1
PARAMETER HW_INSTANCE = psu_cortexa53_0
PARAMETER extra_compiler_flags = -g -Wall -Wextra -Os
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
PARAMETER DRIVER_VER = 5.3
PARAMETER HW_INSTANCE = psu_acpu_gic
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_4
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_5
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_6
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_adma_7
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_4
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_5
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_afi_6
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sysmonpsu
PARAMETER DRIVER_VER = 2.10
PARAMETER HW_INSTANCE = psu_ams
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
PARAMETER DRIVER_VER = 6.11
PARAMETER HW_INSTANCE = psu_apm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
PARAMETER DRIVER_VER = 6.11
PARAMETER HW_INSTANCE = psu_apm_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
PARAMETER DRIVER_VER = 6.11
PARAMETER HW_INSTANCE = psu_apm_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = axipmon
PARAMETER DRIVER_VER = 6.11
PARAMETER HW_INSTANCE = psu_apm_5
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_apu
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_cci_gpv
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_cci_reg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = coresightps_dcc
PARAMETER DRIVER_VER = 1.10
PARAMETER HW_INSTANCE = psu_coresight_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = resetps
PARAMETER DRIVER_VER = 1.7
PARAMETER HW_INSTANCE = psu_crf_apb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_crl_apb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_csu_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = csudma
PARAMETER DRIVER_VER = 1.15
PARAMETER HW_INSTANCE = psu_csudma
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ctrl_ipi
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddrcpsu
PARAMETER DRIVER_VER = 1.6
PARAMETER HW_INSTANCE = psu_ddr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddrcpsu
PARAMETER DRIVER_VER = 1.6
PARAMETER HW_INSTANCE = psu_ddr_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_phy
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_qos_ctrl
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu0_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu1_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu2_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu3_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu4_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ddr_xmpu5_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddrcpsu
PARAMETER DRIVER_VER = 1.6
PARAMETER HW_INSTANCE = psu_ddrc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_efuse
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emacps
PARAMETER DRIVER_VER = 3.20
PARAMETER HW_INSTANCE = psu_ethernet_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_fpd_gpv
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_fpd_slcr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_fpd_slcr_secure
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_fpd_xmpu_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_fpd_xmpu_sink
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_4
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_5
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_6
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = zdma
PARAMETER DRIVER_VER = 1.18
PARAMETER HW_INSTANCE = psu_gdma_7
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpiops
PARAMETER DRIVER_VER = 3.13
PARAMETER HW_INSTANCE = psu_gpio_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_i2c_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = iicps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_i2c_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_iou_scntr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_iou_scntrs
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_iousecure_slcr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_iouslcr_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ipipsu
PARAMETER DRIVER_VER = 2.15
PARAMETER HW_INSTANCE = psu_ipi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_lpd_slcr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_lpd_slcr_secure
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_lpd_xppu
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_lpd_xppu_sink
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_mbistjtag
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_message_buffers
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ocm
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ocm_ram_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_pmu_global_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = qspipsu
PARAMETER DRIVER_VER = 1.19
PARAMETER HW_INSTANCE = psu_qspi_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_qspi_linear_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_r5_0_atcm_global
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_r5_0_btcm_global
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_r5_1_atcm_global
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_r5_1_btcm_global
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_r5_tcm_ram_global
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = scugic
PARAMETER DRIVER_VER = 5.3
PARAMETER HW_INSTANCE = psu_rcpu_gic
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_rpu
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_rsa
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = rtcpsu
PARAMETER DRIVER_VER = 1.14
PARAMETER HW_INSTANCE = psu_rtc
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_serdes
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_siou
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_smmu_gpv
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = psu_smmu_reg
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
PARAMETER DRIVER_VER = 3.14
PARAMETER HW_INSTANCE = psu_uart_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = rfdc
PARAMETER DRIVER_VER = 12.2
PARAMETER HW_INSTANCE = usp_rf_data_converter
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 3.1
PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_ttc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_ttc_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_ttc_2
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ttcps
PARAMETER DRIVER_VER = 3.19
PARAMETER HW_INSTANCE = psu_ttc_3
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilffs
PARAMETER LIBRARY_VER = 5.2
PARAMETER PROC_INSTANCE = psu_cortexa53_0
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilpm
PARAMETER LIBRARY_VER = 5.2
PARAMETER PROC_INSTANCE = psu_cortexa53_0
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = xilsecure
PARAMETER LIBRARY_VER = 5.3
PARAMETER PROC_INSTANCE = psu_cortexa53_0
END
BEGIN LIBRARY
PARAMETER LIBRARY_NAME = lwip220
PARAMETER LIBRARY_VER = 1.0
PARAMETER PROC_INSTANCE = psu_cortexa53_0
PARAMETER lwip_dhcp = true
PARAMETER mem_size = 524288
PARAMETER memp_n_pbuf = 2048
PARAMETER memp_n_tcp_pcb = 1024
PARAMETER memp_n_tcp_seg = 1024
PARAMETER pbuf_pool_size = 4096
PARAMETER tcp_ip_rx_checksum_offload = true
PARAMETER tcp_ip_tx_checksum_offload = true
PARAMETER tcp_snd_buf = 65535
PARAMETER tcp_wnd = 65535
END
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<?xml version="1.0" encoding="ASCII"?> <?xml version="1.0" encoding="ASCII"?>
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_tcp_perf_server" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_tcp_perf_server" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_tcp_perf_server_system" sysConfig="dj_47dr_platform" runtime="C/C++" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0"> <sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_tcp_perf_server" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_tcp_perf_server" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_tcp_perf_server_system" sysConfig="dj_47dr_platform" runtime="C/C++" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0">
<configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.459719114" dirty="true"> <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.459719114">
<configBuildOptions xsi:type="sdkproject:SdkOptions"/> <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/> <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
</configuration> </configuration>
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVPECL } [get_ports pl_refclk_p ] ;# PL_CLK_P
set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVPECL } [get_ports pl_sysref_p ] ;# PL_SYSREF_P
set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_sck ] ;# LMK_SPI_SCK
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports lmk_spi_cs ] ;# LMK_SPI_CS
set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_mosi ] ;# LMK_SPI_SDI
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports lmk_spi_miso ] ;# LMK_SPI_SDO
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_sck ] ;# LMX_RF_ADC_SCK
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_cs ] ;# LMX_RF_ADC_CS
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_mosi ] ;# LMX_RF_ADC_SDI
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports lmx_adc_spi_miso ] ;# LMX_RF_ADC_SDO
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_sck ] ;# LMX_RF_DAC_CLK
set_property -dict {PACKAGE_PIN G13 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_cs ] ;# LMX_RF_DAC_CS
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_mosi ] ;# LMX_RF_DAC_SDI
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports lmx_dac_spi_miso ] ;# LMX_RF_DAC_SDO
# Route HDGC clock through BUFG to adjacent CMT
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci
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{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_auto_pc_0",
"cell_name": "ps8_0_axi_periph/s00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "31",
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
"parameters": {
"component_parameters": {
"SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ID_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xczu47dr" } ],
"NEXTGEN_VERSAL": [ { "value": "0" } ],
"PACKAGE": [ { "value": "ffve1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "31" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2024.1" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"aclk": [ { "direction": "in" } ],
"aresetn": [ { "direction": "in" } ],
"s_axi_awid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
"s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
"s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
"s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
"s_axi_awready": [ { "direction": "out" } ],
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},
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"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
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"AWREGION": [ { "physical_name": "s_axi_awregion" } ],
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"AWREADY": [ { "physical_name": "s_axi_awready" } ],
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
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"WLAST": [ { "physical_name": "s_axi_wlast" } ],
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
"WREADY": [ { "physical_name": "s_axi_wready" } ],
"BID": [ { "physical_name": "s_axi_bid" } ],
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"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
"BREADY": [ { "physical_name": "s_axi_bready" } ],
"ARID": [ { "physical_name": "s_axi_arid" } ],
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
"ARREGION": [ { "physical_name": "s_axi_arregion" } ],
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"RID": [ { "physical_name": "s_axi_rid" } ],
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
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"RLAST": [ { "physical_name": "s_axi_rlast" } ],
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
"RREADY": [ { "physical_name": "s_axi_rready" } ]
}
},
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
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"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
"WREADY": [ { "physical_name": "m_axi_wready" } ],
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
"BREADY": [ { "physical_name": "m_axi_bready" } ],
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
"RREADY": [ { "physical_name": "m_axi_rready" } ]
}
},
"CLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+294
View File
@@ -0,0 +1,294 @@
{
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},
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}
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},
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}
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},
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}
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"sync_valid": [ { "physical_name": "sync_valid" } ],
"sync_data": [ { "physical_name": "sync_data" } ]
}
},
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"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "spi_clk" } ]
}
},
"spi_engine_ctrl_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "master",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "spi_resetn" } ]
}
},
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
}
},
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
}
}
},
"memory_maps": {
"s_axi": {
"address_blocks": {
"axi_lite": {
"base_address": "0",
"range": "65536"
}
}
}
}
}
}
}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci
+658
View File
@@ -0,0 +1,658 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "system_bd_clk_wiz_0_0",
"cell_name": "mts_clk_gen/clk_wiz_pl_clk",
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
"ip_revision": "14",
"gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
"PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
"PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
"CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
"MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_JITTER": [ { "value": "85.228", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT1_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
},
"model_parameters": {
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"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"c_component_name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIM_IN_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
"C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
"C_INCLK_SUM_ROW1": [ { "value": "__primary__________245.76____________0.010", "resolve_type": "generated", "usage": "all" } ],
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__245.76000______0.000______50.0_______85.228_____77.902", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
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"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
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"C_MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
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"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
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"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
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"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
"C_CLKIN1_JITTER_PS": [ { "value": "40.69", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_ps8_0_axi_periph_0/system_bd_ps8_0_axi_periph_0.xci
+353
View File
@@ -0,0 +1,353 @@
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0/system_bd_rst_ps8_0_96M_0.xci
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{
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci
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{
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},
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_usp_rf_data_converter_0_0/system_bd_usp_rf_data_converter_0_0.xci
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0/system_bd_util_ds_buf_0_0.xci
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{
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1/system_bd_util_ds_buf_0_1.xci
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{
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0/system_bd_util_ds_buf_1_0.xci
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{
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci
+1523
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci
+308
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@@ -0,0 +1,308 @@
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci
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}
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},
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}
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"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
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}
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci
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{
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},
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}
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},
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}
}
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}
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}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_zynq_ultra_ps_e_0_1/system_bd_zynq_ultra_ps_e_0_1.xci
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bd
+4907
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda
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{
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui
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{
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"Default View_TopLeft":"-360,-198",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
preplace netloc Conn1 1 0 1 NJ 70
preplace netloc Conn2 1 0 2 NJ 240 NJ
levelinfo -pg 1 0 150 410 670 910 1060
pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
"
}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui
+34
View File
@@ -0,0 +1,34 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-360,-198",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
preplace netloc Conn1 1 0 1 NJ 70
preplace netloc Conn2 1 0 2 NJ 240 NJ
levelinfo -pg 1 0 150 410 670 910 1060
pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
"
}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+179
View File
@@ -0,0 +1,179 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.537304",
"Default View_TopLeft":"-1158,4",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port spi -pg 1 -lvl 4 -x 1120 -y 330 -defaultsOSRD
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
preplace port adc2_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD
preplace port dac2_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
preplace port m00_axis -pg 1 -lvl 4 -x 1120 -y 590 -defaultsOSRD
preplace port m01_axis -pg 1 -lvl 4 -x 1120 -y 610 -defaultsOSRD
preplace port m02_axis -pg 1 -lvl 4 -x 1120 -y 630 -defaultsOSRD
preplace port m03_axis -pg 1 -lvl 4 -x 1120 -y 650 -defaultsOSRD
preplace port m10_axis -pg 1 -lvl 4 -x 1120 -y 670 -defaultsOSRD
preplace port m11_axis -pg 1 -lvl 4 -x 1120 -y 690 -defaultsOSRD
preplace port m12_axis -pg 1 -lvl 4 -x 1120 -y 710 -defaultsOSRD
preplace port m13_axis -pg 1 -lvl 4 -x 1120 -y 730 -defaultsOSRD
preplace port m20_axis -pg 1 -lvl 4 -x 1120 -y 750 -defaultsOSRD
preplace port m21_axis -pg 1 -lvl 4 -x 1120 -y 770 -defaultsOSRD
preplace port m22_axis -pg 1 -lvl 4 -x 1120 -y 790 -defaultsOSRD
preplace port m23_axis -pg 1 -lvl 4 -x 1120 -y 810 -defaultsOSRD
preplace port m30_axis -pg 1 -lvl 4 -x 1120 -y 830 -defaultsOSRD
preplace port m31_axis -pg 1 -lvl 4 -x 1120 -y 850 -defaultsOSRD
preplace port m32_axis -pg 1 -lvl 4 -x 1120 -y 870 -defaultsOSRD
preplace port m33_axis -pg 1 -lvl 4 -x 1120 -y 890 -defaultsOSRD
preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD
preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 600 -defaultsOSRD
preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD
preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD
preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD
preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD
preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 740 -defaultsOSRD
preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 760 -defaultsOSRD
preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD
preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 800 -defaultsOSRD
preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD
preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
preplace port vout00 -pg 1 -lvl 4 -x 1120 -y 910 -defaultsOSRD
preplace port vout02 -pg 1 -lvl 4 -x 1120 -y 930 -defaultsOSRD
preplace port vout10 -pg 1 -lvl 4 -x 1120 -y 950 -defaultsOSRD
preplace port vout12 -pg 1 -lvl 4 -x 1120 -y 970 -defaultsOSRD
preplace port vout20 -pg 1 -lvl 4 -x 1120 -y 990 -defaultsOSRD
preplace port vout22 -pg 1 -lvl 4 -x 1120 -y 1010 -defaultsOSRD
preplace port vout30 -pg 1 -lvl 4 -x 1120 -y 1030 -defaultsOSRD
preplace port vout32 -pg 1 -lvl 4 -x 1120 -y 1050 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1120 -y 350 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1120 -y 1460 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1120 -y 1480 -defaultsOSRD
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1120 -y 540 -defaultsOSRD
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1120 -y 1070 -defaultsOSRD
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1120 -y 1090 -defaultsOSRD
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1120 -y 1110 -defaultsOSRD
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1120 -y 1130 -defaultsOSRD
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1120 -y 1150 -defaultsOSRD
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1120 -y 1170 -defaultsOSRD
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1120 -y 1190 -defaultsOSRD
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1120 -y 1210 -defaultsOSRD
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1020 -defaultsOSRD
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1000 -defaultsOSRD
preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1060 -defaultsOSRD
preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1040 -defaultsOSRD
preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1100 -defaultsOSRD
preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1080 -defaultsOSRD
preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1140 -defaultsOSRD
preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD
preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1180 -defaultsOSRD
preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1160 -defaultsOSRD
preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1220 -defaultsOSRD
preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD
preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1260 -defaultsOSRD
preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1240 -defaultsOSRD
preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1300 -defaultsOSRD
preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1280 -defaultsOSRD
preplace inst usp_rf_data_converter -pg 1 -lvl 1 -x 360 -y 910 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 2 -x 880 -y 350 -defaultsOSRD
preplace inst ps8_0_axi_periph -pg 1 -lvl 1 -x 360 -y 340 -defaultsOSRD
preplace inst rst_ps8_0_96M -pg 1 -lvl 2 -x 880 -y 170 -defaultsOSRD
preplace inst mts_clk_gen -pg 1 -lvl 1 -x 360 -y 1460 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 2 -x 880 -y 470 -defaultsOSRD -orient R180
preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 360 -y 110 -defaultsOSRD
preplace netloc adi_spi_engine_active_0 1 2 2 N 350 N
preplace netloc adi_spi_engine_irq 1 2 1 1060 370n
preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1020
preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1000
preplace netloc m1_axis_aclk_0_1 1 0 1 NJ 1060
preplace netloc m1_axis_aresetn_0_1 1 0 1 NJ 1040
preplace netloc m2_axis_aclk_0_1 1 0 1 NJ 1100
preplace netloc m2_axis_aresetn_0_1 1 0 1 NJ 1080
preplace netloc m3_axis_aclk_0_1 1 0 1 NJ 1140
preplace netloc m3_axis_aresetn_0_1 1 0 1 NJ 1120
preplace netloc mts_sysref_gen_clk_out1_0 1 1 3 N 1460 NJ 1460 N
preplace netloc mts_sysref_gen_locked_0 1 1 3 N 1480 NJ 1480 N
preplace netloc mts_sysref_gen_mts_sysref 1 0 2 20 1380 670
preplace netloc rst_ps8_0_96M_peripheral_aresetn 1 0 3 40 1360 700J 270 1060
preplace netloc s0_axis_aclk_0_1 1 0 1 NJ 1180
preplace netloc s0_axis_aresetn_0_1 1 0 1 NJ 1160
preplace netloc s1_axis_aclk_0_1 1 0 1 NJ 1220
preplace netloc s1_axis_aresetn_0_1 1 0 1 NJ 1200
preplace netloc s2_axis_aclk_0_1 1 0 1 NJ 1260
preplace netloc s2_axis_aresetn_0_1 1 0 1 NJ 1240
preplace netloc s3_axis_aclk_0_1 1 0 1 NJ 1300
preplace netloc s3_axis_aresetn_0_1 1 0 1 N 1280
preplace netloc usp_rf_data_converter_clk_adc0 1 1 3 N 1070 NJ 1070 N
preplace netloc usp_rf_data_converter_clk_adc1 1 1 3 N 1090 NJ 1090 N
preplace netloc usp_rf_data_converter_clk_adc2 1 1 3 N 1110 NJ 1110 N
preplace netloc usp_rf_data_converter_clk_adc3 1 1 3 N 1130 NJ 1130 N
preplace netloc usp_rf_data_converter_clk_dac0 1 1 3 N 1150 NJ 1150 N
preplace netloc usp_rf_data_converter_clk_dac1 1 1 3 N 1170 NJ 1170 N
preplace netloc usp_rf_data_converter_clk_dac2 1 1 3 N 1190 NJ 1190 N
preplace netloc usp_rf_data_converter_clk_dac3 1 1 3 N 1210 NJ 1210 N
preplace netloc usp_rf_data_converter_irq 1 1 2 N 1230 1060
preplace netloc xlconcat_0_dout 1 0 2 20 10 680J
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 540 NJ 540 N
preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 670 110n
preplace netloc adc2_clk_1 1 0 1 N 700
preplace netloc adi_spi_engine_spi_0 1 2 2 N 330 N
preplace netloc dac2_clk_1 1 0 1 N 720
preplace netloc pl_clk_0_1 1 0 1 N 1450
preplace netloc pl_sysref_0_1 1 0 1 N 1470
preplace netloc ps8_0_axi_periph_M00_AXI 1 1 1 NJ 330
preplace netloc ps8_0_axi_periph_M01_AXI 1 0 2 50 200 670J
preplace netloc s00_axis_0_1 1 0 1 NJ 540
preplace netloc s02_axis_0_1 1 0 1 NJ 560
preplace netloc s10_axis_0_1 1 0 1 NJ 580
preplace netloc s12_axis_0_1 1 0 1 NJ 600
preplace netloc s20_axis_0_1 1 0 1 NJ 620
preplace netloc s22_axis_0_1 1 0 1 NJ 640
preplace netloc s30_axis_0_1 1 0 1 NJ 660
preplace netloc s32_axis_0_1 1 0 1 NJ 680
preplace netloc sysref_in_0_1 1 0 1 NJ 900
preplace netloc usp_rf_data_converter_m00_axis 1 1 3 N 590 NJ 590 N
preplace netloc usp_rf_data_converter_m01_axis 1 1 3 N 610 NJ 610 N
preplace netloc usp_rf_data_converter_m02_axis 1 1 3 N 630 NJ 630 N
preplace netloc usp_rf_data_converter_m03_axis 1 1 3 N 650 NJ 650 N
preplace netloc usp_rf_data_converter_m10_axis 1 1 3 N 670 NJ 670 N
preplace netloc usp_rf_data_converter_m11_axis 1 1 3 N 690 NJ 690 N
preplace netloc usp_rf_data_converter_m12_axis 1 1 3 N 710 NJ 710 N
preplace netloc usp_rf_data_converter_m13_axis 1 1 3 N 730 NJ 730 N
preplace netloc usp_rf_data_converter_m20_axis 1 1 3 N 750 NJ 750 N
preplace netloc usp_rf_data_converter_m21_axis 1 1 3 N 770 NJ 770 N
preplace netloc usp_rf_data_converter_m22_axis 1 1 3 N 790 NJ 790 N
preplace netloc usp_rf_data_converter_m23_axis 1 1 3 N 810 NJ 810 N
preplace netloc usp_rf_data_converter_m30_axis 1 1 3 N 830 NJ 830 N
preplace netloc usp_rf_data_converter_m31_axis 1 1 3 N 850 NJ 850 N
preplace netloc usp_rf_data_converter_m32_axis 1 1 3 N 870 NJ 870 N
preplace netloc usp_rf_data_converter_m33_axis 1 1 3 N 890 NJ 890 N
preplace netloc usp_rf_data_converter_vout00 1 1 3 N 910 NJ 910 N
preplace netloc usp_rf_data_converter_vout02 1 1 3 N 930 NJ 930 N
preplace netloc usp_rf_data_converter_vout10 1 1 3 N 950 NJ 950 N
preplace netloc usp_rf_data_converter_vout12 1 1 3 N 970 NJ 970 N
preplace netloc usp_rf_data_converter_vout20 1 1 3 N 990 NJ 990 N
preplace netloc usp_rf_data_converter_vout22 1 1 3 N 1010 NJ 1010 N
preplace netloc usp_rf_data_converter_vout30 1 1 3 N 1030 NJ 1030 N
preplace netloc usp_rf_data_converter_vout32 1 1 3 N 1050 NJ 1050 N
preplace netloc vin0_01_0_1 1 0 1 NJ 740
preplace netloc vin0_23_0_1 1 0 1 NJ 760
preplace netloc vin1_01_0_1 1 0 1 NJ 780
preplace netloc vin1_23_0_1 1 0 1 NJ 800
preplace netloc vin2_01_0_1 1 0 1 NJ 820
preplace netloc vin2_23_0_1 1 0 1 NJ 840
preplace netloc vin3_01_0_1 1 0 1 NJ 860
preplace netloc vin3_23_0_1 1 0 1 NJ 880
preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_LPD 1 0 2 40 20 670
levelinfo -pg 1 0 360 880 1080 1120
pagesize -pg 1 -db -bbox -sgen -170 0 1240 1530
"
}
{
"da_axi4_cnt":"4",
"da_board_cnt":"1"
}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui
+28
View File
@@ -0,0 +1,28 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-578,-657",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 740 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
preplace port port-id_active -pg 1 -lvl 3 -x 740 -y -230 -defaultsOSRD
preplace port port-id_irq -pg 1 -lvl 3 -x 740 -y -320 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 600 -y -240 -defaultsOSRD
preplace netloc axi_spi_engine_irq 1 1 2 480J -320 NJ
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 490J
preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
preplace netloc spi_engine_execution_active 1 2 1 NJ -230
preplace netloc Conn1 1 0 1 NJ -270
preplace netloc Conn2 1 2 1 NJ -250
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
levelinfo -pg 1 0 340 600 740
pagesize -pg 1 -db -bbox -sgen -150 -630 840 180
"
}
0
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui
+26
View File
@@ -0,0 +1,26 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-578,-657",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 710 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
preplace port port-id_active -pg 1 -lvl 3 -x 710 -y -230 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 590 -y -240 -defaultsOSRD
preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 480J
preplace netloc spi_engine_execution_active 1 2 1 NJ -230
preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
preplace netloc Conn1 1 0 1 NJ -270
preplace netloc Conn2 1 2 1 NJ -250
levelinfo -pg 1 0 340 590 710
pagesize -pg 1 -db -bbox -sgen -150 -630 810 180
"
}
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci
+213
View File
@@ -0,0 +1,213 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "cmpy_18x8",
"component_reference": "xilinx.com:ip:cmpy:6.0",
"ip_revision": "24",
"gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HasATUSER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci
+358
View File
@@ -0,0 +1,358 @@
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/hop_rom/hop_rom.xci
+254
View File
@@ -0,0 +1,254 @@
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/ila_adc/ila_adc.xci
+6314
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/ila_dac/ila_dac.xci
+6300
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/sweep_freq.coe
+258
View File
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2147483647;
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/15/2022 08:34:01 PM
// Design Name:
// Module Name: system_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_top
(
// *************************************************************************
// *************************** Clocks and SYSREF ***************************
// *************************************************************************
// adc clock
input adc1_clk_in_p ,
input adc1_clk_in_n ,
input adc2_clk_in_p ,
input adc2_clk_in_n ,
// dac clock
input dac0_clk_in_p ,
input dac0_clk_in_n ,
input dac2_clk_in_p ,
input dac2_clk_in_n ,
// sysref for rf
input rf_sysref_p ,
input rf_sysref_n ,
// sysref for pl
input pl_sysref_p ,
input pl_sysref_n ,
// fpga clock
input pl_refclk_p ,
input pl_refclk_n ,
// *************************************************************************
// ******************************** RF-DAC *********************************
// *************************************************************************
input adc0_01_in_p ,
input adc0_01_in_n ,
input adc0_23_in_p ,
input adc0_23_in_n ,
input adc1_01_in_p ,
input adc1_01_in_n ,
input adc1_23_in_p ,
input adc1_23_in_n ,
input adc2_01_in_p ,
input adc2_01_in_n ,
input adc2_23_in_p ,
input adc2_23_in_n ,
input adc3_01_in_p ,
input adc3_01_in_n ,
input adc3_23_in_p ,
input adc3_23_in_n ,
// *************************************************************************
// ******************************** RF-DAC *********************************
// *************************************************************************
output dac00_out_p ,
output dac00_out_n ,
output dac02_out_p ,
output dac02_out_n ,
output dac10_out_p ,
output dac10_out_n ,
output dac12_out_p ,
output dac12_out_n ,
output dac20_out_p ,
output dac20_out_n ,
output dac22_out_p ,
output dac22_out_n ,
output dac30_out_p ,
output dac30_out_n ,
output dac32_out_p ,
output dac32_out_n ,
// *************************************************************************
// ***************************** SPI Interface *****************************
// *************************************************************************
// lmk04828
output lmk_spi_sck ,
output lmk_spi_cs ,
inout lmk_spi_mosi ,
input lmk_spi_miso ,
// lmx2594-adc
output lmx_adc_spi_sck ,
output lmx_adc_spi_cs ,
inout lmx_adc_spi_mosi ,
input lmx_adc_spi_miso ,
// lmx2594-dac
output lmx_dac_spi_sck ,
output lmx_dac_spi_cs ,
inout lmx_dac_spi_mosi ,
input lmx_dac_spi_miso
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Block Design Interface ////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire ps_clk0;
wire sys_clk;
wire sys_rstn;
// spi interface
wire spi_sclk ;
wire [2:0] spi_cs ;
reg spi_sdi ;
wire spi_sdo ;
wire spi_sdo_t ;
wire spi_three_wire;
wire spi_active ;
assign lmk_spi_sck = spi_sclk;
assign lmk_spi_cs = spi_cs[0];
assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_adc_spi_sck = spi_sclk;
assign lmx_adc_spi_cs = spi_cs[1];
assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_dac_spi_sck = spi_sclk;
assign lmx_dac_spi_cs = spi_cs[2];
assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
always @(*) begin
case (spi_cs)
3'b110: spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
3'b101: spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
3'b011: spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
default: spi_sdi = 1'bz;
endcase
end
// -----------------------------------------------------------------------------
// ADC Tile & Channel Mapping (Dual RF-ADC)
// -----------------------------------------------------------------------------
// m00_axis adc00 adc tile 224 (adc0), channel 0
// m01_axis adc01 adc tile 224 (adc0), channel 1
// m02_axis adc02 adc tile 224 (adc0), channel 2
// m03_axis adc03 adc tile 224 (adc0), channel 3
// -----------------------------------------------------------------------------
// m10_axis adc10 adc tile 225 (adc1), channel 0
// m11_axis adc11 adc tile 225 (adc1), channel 1
// m12_axis adc12 adc tile 225 (adc1), channel 2
// m13_axis adc13 adc tile 225 (adc1), channel 3
// -----------------------------------------------------------------------------
// m20_axis adc20 adc tile 226 (adc2), channel 0
// m21_axis adc21 adc tile 226 (adc2), channel 1
// m22_axis adc22 adc tile 226 (adc2), channel 2
// m23_axis adc23 adc tile 226 (adc2), channel 3
// -----------------------------------------------------------------------------
// m30_axis adc30 adc tile 227 (adc3), channel 0
// m31_axis adc31 adc tile 227 (adc3), channel 1
// m32_axis adc32 adc tile 227 (adc3), channel 2
// m33_axis adc33 adc tile 227 (adc3), channel 3
// -----------------------------------------------------------------------------
// Note:
// 1) If digital output data is set to real, only channel 0/2 is enabled; if
// digital output data is set to i/q, both channel 0/2 and 1/3 are enabled,
// since i/q data are transferred in different channels.
// 2) When modify the following wire definition, **ONLY** change the data width.
// The extra definition will be optimized automatically.
// -----------------------------------------------------------------------------
wire [15:0] adc00_data, adc01_data;
wire adc00_data_ready, adc01_data_ready;
wire adc00_data_valid, adc01_data_valid;
wire [15:0] adc02_data, adc03_data;
wire adc02_data_ready, adc03_data_ready;
wire adc02_data_valid, adc03_data_valid;
wire [15:0] adc10_data, adc11_data;
wire adc10_data_ready, adc11_data_ready;
wire adc10_data_valid, adc11_data_valid;
wire [15:0] adc12_data, adc13_data;
wire adc12_data_ready, adc13_data_ready;
wire adc12_data_valid, adc13_data_valid;
wire [15:0] adc20_data, adc21_data;
wire adc20_data_ready, adc21_data_ready;
wire adc20_data_valid, adc21_data_valid;
wire [15:0] adc22_data, adc23_data;
wire adc22_data_ready, adc23_data_ready;
wire adc22_data_valid, adc23_data_valid;
wire [15:0] adc30_data, adc31_data;
wire adc30_data_ready, adc31_data_ready;
wire adc30_data_valid, adc31_data_valid;
wire [15:0] adc32_data, adc33_data;
wire adc32_data_ready, adc33_data_ready;
wire adc32_data_valid, adc33_data_valid;
// -----------------------------------------------------------------------------
// DAC Tile & Channel Mapping (Dual RF-DAC)
// -----------------------------------------------------------------------------
// s00_axis dac00 dac tile 228 (dac0), channel 0
// s01_axis dac00 dac tile 228 (dac0), channel 1
// s02_axis dac02 dac tile 228 (dac0), channel 2
// s03_axis dac02 dac tile 228 (dac0), channel 3
// -----------------------------------------------------------------------------
// s10_axis dac10 dac tile 229 (dac1), channel 0
// s11_axis dac10 dac tile 229 (dac1), channel 1
// s12_axis dac12 dac tile 229 (dac1), channel 2
// s13_axis dac12 dac tile 229 (dac1), channel 3
// -----------------------------------------------------------------------------
// s20_axis dac20 dac tile 230 (dac2), channel 0
// s21_axis dac20 dac tile 230 (dac2), channel 1
// s22_axis dac22 dac tile 230 (dac2), channel 2
// s23_axis dac22 dac tile 230 (dac2), channel 3
// -----------------------------------------------------------------------------
// s30_axis dac30 dac tile 231 (dac3), channel 0
// s31_axis dac30 dac tile 231 (dac3), channel 1
// s32_axis dac32 dac tile 231 (dac3), channel 2
// s33_axis dac32 dac tile 231 (dac3), channel 3
// -----------------------------------------------------------------------------
// Note:
// 1) In most single-band cases, only channel 0/2 is enabled since i/q data are
// transferred in one signle channel; when multi-band is used, multiple digital
// channel may be enabled.
// 2) When modify the following wire definition, **ONLY** change the data width.
// The extra definition will be optimized automatically.
// -----------------------------------------------------------------------------
wire [31:0] dac00_data, dac01_data;
wire dac00_data_ready, dac01_data_ready;
wire dac00_data_valid, dac01_data_valid;
wire [31:0] dac02_data, dac03_data;
wire dac02_data_ready, dac03_data_ready;
wire dac02_data_valid, dac03_data_valid;
wire [31:0] dac10_data, dac11_data;
wire dac10_data_ready, dac11_data_ready;
wire dac10_data_valid, dac11_data_valid;
wire [31:0] dac12_data, dac13_data;
wire dac12_data_ready, dac13_data_ready;
wire dac12_data_valid, dac13_data_valid;
wire [31:0] dac20_data, dac21_data;
wire dac20_data_ready, dac21_data_ready;
wire dac20_data_valid, dac21_data_valid;
wire [31:0] dac22_data, dac23_data;
wire dac22_data_ready, dac23_data_ready;
wire dac22_data_valid, dac23_data_valid;
wire [31:0] dac30_data, dac31_data;
wire dac30_data_ready, dac31_data_ready;
wire dac30_data_valid, dac31_data_valid;
wire [31:0] dac32_data, dac33_data;
wire dac32_data_ready, dac33_data_ready;
wire dac32_data_valid, dac33_data_valid;
system_bd_wrapper u_system_bd_wrapper
(
// *************************************************************************
// ********************* PL SYSREF & Reference Clocks **********************
// *************************************************************************
.ps_clk0 (ps_clk0 ),
.pl_clk_clk_p (pl_refclk_p ),
.pl_clk_clk_n (pl_refclk_n ),
.pl_sysref_clk_p (pl_sysref_p ),
.pl_sysref_clk_n (pl_sysref_n ),
.sys_clk (sys_clk ),
.sys_rstn (sys_rstn ),
// *************************************************************************
// ********************* RF SYSREF & Reference Clocks **********************
// *************************************************************************
.spi_sclk (spi_sclk ),
.spi_cs (spi_cs ),
.spi_sdi (spi_sdi ),
.spi_sdo (spi_sdo ),
.spi_sdo_t (spi_sdo_t ),
.spi_three_wire (spi_three_wire ),
.spi_active (spi_active ),
// *************************************************************************
// ********************* RF SYSREF & Reference Clocks **********************
// *************************************************************************
// rf sysref
.sysref_in_diff_p (rf_sysref_p ), // input sysref_in_diff_p
.sysref_in_diff_n (rf_sysref_n ), // input sysref_in_diff_n
// -------------------------------------------------------------------------
// RF ADC Reference Clocks Mapping
// -------------------------------------------------------------------------
// adc0_clk_clk adc tile 224 (adc0) ref clock input, nc on borad
// adc1_clk_clk adc tile 225 (adc1) ref clock input, from lmk04828
// adc2_clk_clk adc tile 226 (adc2) ref clock input, from sma
// adc3_clk_clk adc tile 227 (adc3) ref clock input, nc on borad
// clk_adc0 adc tile 224 (adc0) clock output
// clk_adc1 adc tile 225 (adc1) clock output
// clk_adc2 adc tile 226 (adc2) clock output
// clk_adc3 adc tile 227 (adc3) clock output
// -------------------------------------------------------------------------
// Note:
// When modify the following wire connections, **ONLY** uncomment the needed
// ports and comment the not-needed ones.
// -------------------------------------------------------------------------
// .adc1_clk_clk_p (adc1_clk_in_p ), // input adc1_clk_clk_p
// .adc1_clk_clk_n (adc1_clk_in_n ), // input adc1_clk_clk_n
.adc2_clk_clk_p (adc2_clk_in_p ), // input adc2_clk_clk_p
.adc2_clk_clk_n (adc2_clk_in_n ), // input adc2_clk_clk_n
.clk_adc0 ( ), // output clk_adc0
.clk_adc1 ( ), // output clk_adc1
.clk_adc2 ( ), // output clk_adc2
.clk_adc3 ( ), // output clk_adc3
// -------------------------------------------------------------------------
// RF DAC Reference Clocks Mapping
// -------------------------------------------------------------------------
// dac0_clk_clk dac tile 228 (dac0) ref clock input, from lmk04828
// dac1_clk_clk dac tile 229 (dac1) ref clock input, none for zu48dr
// dac2_clk_clk dac tile 230 (dac2) ref clock input, from sma
// dac3_clk_clk dac tile 231 (dac3) ref clock input, none for zu48dr
// clk_dac0 dac tile 228 (dac0) clock output
// clk_dac1 dac tile 229 (dac1) clock output
// clk_dac2 dac tile 230 (dac2) clock output
// clk_dac3 dac tile 231 (dac3) clock output
// -------------------------------------------------------------------------
// Note:
// When modify the following wire connections, **ONLY** uncomment the needed
// ports and comment the not-needed ones.
// -------------------------------------------------------------------------
// .dac0_clk_clk_p (dac0_clk_in_p ), // input dac0_clk_clk_p
// .dac0_clk_clk_n (dac0_clk_in_n ), // input dac0_clk_clk_n
.dac2_clk_clk_p (dac2_clk_in_p ), // input dac2_clk_clk_p
.dac2_clk_clk_n (dac2_clk_in_n ), // input dac2_clk_clk_n
.clk_dac0 ( ), // output clk_dac0
.clk_dac1 ( ), // output clk_dac1
.clk_dac2 ( ), // output clk_dac2
.clk_dac3 ( ), // output clk_dac3
// *************************************************************************
// *********** RF-ADC Tile 224 (adc0) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.m0_axis_aclk (sys_clk ), // input m0_axis_aclk
.m0_axis_aresetn (sys_rstn ), // input m0_axis_aresetn
// channel 0 data
.m00_axis_tdata (adc00_data ), // output [15:0]m00_axis_tdata
.m00_axis_tready (adc00_data_ready ), // input m00_axis_tready
.m00_axis_tvalid (adc00_data_valid ), // output m00_axis_tvalid
// channel 1 data
.m01_axis_tdata (adc01_data ), // output [15:0]m01_axis_tdata
.m01_axis_tready (adc01_data_ready ), // input m01_axis_tready
.m01_axis_tvalid (adc01_data_valid ), // output m01_axis_tvalid
// analog input signal, J3 on board
.vin0_01_v_p (adc0_01_in_p ), // input vin0_01_v_p
.vin0_01_v_n (adc0_01_in_n ), // input vin0_01_v_n
// channel 2 data
.m02_axis_tdata (adc02_data ), // output [15:0]m02_axis_tdata
.m02_axis_tready (adc02_data_ready ), // input m02_axis_tready
.m02_axis_tvalid (adc02_data_valid ), // output m02_axis_tvalid
// channel 3 data
.m03_axis_tdata (adc03_data ), // output [15:0]m03_axis_tdata
.m03_axis_tready (adc03_data_ready ), // input m03_axis_tready
.m03_axis_tvalid (adc03_data_valid ), // output m03_axis_tvalid
// analog input signal, J5 on board
.vin0_23_v_p (adc0_23_in_p ), // input vin0_23_v_p
.vin0_23_v_n (adc0_23_in_n ), // input vin0_23_v_n
// *************************************************************************
// *********** RF-ADC Tile 225 (adc1) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.m1_axis_aclk (sys_clk ), // input m1_axis_aclk
.m1_axis_aresetn (sys_rstn ), // input m1_axis_aresetn
// channel 0 data
.m10_axis_tdata (adc10_data ), // output [15:0]m10_axis_tdata
.m10_axis_tready (adc10_data_ready ), // input m10_axis_tready
.m10_axis_tvalid (adc10_data_valid ), // output m10_axis_tvalid
// channel 1 data
.m11_axis_tdata (adc11_data ), // output [15:0]m11_axis_tdata
.m11_axis_tready (adc11_data_ready ), // input m11_axis_tready
.m11_axis_tvalid (adc11_data_valid ), // output m11_axis_tvalid
// analog input signal, J6 on board
.vin1_01_v_p (adc1_01_in_p ), // input vin1_01_v_p
.vin1_01_v_n (adc1_01_in_n ), // input vin1_01_v_n
// channel 2 data
.m12_axis_tdata (adc12_data ), // output [15:0]m12_axis_tdata
.m12_axis_tready (adc12_data_ready ), // input m12_axis_tready
.m12_axis_tvalid (adc12_data_valid ), // output m12_axis_tvalid
// channel 3 data
.m13_axis_tdata (adc13_data ), // output [15:0]m13_axis_tdata
.m13_axis_tready (adc13_data_ready ), // input m13_axis_tready
.m13_axis_tvalid (adc13_data_valid ), // output m13_axis_tvalid
// analog input signal, J7 on board
.vin1_23_v_p (adc1_23_in_p ), // input vin1_23_v_p
.vin1_23_v_n (adc1_23_in_n ), // input vin1_23_v_n
// *************************************************************************
// *********** RF-ADC Tile 226 (adc2) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.m2_axis_aclk (sys_clk ), // input m2_axis_aclk
.m2_axis_aresetn (sys_rstn ), // input m2_axis_aresetn
// channel 0 data
.m20_axis_tdata (adc20_data ), // output [15:0]m20_axis_tdata
.m20_axis_tready (adc20_data_ready ), // input m20_axis_tready
.m20_axis_tvalid (adc20_data_valid ), // output m20_axis_tvalid
// channel 1 data
.m21_axis_tdata (adc21_data ), // output [15:0]m21_axis_tdata
.m21_axis_tready (adc21_data_ready ), // input m21_axis_tready
.m21_axis_tvalid (adc21_data_valid ), // output m21_axis_tvalid
// analog input signal, J8 on board
.vin2_01_v_p (adc2_01_in_p ), // input vin2_01_v_p
.vin2_01_v_n (adc2_01_in_n ), // input vin2_01_v_n
// channel 2 data
.m22_axis_tdata (adc22_data ), // output [15:0]m22_axis_tdata
.m22_axis_tready (adc22_data_ready ), // input m22_axis_tready
.m22_axis_tvalid (adc22_data_valid ), // output m22_axis_tvalid
// channel 3 data
.m23_axis_tdata (adc23_data ), // output [15:0]m23_axis_tdata
.m23_axis_tready (adc23_data_ready ), // input m23_axis_tready
.m23_axis_tvalid (adc23_data_valid ), // output m23_axis_tvalid
// analog input signal, J9 on board
.vin2_23_v_p (adc2_23_in_p ), // input vin2_23_v_p
.vin2_23_v_n (adc2_23_in_n ), // input vin2_23_v_n
// *************************************************************************
// *********** RF-ADC Tile 227 (adc3) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.m3_axis_aclk (sys_clk ), // input m3_axis_aclk
.m3_axis_aresetn (sys_rstn ), // input m3_axis_aresetn
// channel 0 data
.m30_axis_tdata (adc30_data ), // output [15:0]m30_axis_tdata
.m30_axis_tready (adc30_data_ready ), // input m30_axis_tready
.m30_axis_tvalid (adc30_data_valid ), // output m30_axis_tvalid
// channel 1 data
.m31_axis_tdata (adc31_data ), // output [15:0]m31_axis_tdata
.m31_axis_tready (adc31_data_ready ), // input m31_axis_tready
.m31_axis_tvalid (adc31_data_valid ), // output m31_axis_tvalid
// analog input signal, J10 on board
.vin3_01_v_p (adc3_01_in_p ), // input vin3_01_v_p
.vin3_01_v_n (adc3_01_in_n ), // input vin3_01_v_n
// channel 2 data
.m32_axis_tdata (adc32_data ), // output [15:0]m32_axis_tdata
.m32_axis_tready (adc32_data_ready ), // input m32_axis_tready
.m32_axis_tvalid (adc32_data_valid ), // output m32_axis_tvalid
// channel 3 data
.m33_axis_tdata (adc33_data ), // output [15:0]m33_axis_tdata
.m33_axis_tready (adc33_data_ready ), // input m33_axis_tready
.m33_axis_tvalid (adc33_data_valid ), // output m33_axis_tvalid
// analog input signal, J12 on board
.vin3_23_v_p (adc3_23_in_p ), // input vin3_23_v_p
.vin3_23_v_n (adc3_23_in_n ), // input vin3_23_v_n
// *************************************************************************
// *********** RF-DAC Tile 228 (dac0) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.s0_axis_aclk (sys_clk ), // input s0_axis_aclk
.s0_axis_aresetn (sys_rstn ), // input s0_axis_aresetn
// channel 0 data
.s00_axis_tdata (dac00_data ), // input [31:0]s00_axis_tdata
.s00_axis_tready (dac00_data_ready ), // output s00_axis_tready
.s00_axis_tvalid (dac00_data_valid ), // input s00_axis_tvalid
// channel 1 data
// .s01_axis_tdata (dac01_data ), // input [31:0]s01_axis_tdata
// .s01_axis_tready (dac01_data_ready ), // output s01_axis_tready
// .s01_axis_tvalid (dac01_data_valid ), // input s01_axis_tvalid
// analog output signal, J14 on board
.vout00_v_p (dac00_out_p ), // output vout00_v_p
.vout00_v_n (dac00_out_n ), // output vout00_v_n
// channel 2 data
.s02_axis_tdata (dac02_data ), // input [31:0]s02_axis_tdata
.s02_axis_tready (dac02_data_ready ), // output s02_axis_tready
.s02_axis_tvalid (dac02_data_valid ), // input s02_axis_tvalid
// channel 3 data
// .s03_axis_tdata (dac03_data ), // input [31:0]s03_axis_tdata
// .s03_axis_tready (dac03_data_ready ), // output s03_axis_tready
// .s03_axis_tvalid (dac03_data_valid ), // input s03_axis_tvalid
// analog output signal, J16 on board
.vout02_v_p (dac02_out_p ), // output vout02_v_p
.vout02_v_n (dac02_out_n ), // output vout02_v_n
// *************************************************************************
// *********** RF-DAC Tile 229 (dac1) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.s1_axis_aclk (sys_clk ), // input s1_axis_aclk
.s1_axis_aresetn (sys_rstn ), // input s1_axis_aresetn
// channel 0 data
.s10_axis_tdata (dac10_data ), // input [31:0]s10_axis_tdata
.s10_axis_tready (dac10_data_ready ), // output s10_axis_tready
.s10_axis_tvalid (dac10_data_valid ), // input s10_axis_tvalid
// channel 1 data
// .s11_axis_tdata (dac11_data ), // input [31:0]s11_axis_tdata
// .s11_axis_tready (dac11_data_ready ), // output s11_axis_tready
// .s11_axis_tvalid (dac11_data_valid ), // input s11_axis_tvalid
// analog output signal, J17 on board
.vout10_v_p (dac10_out_p ), // output vout10_v_p
.vout10_v_n (dac10_out_n ), // output vout10_v_n
// channel 2 data
.s12_axis_tdata (dac12_data ), // input [31:0]s12_axis_tdata
.s12_axis_tready (dac12_data_ready ), // output s12_axis_tready
.s12_axis_tvalid (dac12_data_valid ), // input s12_axis_tvalid
// channel 3 data
// .s13_axis_tdata (dac13_data ), // input [31:0]s13_axis_tdata
// .s13_axis_tready (dac13_data_ready ), // output s13_axis_tready
// .s13_axis_tvalid (dac13_data_valid ), // input s13_axis_tvalid
// analog output signal, J18 on board
.vout12_v_p (dac12_out_p ), // output vout12_v_p
.vout12_v_n (dac12_out_n ), // output vout12_v_n
// *************************************************************************
// *********** RF-DAC Tile 230 (dac2) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.s2_axis_aclk (sys_clk ), // input s2_axis_aclk
.s2_axis_aresetn (sys_rstn ), // input s2_axis_aresetn
// channel 0 data
.s20_axis_tdata (dac20_data ), // input [31:0]s20_axis_tdata
.s20_axis_tready (dac20_data_ready ), // output s20_axis_tready
.s20_axis_tvalid (dac20_data_valid ), // input s20_axis_tvalid
// channel 1 data
// .s21_axis_tdata (dac21_data ), // input [31:0]s21_axis_tdata
// .s21_axis_tready (dac21_data_ready ), // output s21_axis_tready
// .s21_axis_tvalid (dac21_data_valid ), // input s21_axis_tvalid
// analog output signal, J19 on board
.vout20_v_p (dac20_out_p ), // output vout20_v_p
.vout20_v_n (dac20_out_n ), // output vout20_v_n
// channel 2 data
.s22_axis_tdata (dac22_data ), // input [31:0]s22_axis_tdata
.s22_axis_tready (dac22_data_ready ), // output s22_axis_tready
.s22_axis_tvalid (dac22_data_valid ), // input s22_axis_tvalid
// channel 3 data
// .s23_axis_tdata (dac23_data ), // input [31:0]s23_axis_tdata
// .s23_axis_tready (dac23_data_ready ), // output s23_axis_tready
// .s23_axis_tvalid (dac23_data_valid ), // input s23_axis_tvalid
// analog output signal, J20 on board
.vout22_v_p (dac22_out_p ), // output vout22_v_p
.vout22_v_n (dac22_out_n ), // output vout22_v_n
// *************************************************************************
// *********** RF-DAC Tile 231 (dac3) Digital & Analog Interface ***********
// *************************************************************************
// fabric clock (axi4-stream clock)
.s3_axis_aclk (sys_clk ), // input s3_axis_aclk
.s3_axis_aresetn (sys_rstn ), // input s3_axis_aresetn
// channel 0 data
.s30_axis_tdata (dac30_data ), // input [31:0]s30_axis_tdata
.s30_axis_tready (dac30_data_ready ), // output s30_axis_tready
.s30_axis_tvalid (dac30_data_valid ), // input s30_axis_tvalid
// channel 1 data
// .s31_axis_tdata (dac31_data ), // input [31:0]s31_axis_tdata
// .s31_axis_tready (dac31_data_ready ), // output s31_axis_tready
// .s31_axis_tvalid (dac31_data_valid ), // input s31_axis_tvalid
// analog output signal, J21 on board
.vout30_v_p (dac30_out_p ), // output vout30_v_p
.vout30_v_n (dac30_out_n ), // output vout30_v_n
// channel 2 data
.s32_axis_tdata (dac32_data ), // input [31:0]s32_axis_tdata
.s32_axis_tready (dac32_data_ready ), // output s32_axis_tready
.s32_axis_tvalid (dac32_data_valid ), // input s32_axis_tvalid
// channel 3 data
// .s33_axis_tdata (dac33_data ), // input [31:0]s33_axis_tdata
// .s33_axis_tready (dac33_data_ready ), // output s33_axis_tready
// .s33_axis_tvalid (dac33_data_valid ), // input s33_axis_tvalid
// analog output signal, J23 on board
.vout32_v_p (dac32_out_p ), // output vout32_v_p
.vout32_v_n (dac32_out_n ) // output vout32_v_n
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// Tx Signal ///////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// tx signal mapping
wire [15:0] tx_data_i, tx_data_q;
assign dac00_data = {tx_data_q, tx_data_i};
assign dac02_data = {tx_data_q, tx_data_i};
assign dac10_data = {tx_data_q, tx_data_i};
assign dac12_data = {tx_data_q, tx_data_i};
assign dac20_data = {tx_data_q, tx_data_i};
assign dac22_data = {tx_data_q, tx_data_i};
assign dac30_data = {tx_data_q, tx_data_i};
assign dac32_data = {tx_data_q, tx_data_i};
// transimitter logic
wire [ 1:0] waveform_sel;
wire sweep_on ;
wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk #(
.DATA_WIDTH (16),
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (245_760_000)
) u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (~sys_rstn ), // input rst
.tx_data_i (tx_data_i ), // output [15:0] tx_data_i
.tx_data_q (tx_data_q ), // output [15:0] tx_data_q
// debug ports
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
.sweep_on (sweep_on ), // input sweep_on
.freq_set (freq_set ), // input [31:0] freq_set
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////// Rx Signal ///////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// rx signal mapping
wire [15:0] rx_ch1_i, rx_ch1_q;
wire [15:0] rx_ch2_i, rx_ch2_q;
wire [15:0] rx_ch3_i, rx_ch3_q;
wire [15:0] rx_ch4_i, rx_ch4_q;
wire [15:0] rx_ch5_i, rx_ch5_q;
wire [15:0] rx_ch6_i, rx_ch6_q;
wire [15:0] rx_ch7_i, rx_ch7_q;
wire [15:0] rx_ch8_i, rx_ch8_q;
assign rx_ch1_i = adc00_data;
assign rx_ch1_q = adc01_data;
assign rx_ch2_i = adc02_data;
assign rx_ch2_q = adc03_data;
assign rx_ch3_i = adc10_data;
assign rx_ch3_q = adc11_data;
assign rx_ch4_i = adc12_data;
assign rx_ch4_q = adc13_data;
assign rx_ch5_i = adc20_data;
assign rx_ch5_q = adc21_data;
assign rx_ch6_i = adc22_data;
assign rx_ch6_q = adc23_data;
assign rx_ch7_i = adc30_data;
assign rx_ch7_q = adc31_data;
assign rx_ch8_i = adc32_data;
assign rx_ch8_q = adc33_data;
// receiver logic
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
ila_adc u_ila_adc
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_ch1_i ), // input wire [15:0] probe0
.probe1 (rx_ch1_q ), // input wire [15:0] probe1
.probe2 (rx_ch2_i ), // input wire [15:0] probe2
.probe3 (rx_ch2_q ), // input wire [15:0] probe3
.probe4 (rx_ch3_i ), // input wire [15:0] probe4
.probe5 (rx_ch3_q ), // input wire [15:0] probe5
.probe6 (rx_ch4_i ), // input wire [15:0] probe6
.probe7 (rx_ch4_q ), // input wire [15:0] probe7
.probe8 (rx_ch5_i ), // input wire [15:0] probe8
.probe9 (rx_ch5_q ), // input wire [15:0] probe9
.probe10(rx_ch6_i ), // input wire [15:0] probe10
.probe11(rx_ch6_q ), // input wire [15:0] probe11
.probe12(rx_ch7_i ), // input wire [15:0] probe12
.probe13(rx_ch7_q ), // input wire [15:0] probe13
.probe14(rx_ch8_i ), // input wire [15:0] probe14
.probe15(rx_ch8_q ) // input wire [15:0] probe15
);
ila_dac u_ila_dac
(
.clk (sys_clk ), // input wire clk
.probe0 (tx_data_i ), // input wire [15:0] probe0
.probe1 (tx_data_q ) // input wire [15:0] probe1
);
vio_manual_ctrl u_vio_manual_ctrl
(
.clk (sys_clk ), // input wire clk
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
);
endmodule
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v
+539
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/03/23 20:17:56
// Last Modified Date: 2023/03/10 15:41
// Design Name:
// Module Name: tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
// 算得出。
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_qpsk
#(
parameter DATA_WIDTH = 12, // need to be <= 16
parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
parameter BIT_DATA_LEN = 128,
parameter SQUARE_INTERP = 8,
parameter CLK_FREQ = 245760000 // in Hertz
)
(
input clk ,
input rst ,
output [DATA_WIDTH-1:0] tx_data_i ,
output [DATA_WIDTH-1:0] tx_data_q ,
// debug ports
input [ 1:0] waveform_sel ,
input sweep_on ,
input [31:0] freq_set ,
input [ 1:0] iq_sel ,
input [ 3:0] bb_rshift
);
localparam RCOS_INTERP = 64;
localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////// Data Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// symbol & interpolation counter
reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0;
always @(posedge clk) begin
if (rst) begin
cnt <= 'b0;
end
else begin
cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
always @(posedge clk) begin
if (rst) begin
hrc_data_addr_i <= 'b0;
hrc_data_addr_q <= 'b1;
end
else begin
hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
end
end
// bit data
reg hrc_data_i = 'b0;
reg hrc_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
hrc_data_i <= 'b0;
hrc_data_q <= 'b0;
end
else begin
hrc_data_i <= BIT_DATA[hrc_data_addr_i];
hrc_data_q <= BIT_DATA[hrc_data_addr_q];
end
end
// polarization
wire [ 7:0] hrc_data_polar_i;
wire [ 7:0] hrc_data_polar_q;
assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
// root raised cosine shaping-filter
wire [23:0] hrc_wave_i;
wire [23:0] hrc_wave_q;
hrc_64_12_025 u_hrc_i (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata
);
hrc_64_12_025 u_hrc_q (
.aclk (clk ), // input wire aclk
.s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid
.s_axis_data_tready ( ), // output wire s_axis_data_tready
.s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Square Shaping Filter /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// address
reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data_addr <= 'b0;
end
else
hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
end
// bit data
reg hsq_data = 'b0;
always @(posedge clk) begin
if (rst) begin
hsq_data <= 'b0;
end
else begin
hsq_data <= BIT_DATA[hsq_data_addr];
end
end
// square shaping-filter
reg [17:0] hsq_wave_i ='b0;
reg [17:0] hsq_wave_q ='b0;
always @(posedge clk) begin
if (rst) begin
hsq_wave_i <= 'b0;
hsq_wave_q <= 'b0;
end
else begin
hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
end
end
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Two Tone Siganl ////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// cosine wave with freq of 1 MHz
wire signed [7:0] cos_1m;
wire signed [7:0] sin_1m;
dds_32b_8b u_dds_1m
(
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata
);
// two-tone signal
reg signed [16:0] two_tone_wave_i = 'b0;
reg signed [16:0] two_tone_wave_q = 'b0;
always @(posedge clk) begin
if (rst) begin
two_tone_wave_i <= 'b0;
two_tone_wave_q <= 'b0;
end
else begin
two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
end
end
////////////////////////////////////////////////////////////////////////////////
///////////////////// Waveform Selection & Hopping Control /////////////////////
////////////////////////////////////////////////////////////////////////////////
// baseband signal select
reg [17:0] baseband_sel_i = 'b0;
reg [17:0] baseband_sel_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_sel_i <= 'b0;
baseband_sel_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
2'd1: begin
baseband_sel_i <= hsq_wave_i[17:0];
baseband_sel_q <= hsq_wave_q[17:0];
end
2'd2: begin
baseband_sel_i <= 18'b01_1111_1111_1111_1111;
baseband_sel_q <= 18'b0;
end
2'd3: begin
baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
end
default: begin
baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
end
endcase
end
end
// hopping control, 3750hop/s
reg [23:0] sweep_rom_addr = 'b0;
wire [31:0] freq_sweep;
always @(posedge clk) begin
if (rst) begin
sweep_rom_addr <= 'b0;
end
else if (sweep_on) begin
sweep_rom_addr <= sweep_rom_addr + 24'b1;
end
else begin
sweep_rom_addr <= 'b0;
end
end
hop_rom u_sweep_rom
(
.clka (clk ), // input wire clka
.addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra
.douta (freq_sweep ) // output wire [31 : 0] douta
);
// choose the actual frequency word
reg [31:0] freq_word = 'b0;
always @(posedge clk) begin
if (rst) begin
freq_word <= 'b0;
end
else if (sweep_on) begin
// frequency sweep
freq_word <= freq_sweep;
end
else begin
// normal operation
freq_word <= freq_set;
end
end
// baseband frequency shift carrier generation
wire [ 7:0] cos_dds;
wire [ 7:0] sin_dds;
reg [ 7:0] cos = 'b0;
reg [ 7:0] sin = 'b0;
dds_32b_8b u_dds_bb_shift (
.aclk (clk ), // input wire aclk
.s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid
.m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata
);
always @(posedge clk) begin
if (rst) begin
cos <= 'b0;
sin <= 'b0;
end
else if (freq_word == 'b0) begin
// to make sure the carriers stay at the right position when freq = 0
cos <= 8'b0111_1111;
sin <= 8'b0111_1111;
end
else begin
cos <= cos_dds;
sin <= sin_dds;
end
end
// baseband frequency shift modulation
wire [47:0] mod_cmpy_a;
wire [15:0] mod_cmpy_b;
wire [63:0] mod_cmpy_out;
wire [26:0] baseband_mult_i;
wire [26:0] baseband_mult_q;
assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
assign mod_cmpy_b = {-sin,cos};
assign baseband_mult_i = mod_cmpy_out[58:32];
assign baseband_mult_q = mod_cmpy_out[26: 0];
cmpy_18x8 u_cmpy_18x8
(
.aclk (clk ), // input wire aclk
.s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata
.s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid
.s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata
.m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata
);
// truncate to 16-bit
reg signed [15:0] baseband_i = 'b0;
reg signed [15:0] baseband_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_i <= 'b0;
baseband_q <= 'b0;
end
else begin
case (waveform_sel[1:0])
2'd0: begin
// scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
end
2'd1: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
end
2'd2: begin
baseband_i <= baseband_mult_i[24:9];
baseband_q <= baseband_mult_q[24:9];
end
2'd3: begin
baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
end
default: begin
// scale rasied-cosine-shaped bpsk signal by 1.125
baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
end
endcase
end
end
// iq selection & baseband right shift
reg signed [15:0] baseband_data_i = 'b0;
reg signed [15:0] baseband_data_q = 'b0;
always @(posedge clk) begin
if (rst) begin
baseband_data_i <= 'b0;
baseband_data_q <= 'b0;
end
else begin
// inphase selection
if (iq_sel[1]) begin
baseband_data_i <= baseband_i >>> bb_rshift;
end
else begin
baseband_data_i <= 'b0;
end
// quadrature selection
if (iq_sel[0]) begin
baseband_data_q <= baseband_q >>> bb_rshift;
end
else begin
baseband_data_q <= 'b0;
end
end
end
// output data to ports
assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/12/08 12:43:46
// Design Name:
// Module Name: tb_tx_qpsk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_tx_qpsk;
// reg clk = 1'b0 ;
// reg rst = 1'b1 ;
// reg tx_on = 1'b1 ;
// reg [31:0] freq_set ;
// reg [ 1:0] waveform_sel = 2'b00;
// reg [ 1:0] iq_sel = 2'b11 ;
// wire [11:0] tx_data_i ;
// wire [11:0] tx_data_q ;
// reg [ 3:0] bb_rshift = 5'b0 ;
// tx_qpsk u_tx_qpsk
// (
// .clk (clk ),
// .rst (rst ),
// .tx_data_i (tx_data_i ),
// .tx_data_q (tx_data_q ),
// .waveform_sel (waveform_sel ),
// .sweep_on (1'b0 ),
// // .freq_set (32'd447392426 ),
// .freq_set (32'd0 ),
// .iq_sel (iq_sel ),
// .bb_rshift (bb_rshift )
// );
// initial begin
// #102
// rst = 1'b0;
// // freq_set = 32'd873813333;
// // waveform_sel = 2'b00;
// // bb_rshift = 5'd0;
// // #5000
// // bb_rshift = 5'd1;
// // #5000
// // bb_rshift = 5'd2;
// // #5000
// // bb_rshift = 5'd3;
// // #5000
// // bb_rshift = 5'd4;
// // #5000
// // bb_rshift = 5'd5;
// // #5000
// // bb_rshift = 5'd6;
// // #5000
// // bb_rshift = 5'd7;
// // #5000
// // bb_rshift = 5'd8;
// // #5000
// // bb_rshift = 5'd9;
// // #5000
// // bb_rshift = 5'd14;
// // #5000
// // bb_rshift = 5'd15;
// // #5000
// // bb_rshift = 5'd16;
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b100;
// // #7777
// // freq_set = 32'd536870912;
// // func_sel = 3'b010;
// // #7777
// // freq_set = 32'd0;
// // func_sel = 3'b010;
// // freq_set = 32'd536870912;
// // iq_sel = 2'b00;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b01;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b10;
// // #7777
// // freq_set = 32'd536870912;
// // iq_sel = 2'b11;
// end
// always #5 clk = ~clk;
// // integer i;
// // integer w_file;
// // initial begin
// // w_file = $fopen("D:\\qpsk_josh.txt","w");
// // for (i = 0; i <= 35000; i = i + 1) begin
// // wait(clk);
// // #10;
// // $fdisplay(w_file,"%d %d",$signed(tx_data_i),
// // $signed(tx_data_q));
// // if (i == 35000) begin
// // $fclose(w_file);
// // $stop;
// // end
// // end
// // end
// endmodule
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="ila_dac"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="vio_manual_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl" RelGenDir="$PGENDIR/vio_manual_ctrl">
<File Path="$PSRCDIR/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci"/>
<Attr Name="ImportTime" Val="1719371236"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_manual_ctrl"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_spi_engine_execution_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_spi_engine_execution_0_0" RelGenDir="$PGENDIR/system_bd_spi_engine_execution_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_spi_engine_execution_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_usp_rf_data_converter_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_usp_rf_data_converter_0_0" RelGenDir="$PGENDIR/system_bd_usp_rf_data_converter_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_usp_rf_data_converter_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
<Config>
<Option Name="TopModule" Val="system_bd_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_xpm_cdc_gen_pl_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xpm_cdc_gen_pl_sysref_0" RelGenDir="$PGENDIR/system_bd_xpm_cdc_gen_pl_sysref_0">
<Config>
<Option Name="TopModule" Val="system_bd_xpm_cdc_gen_pl_sysref_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_xpm_cdc_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xpm_cdc_gen_0_0" RelGenDir="$PGENDIR/system_bd_xpm_cdc_gen_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_xpm_cdc_gen_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_rst_ps8_0_96M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_rst_ps8_0_96M_0" RelGenDir="$PGENDIR/system_bd_rst_ps8_0_96M_0">
<Config>
<Option Name="TopModule" Val="system_bd_rst_ps8_0_96M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
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<Config>
<Option Name="TopModule" Val="system_bd_clk_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_util_ds_buf_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_0_0" RelGenDir="$PGENDIR/system_bd_util_ds_buf_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_util_ds_buf_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_util_ds_buf_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_1_0" RelGenDir="$PGENDIR/system_bd_util_ds_buf_1_0">
<Config>
<Option Name="TopModule" Val="system_bd_util_ds_buf_1_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_util_ds_buf_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_0_1" RelGenDir="$PGENDIR/system_bd_util_ds_buf_0_1">
<Config>
<Option Name="TopModule" Val="system_bd_util_ds_buf_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_zynq_ultra_ps_e_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_zynq_ultra_ps_e_0_1" RelGenDir="$PGENDIR/system_bd_zynq_ultra_ps_e_0_1">
<Config>
<Option Name="TopModule" Val="system_bd_zynq_ultra_ps_e_0_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
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<Option Name="CompiledLib" Val="0"/>
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<Simulator Name="VCS">
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<Simulator Name="Riviera">
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/.gitignore
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>dj_47dr_basic</name>
<comment>Created by Vitis v2024.1</comment>
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<project>dj_47dr_platform</project>
</projects>
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/_ide/bitstream/system_top.bit
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/_ide/psinit/psu_init.tcl
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/README.md
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# README.md
> Vivado Project Name: dj_47dr_lmx
>
> Vitis Project Name: dj_47dr_basic
>
> Board: RFSOC_47DR_Z7045
>
> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmx2594(u67), lmx2594(u68)
>
> Date: 2024/07/05
>
> Archiver: Josh Gao
1. 注意事项
本工程启用了动态 DDR 配置，依赖于 FSBL 启动，在启动时 FSBL 会使用 I2C 读取 DDR 的 SPD EEPROM 获得 DDR 参数，并初始化 DDR 控制器。
由于原理图与 Xilinx 开发板 I2C Mux Slave 连接不一致，FSBL 已将 I2C Mux 的 Slave 选择改为 `0x04`。若重新建立 PS 工程，注意修改 FSBL，否则可能无法正常启动。
2. 实现的功能
- 配置了 LMK04828，使用 10 MHz 输入时钟和 122.88 MHz VCXO 完成配置，PLL2 锁定，输出时钟频率为 245.76 MHz。
- 配置了两片 LMK2594，RF 部分使用外部采样时钟，采样率为 4.9152 Gbps。
- 初始化了 RF Data Converter，自发自收测试 ch5 发 ch5 收正常，信号功率和 EVM 等未测量。
- 降低 SPI 速率后 LMX2594 回读正常。
3. 存在的问题
- LMK04828 PLL1 锁定时间较长（约 1 分钟），单独配置 LMK04828 时同样存在该问题。
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/adc/ad9694/ad9694.c
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/***************************************************************************//**
* @file ad9694.c
* @brief Implementation of AD9680 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include "ad9694.h"
#include "../../../include/error.h"
/***************************************************************************//**
* @brief ad9694_read
*******************************************************************************/
int32_t ad9694_read(struct ad9694_dev *dev,
uint16_t reg_addr,
uint8_t *reg_data)
{
uint8_t tx_buf[2];
uint8_t rx_buf[1];
int32_t ret;
tx_buf[0] = 0x80 | (reg_addr >> 8);
tx_buf[1] = reg_addr & 0xFF;
ret = spi_write_and_read_3wire(dev->spi_desc,
tx_buf, rx_buf, 2, 1);
*reg_data = rx_buf[0];
return ret;
}
/***************************************************************************//**
* @brief ad9694_write
*******************************************************************************/
int32_t ad9694_write(struct ad9694_dev *dev,
uint16_t reg_addr,
uint8_t reg_data)
{
uint8_t buf[3];
int32_t ret;
buf[0] = reg_addr >> 8;
buf[1] = reg_addr & 0xFF;
buf[2] = reg_data;
ret = spi_write_and_read_3wire(dev->spi_desc,
buf, NULL, 3, 0);
return ret;
}
/***************************************************************************//**
* @brief ad9694_init
*******************************************************************************/
int32_t ad9694_init(struct ad9694_dev **device,
const struct ad9694_init_param *init_param)
{
int ret = SUCCESS;
struct ad9694_dev *dev;
dev = (struct ad9694_dev *)malloc(sizeof(*dev));
if (!dev)
return FAILURE;
/* SPI */
ret = spi_init(&dev->spi_desc, init_param->spi_init);
*device = dev;
return ret;
}
/***************************************************************************//**
* @brief Free the resources allocated by ad9694_setup().
*
* @param dev - The device structure.
*
* @return SUCCESS in case of success, negative error code otherwise.
*******************************************************************************/
int32_t ad9694_remove(struct ad9694_dev *dev)
{
int32_t ret;
ret = spi_remove(dev->spi_desc);
free(dev);
return ret;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/adc/ad9694/ad9694.h
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/***************************************************************************//**
* @file ad9694.h
* @brief Header file of AD9694 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef AD9694_H_
#define AD9694_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../../include/delay.h"
#include "../../../include/spi.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A 0x0000
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B 0x0001
#define AD9694_REG_CH_MAP_CHIP_CONF 0x0002
#define AD9694_REG_PAIR_MAP_CHIP_TYPE 0x0003
#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB 0x0004
#define AD9694_REG_PAIR_MAP_CHIP_GRADE 0x0006
#define AD9694_REG_PAIR_MAP_DEV_INDEX 0x0008
#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX 0x0009
#define AD9694_REG_PAIR_MAP_SCRATCH_PAD 0x000A
#define AD9694_REG_PAIR_MAP_SPI_REVISION 0x000B
#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB 0x000C
#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB 0x000D
#define AD9694_REG_CH_MAP_CHIP_PD_PIN 0x003F
#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1 0x0040
#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL 0x0108
#define AD9694_REG_CH_MAP_CLK_DIV_PHASE 0x0109
#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL 0x010A
#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL 0x0110
#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY 0x0111
#define AD9694_REG_CH_MAP_CLK_FINE_DELAY 0x0112
#define AD9694_REG_CLK_DETN_CTRL 0x011A
#define AD9694_REG_PAIR_MAP_CLK_STAT 0x011B
#define AD9694_REG_CLK_DCS_CTRL_1 0x011C
#define AD9694_REG_CLK_DCS_CTRL_2 0x011E
#define AD9694_REG_CLK_DCS_CTRL_3 0x011F
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1 0x0120
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2 0x0121
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4 0x0123
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1 0x0128
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2 0x0129
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3 0x012A
#define AD9694_REG_PAIR_MAP_CHIP_SYNC 0x01FF
#define AD9694_REG_PAIR_MAP_CHIP_MODE 0x0200
#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO 0x0201
#define AD9694_REG_CH_MAP_CUSTOM_OFFSET 0x0228
#define AD9694_REG_CH_MAP_FD_CTRL 0x0245
#define AD9694_REG_CH_MAP_FD_UT_LSB 0x0247
#define AD9694_REG_CH_MAP_FD_UT_MSB 0x0248
#define AD9694_REG_CH_MAP_FD_LT_LSB 0x0249
#define AD9694_REG_CH_MAP_FD_LT_MSB 0x024A
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB 0x024B
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB 0x024C
#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL 0x026F
#define AD9694_REG_CH_MAP_SIG_MON_CTRL 0x0270
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0 0x0271
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1 0x0272
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2 0x0273
#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL 0x0274
#define AD9694_REG_CH_MAP_SIG_MON_STAT_0 0x0275
#define AD9694_REG_CH_MAP_SIG_MON_STAT_1 0x0276
#define AD9694_REG_CH_MAP_SIG_MON_STAT_2 0x0277
#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT 0x0278
#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL 0x0279
#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL 0x027A
#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL 0x0300
#define AD9694_REG_PAIR_MAP_DDC_0_CTRL 0x0310
#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL 0x0311
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0 0x0314
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1 0x0315
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2 0x0316
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3 0x0317
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4 0x0318
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5 0x031A
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0 0x031D
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1 0x031E
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2 0x031F
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3 0x0320
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4 0x0321
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5 0x0322
#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE 0x0327
#define AD9694_REG_PAIR_MAP_DDC_1_CTRL 0x0330
#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL 0x0331
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0 0x0334
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1 0x0335
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2 0x0336
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3 0x0337
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4 0x0338
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5 0x033A
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0 0x033D
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1 0x033E
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2 0x033F
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3 0x0340
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4 0x0341
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5 0x0342
#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE 0x0347
#define AD9694_REG_CH_MAP_TEST_MODE_CTRL 0x0550
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB 0x0551
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB 0x0552
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB 0x0553
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB 0x0554
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB 0x0555
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB 0x0556
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB 0x0557
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB 0x0558
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0 0x0559
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1 0x055A
#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE 0x0561
#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL 0x0564
#define AD9694_REG_JESD204B_MAP_PLL_CTRL 0x056E
#define AD9694_REG_JESD204B_MAP_PLL_STAT 0x056F
#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF 0x0570
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1 0x0571
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2 0x0572
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3 0x0573
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4 0x0574
#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET 0x0578
#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF 0x0580
#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF 0x0581
#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF 0x0583
#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF 0x0585
#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF 0x058B
#define AD9694_REG_JESD204B_MAP_JTX_F_CONF 0x058C
#define AD9694_REG_JESD204B_MAP_JTX_K_CONF 0x058D
#define AD9694_REG_JESD204B_MAP_JTX_M_CONF 0x058E
#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF 0x058F
#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF 0x0590
#define AD9694_REG_JESD204B_MAP_JTX_S_CONF 0x0591
#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF 0x0592
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF 0x05A0
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF 0x05A1
#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD 0x05B0
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1 0x05B2
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2 0x05B3
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0 0x05C0
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1 0x05C1
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0 0x05C4
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1 0x05C6
#define AD9694_REG_LARGE_DITHER_CTRL 0x0922
#define AD9694_REG_PLL_CAL 0x1222
#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST 0x1228
#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL 0x1262
#define AD9694_REG_DC_OFFSET_CAL_CTRL 0x0701
#define AD9694_REG_DC_OFFSET_CAL_CTRL_2 0x073B
#define AD9694_REG_PAIR_MAP_VREF_CTRL 0x18A6
#define AD9694_REG_EXT_VCM_BUF_CTRL_1 0x18E0
#define AD9694_REG_EXT_VCM_BUF_CTRL_2 0x18E1
#define AD9694_REG_EXT_VCM_BUF_CTRL_3 0x18E2
#define AD9694_REG_EXT_VCM_BUF_CTRL 0x18E3
#define AD9694_REG_TEMP_DIODE_EXPORT 0x18E6
#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL 0x1908
#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE 0x1910
#define AD9694_REG_CH_MAP_BUF_CTRL_1 0x1A4C
#define AD9694_REG_CH_MAP_BUF_CTRL_2 0x1A4D
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
struct ad9694_dev {
/* SPI */
spi_desc *spi_desc;
};
struct ad9694_init_param {
/* SPI */
spi_init_param *spi_init;
};
struct ad9694_config {
uint16_t addr;
uint8_t value;
};
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
int32_t ad9694_read(struct ad9694_dev *dev,
uint16_t reg_addr,
uint8_t *reg_data);
int32_t ad9694_write(struct ad9694_dev *dev,
uint16_t reg_addr,
uint8_t reg_data);
int32_t ad9694_init(struct ad9694_dev **device,
const struct ad9694_init_param *init_param);
int32_t ad9694_remove(struct ad9694_dev *dev);
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/gpio.c
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/***************************************************************************//**
* @file gpio.c
* @brief Implementation of the GPIO Interface
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
********************************************************************************
* Copyright 2020(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include <inttypes.h>
#include <stdlib.h>
#include "../../include/gpio.h"
#include "../../include/error.h"
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief Obtain the GPIO decriptor.
* @param desc - The GPIO descriptor.
* @param param - GPIO Initialization parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get(struct gpio_desc **desc,
const struct gpio_init_param *param)
{
if (!param)
return FAILURE;
if ((param->platform_ops->gpio_ops_get(desc, param)))
return FAILURE;
(*desc)->platform_ops = param->platform_ops;
return SUCCESS;
}
/**
* @brief Get the value of an optional GPIO.
* @param desc - The GPIO descriptor.
* @param param - GPIO Initialization parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get_optional(struct gpio_desc **desc,
const struct gpio_init_param *param)
{
if (!param || (param->number == -1)) {
*desc = NULL;
return SUCCESS;
}
if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
return FAILURE;
(*desc)->platform_ops = param->platform_ops;
return SUCCESS;
}
/**
* @brief Free the resources allocated by gpio_get().
* @param desc - The GPIO descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_remove(struct gpio_desc *desc)
{
if (desc)
return desc->platform_ops->gpio_ops_remove(desc);
else
return SUCCESS;
}
/**
* @brief Enable the input direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_direction_input(struct gpio_desc *desc)
{
if (desc)
return desc->platform_ops->gpio_ops_direction_input(desc);
else
return SUCCESS;
}
/**
* @brief Enable the output direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_direction_output(struct gpio_desc *desc,
uint8_t value)
{
if (desc)
return desc->platform_ops->
gpio_ops_direction_output(desc, value);
else
return SUCCESS;
}
/**
* @brief Get the direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param direction - The direction.
* Example: GPIO_OUT
* GPIO_IN
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get_direction(struct gpio_desc *desc,
uint8_t *direction)
{
if (desc)
return desc->platform_ops->
gpio_ops_get_direction(desc, direction);
else
return SUCCESS;
}
/**
* @brief Set the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_set_value(struct gpio_desc *desc,
uint8_t value)
{
if (desc)
return desc->platform_ops->gpio_ops_set_value(desc, value);
else
return SUCCESS;
}
/**
* @brief Get the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t gpio_get_value(struct gpio_desc *desc,
uint8_t *value)
{
if (desc)
return desc->platform_ops->gpio_ops_get_value(desc, value);
else
return SUCCESS;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/irq.c
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/***************************************************************************//**
* @file irq.c
* @brief Implementation of the IRQ Interface
* @author Andrei Porumb (andrei.porumb@analog.com)
********************************************************************************
* Copyright 2021(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include <inttypes.h>
#include <stdlib.h>
#include "../../include/irq.h"
#include "../../include/error.h"
/**
* @brief Initialize the IRQ interrupts.
* @param desc - The IRQ descriptor.
* @param param - The structure that contains the IRQ parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
const struct irq_init_param *param)
{
if (!param)
return FAILURE;
if ((param->platform_ops->init(desc, param)))
return FAILURE;
(*desc)->platform_ops = param->platform_ops;
return SUCCESS;
}
/**
* @brief Free the resources allocated by irq_ctrl_init().
* @param desc - The SPI descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
{
return desc->platform_ops->remove(desc);
}
/**
* @brief Register a callback to handle the irq events.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @param callback_desc - Callback descriptor
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
struct callback_desc *callback_desc)
{
return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
}
/**
* @brief Unregisters a generic IRQ handling function.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
return desc->platform_ops->unregister(desc, irq_id);
}
/**
* @brief Enable global interrupts.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_global_enable(struct irq_ctrl_desc *desc)
{
return desc->platform_ops->global_enable(desc);
}
/**
* @brief Disable global interrupts.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_global_disable(struct irq_ctrl_desc *desc)
{
return desc->platform_ops->global_disable(desc);
}
/**
* @brief Set interrupt trigger level.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @param trig - New trigger level for the interrupt.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
enum irq_trig_level trig)
{
if(desc->platform_ops->trigger_level_set)
return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
else
return ENOSYS;
}
/**
* @brief Enable specific interrupt.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
return desc->platform_ops->enable(desc, irq_id);
}
/**
* @brief Disable specific interrupt.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
return desc->platform_ops->disable(desc, irq_id);
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/spi.c
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/***************************************************************************//**
* @file spi.c
* @brief Implementation of the SPI Interface
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
********************************************************************************
* Copyright 2020(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include <inttypes.h>
#include <stdlib.h>
#include <string.h>
#include "../../include/spi.h"
#include "../../include/error.h"
/**
* @brief Initialize the SPI communication peripheral.
* @param desc - The SPI descriptor.
* @param param - The structure that contains the SPI parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_init(struct spi_desc **desc,
const struct spi_init_param *param)
{
if (!param)
return FAILURE;
if ((param->platform_ops->init(desc, param)))
return FAILURE;
(*desc)->platform_ops = param->platform_ops;
return SUCCESS;
}
/**
* @brief Free the resources allocated by spi_init().
* @param desc - The SPI descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_remove(struct spi_desc *desc)
{
return desc->platform_ops->remove(desc);
}
/**
* @brief Write and read data to/from SPI.
* @param desc - The SPI descriptor.
* @param data - The buffer with the transmitted/received data.
* @param bytes_number - Number of bytes to write/read.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_write_and_read(struct spi_desc *desc,
uint8_t *data,
uint16_t bytes_number)
{
return desc->platform_ops->write_and_read(desc, data, bytes_number);
}
/**
* @brief Write and read data to/from SPI in 3 wire mode.
* @param desc - The SPI descriptor.
* @param write_data - The buffer with the transmitted data.
* @param read_data - The buffer with the received data.
* @param write_bytes_number - Number of bytes to write.
* @param read_bytes_number - Number of bytes to read.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t spi_write_and_read_3wire(struct spi_desc *desc,
uint8_t *write_data,
uint8_t *read_data,
uint16_t write_bytes_number,
uint16_t read_bytes_number)
{
int ret;
if(desc->platform_ops->write_and_read_3wire != NULL){
return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
write_bytes_number, read_bytes_number);
}
else{
return FAILURE;
}
}
/**
* @brief Iterate over head list and send all spi messages
* @param desc - The SPI descriptor.
* @param msgs - Array of messages.
* @param len - Number of messages in the array.
* @return SUCCESS in case of success, negativ error code otherwise.
*/
int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
{
int32_t ret;
uint32_t i;
if (!desc || !desc->platform_ops)
return -EINVAL;
if (desc->platform_ops->transfer)
return desc->platform_ops->transfer(desc, msgs, len);
for (i = 0; i < len; i++) {
if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
return -EINVAL;
ret = spi_write_and_read(desc, msgs[i].rx_buff,
msgs[i].bytes_number);
if (IS_ERR_VALUE(ret))
return ret;
}
return SUCCESS;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c
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/***************************************************************************//**
* @file axi_dmac.c
* @brief Driver for the Analog Devices AXI-DMAC core.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2018(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <stdint.h>
#include "../../../include/axi_io.h"
#include "../../../include/error.h"
#include "../axi_dmac/axi_dmac.h"
/***************************************************************************//**
* @brief dma_isr
*******************************************************************************/
void axi_dmac_default_isr(void *instance)
{
struct axi_dmac *dmac = (struct axi_dmac *)instance;
uint32_t remaining_size, burst_size;
uint32_t reg_val;
/* Get interrupt sources and clear interrupts. */
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
remaining_size = dmac->big_transfer.size -
dmac->big_transfer.size_done;
burst_size = (remaining_size <= dmac->transfer_max_size) ?
remaining_size : dmac->transfer_max_size;
dmac->big_transfer.size_done += burst_size;
dmac->big_transfer.address += burst_size;
switch (dmac->direction) {
case DMA_DEV_TO_MEM:
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
dmac->big_transfer.address);
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
break;
case DMA_MEM_TO_DEV:
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
dmac->big_transfer.address);
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
break;
default:
return; // Other directions are not supported yet
}
/* The current transfer was started and a new one is queued. */
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
burst_size);
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
}
if (reg_val & AXI_DMAC_IRQ_EOT) {
dmac->big_transfer.transfer_done = true;
dmac->big_transfer.address = 0;
dmac->big_transfer.size = 0;
dmac->big_transfer.size_done = 0;
}
}
/***************************************************************************//**
* @brief axi_dmac_read
*******************************************************************************/
int32_t axi_dmac_read(struct axi_dmac *dmac,
uint32_t reg_addr,
uint32_t *reg_data)
{
axi_io_read(dmac->base, reg_addr, reg_data);
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_write
*******************************************************************************/
int32_t axi_dmac_write(struct axi_dmac *dmac,
uint32_t reg_addr,
uint32_t reg_data)
{
axi_io_write(dmac->base, reg_addr, reg_data);
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_transfer_nonblock
*******************************************************************************/
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
uint32_t address, uint32_t size)
{
uint32_t reg_val;
if (size == 0)
return SUCCESS; /* nothing to do */
axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, &reg_val);
if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
}
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
if (!(reg_val & 1)) {
switch (dmac->direction) {
case DMA_DEV_TO_MEM:
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
break;
case DMA_MEM_TO_DEV:
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
break;
default:
return FAILURE; // Other directions are not supported yet
}
if ((size - 1) > dmac->transfer_max_size) {
dmac->big_transfer.address = address;
dmac->big_transfer.size = size - 1;
dmac->big_transfer.size_done = dmac->transfer_max_size;
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
dmac->transfer_max_size);
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
} else {
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
size - 1);
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
}
} else {
return FAILURE;
}
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_is_transfer_ready
*******************************************************************************/
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
{
*rdy = dmac->big_transfer.transfer_done;
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_transfer
*******************************************************************************/
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
uint32_t address, uint32_t size)
{
uint32_t transfer_id;
uint32_t reg_val;
uint32_t timeout = 0;
if (size == 0)
return SUCCESS; /* nothing to do */
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
switch (dmac->direction) {
case DMA_DEV_TO_MEM:
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
break;
case DMA_MEM_TO_DEV:
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
break;
default:
return FAILURE; // Other directions are not supported yet
}
if ((size - 1) > dmac->transfer_max_size) {
dmac->big_transfer.address = address;
dmac->big_transfer.size = size - 1;
dmac->big_transfer.size_done = dmac->transfer_max_size;
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
dmac->transfer_max_size);
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
while(!dmac->big_transfer.transfer_done) {
timeout++;
if (timeout == UINT32_MAX)
return FAILURE;
}
dmac->big_transfer.address = 0;
dmac->big_transfer.size = 0;
dmac->big_transfer.size_done = 0;
return SUCCESS;
}
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
if (dmac->flags & DMA_CYCLIC)
return SUCCESS;
/* Wait until the new transfer is queued. */
do {
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
} while(reg_val == 1);
/* Wait until the current transfer is completed. */
do {
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
break;
} while(!dmac->big_transfer.transfer_done);
if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
/* Wait until the transfer with the ID transfer_id is completed. */
do {
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, &reg_val);
} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_init
*******************************************************************************/
int32_t axi_dmac_init(struct axi_dmac **dmac_core,
const struct axi_dmac_init *init)
{
struct axi_dmac *dmac;
dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
if (!dmac)
return FAILURE;
dmac->name = init->name;
dmac->base = init->base;
dmac->direction = init->direction;
dmac->flags = init->flags;
dmac->transfer_max_size = -1;
dmac->big_transfer.address = 0;
dmac->big_transfer.size = 0;
dmac->big_transfer.size_done = 0;
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
*dmac_core = dmac;
return SUCCESS;
}
/***************************************************************************//**
* @brief axi_dmac_remove
*******************************************************************************/
int32_t axi_dmac_remove(struct axi_dmac *dmac)
{
if(!dmac)
return FAILURE;
free(dmac);
return SUCCESS;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h
+124
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@@ -0,0 +1,124 @@
/***************************************************************************//**
* @file axi_dmac.h
* @brief Driver for the Analog Devices AXI-DMAC core.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2018(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef AXI_DMAC_H_
#define AXI_DMAC_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../../include/util.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define AXI_DMAC_REG_IRQ_MASK 0x80
#define AXI_DMAC_REG_IRQ_PENDING 0x84
#define AXI_DMAC_IRQ_SOT BIT(0)
#define AXI_DMAC_IRQ_EOT BIT(1)
#define AXI_DMAC_REG_CTRL 0x400
#define AXI_DMAC_CTRL_ENABLE BIT(0)
#define AXI_DMAC_CTRL_PAUSE BIT(1)
#define AXI_DMAC_REG_TRANSFER_ID 0x404
#define AXI_DMAC_REG_START_TRANSFER 0x408
#define AXI_DMAC_REG_FLAGS 0x40c
#define AXI_DMAC_REG_DEST_ADDRESS 0x410
#define AXI_DMAC_REG_SRC_ADDRESS 0x414
#define AXI_DMAC_REG_X_LENGTH 0x418
#define AXI_DMAC_REG_Y_LENGTH 0x41c
#define AXI_DMAC_REG_DEST_STRIDE 0x420
#define AXI_DMAC_REG_SRC_STRIDE 0x424
#define AXI_DMAC_REG_TRANSFER_DONE 0x428
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
enum dma_direction {
DMA_DEV_TO_MEM,
DMA_MEM_TO_DEV
};
enum dma_flags {
DMA_CYCLIC = 1,
DMA_LAST = 2
};
struct axi_dma_transfer {
uint32_t size;
uint32_t address;
uint32_t size_done;
volatile bool transfer_done;
};
struct axi_dmac {
const char *name;
uint32_t base;
enum dma_direction direction;
uint32_t flags;
uint32_t transfer_max_size;
volatile struct axi_dma_transfer big_transfer;
};
struct axi_dmac_init {
const char *name;
uint32_t base;
enum dma_direction direction;
uint32_t flags;
};
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
void axi_dmac_default_isr(void *instance);
int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
uint32_t *reg_data);
int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
uint32_t reg_data);
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
uint32_t address, uint32_t size);
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
uint32_t address, uint32_t size);
int32_t axi_dmac_init(struct axi_dmac **adc_core,
const struct axi_dmac_init *init);
int32_t axi_dmac_remove(struct axi_dmac *dmac);
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c
+978
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@@ -0,0 +1,978 @@
/*******************************************************************************
* @file spi_engine.c
* @brief Core implementation of the SPI Engine Driver.
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
/* In debug mode the printf function used in displaying the messages is causing
significant delays */
//#define DEBUG_LEVEL 2
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <sleep.h>
#include <inttypes.h>
#include "spi_engine.h"
#include "../axi_dmac/axi_dmac.h"
#include "../../../include/axi_io.h"
#include "../../../include/error.h"
/**
* @brief Spi engine platform specific SPI platform ops structure
*/
const struct spi_platform_ops spi_eng_platform_ops = {
.init = &spi_engine_init,
.write_and_read = &spi_engine_spi_write_and_read,
.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
.remove = &spi_engine_remove
};
/******************************************************************************/
/***************************** Static variables *******************************/
/******************************************************************************/
/**
* @brief Static variable used to sync transfers
*
*/
static uint8_t _sync_id = 0x01;
/******************************************************************************/
/************************** Functions Implementation **************************/
/******************************************************************************/
/**
* @brief Write SPI Engine's axi registers
*
* @param desc Decriptor containing SPI Engine's parameters
* @param reg_addr The address of the SPI Engine's axi register where the data
* will be written
* @param reg_data Data that will be written
* @return int32_t This function allways returns SUCCESS
*/
int32_t spi_engine_write(struct spi_engine_desc *desc,
uint32_t reg_addr,
uint32_t reg_data)
{
axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
return SUCCESS;
}
/**
* @brief Read SPI Engine's axi registers
*
* @param desc Decriptor containing SPI Engine's parameters
* @param reg_addr The address of the SPI Engine's axi register from where the
* data where the data will be read
* @param reg_data Pointer where the read that will be stored
* @return int32_t This function allways returns SUCCESS
*/
int32_t spi_engine_read(struct spi_engine_desc *desc,
uint32_t reg_addr,
uint32_t *reg_data)
{
axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
return SUCCESS;
}
/**
* @brief Set width of the transferred word over SPI
*
* @param desc Decriptor containing SPI interface parameters
* @param data_width The desired data width
* The supported values are:
* - 8
* - 16
* - 24
* - 32
*/
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
uint8_t data_width)
{
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
if (data_width > desc_extra->max_data_width)
desc_extra->data_width = desc_extra->max_data_width;
else
desc_extra->data_width = data_width;
return SUCCESS;
}
/**
* @brief Set SPI engine clock frequency
*
* @param desc Decriptor containing SPI Engine's parameters
* @param speed_hz SPI engine transfer speed
*/
void spi_engine_set_speed(struct spi_desc *desc,
uint32_t speed_hz)
{
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
desc_extra->clk_div = desc_extra->ref_clk_hz /
(2 * speed_hz) - 1;
}
/**
* @brief Set the number of words transferred in a single transaction
*
* @param desc Decriptor containing SPI Engine's parameters
* @param bytes_number The number of bytes to be converted
* @return uint8_t A number of words in which bytes_number can be grouped
*/
static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
uint8_t bytes_number)
{
uint8_t xfer_word_len;
uint8_t words_number;
xfer_word_len = desc->data_width / 8;
words_number = bytes_number / xfer_word_len;
if ((bytes_number % xfer_word_len) != 0)
words_number++;
return words_number;
}
/**
* @brief Get the word length in bytes
*
* @param desc Decriptor containing SPI Engine's parameters
* @return uint8_t Number of bytes that fit in one word
*/
static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
{
uint8_t word_length;
word_length = desc->data_width / 8;
return word_length;
}
/**
* @brief Compute the prescaler used to set the sleep period.
*
* @param desc Decriptor containing SPI interface parameters
* @param sleep_time_ns The amount of time where the transfer hangs
* @param sleep_div Clock prescaler
* @return int32_t This function allways returns SUCCESS
*/
static int32_t spi_get_sleep_div(struct spi_desc *desc,
uint32_t sleep_time_ns,
uint32_t *sleep_div)
{
struct spi_engine_desc *eng_desc;
eng_desc = desc->extra;
/*
* Engine Wiki:
*
* The frequency of the SCLK signal is derived from the
* module clock frequency using the following formula:
* f_sclk = f_clk / ((div + 1) * 2)
*/
*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
((eng_desc->clk_div + 1) * 2) - 1;
return SUCCESS;
}
/**
* @brief Create a new commands queue used in a spi transfer
*
* @param fifo Command buffer, usually used in fifo mode
* @param cmd Command with witch the buffer will be initiated
* @return int32_t Failure if the memory allocation failed
*/
static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
uint32_t cmd)
{
struct spi_engine_cmd_queue *local_fifo;
local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
if(!local_fifo)
return FAILURE;
local_fifo->cmd = cmd;
local_fifo->next = NULL;
*fifo = local_fifo;
return SUCCESS;
}
/**
* @brief Add a command at the end of an existing queue
*
* @param fifo Command buffer, usually used in fifo mode
* @param cmd Command to be added
*/
static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
uint32_t cmd)
{
struct spi_engine_cmd_queue *to_add = NULL;
struct spi_engine_cmd_queue *local_fifo;
local_fifo = *fifo;
while (local_fifo->next != NULL) {
// Get the last element
local_fifo = local_fifo->next;
}
// Create a new element
spi_engine_queue_new_cmd(&to_add, cmd);
// Add as the next element
local_fifo->next = to_add;
}
/**
* @brief Add a command at the beginning of an existing queue
*
* @param fifo Command buffer, usually used in fifo mode
* @param cmd Command to be added
*/
static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
uint32_t cmd)
{
struct spi_engine_cmd_queue *to_add = NULL;
// Create a new element
spi_engine_queue_new_cmd(&to_add, cmd);
// Interchange the addresses
to_add->next = *fifo;
*fifo = to_add;
}
/**
* @brief Get the command from the beginning of the queue
*
* @param fifo Command buffer, usually used in fifo mode
* @param cmd Value of the command that was extracted
* @return int32_t Return FAILURE if the queue is empty
*/
static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
uint32_t *cmd)
{
struct spi_engine_cmd_queue *local_fifo;
if (!*fifo)
return FAILURE;
local_fifo = *fifo;
*cmd = local_fifo->cmd;
if ((*fifo)->next) {
*fifo = local_fifo->next;
free(local_fifo);
} else {
free(*fifo);
*fifo = NULL;
}
return SUCCESS;
}
/**
* @brief Free the memory allocated by a queue
*
* @param fifo The queue that needs it's memory freed
* @return int32_t This function allways return SUCCESS
*/
static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
{
if(*fifo && (*fifo)->next)
spi_engine_queue_free(&(*fifo)->next);
if((*fifo) != NULL) {
free(*fifo);
*fifo = NULL;
}
return SUCCESS;
}
/**
* @brief Write the SPI engine's command fifo
*
* @param desc Decriptor containing SPI Engine's parameters
* @param cmd The command that will be written
* @return int32_t Returns FAILURE if the the axi transfer failed
*/
static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
uint32_t cmd)
{
int32_t ret;
/* Check if offload is enabled */
if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
ret = spi_engine_write(desc,
SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
cmd);
} else {
ret = spi_engine_write(desc,
SPI_ENGINE_REG_CMD_FIFO,
cmd);
}
return ret;
}
/**
* @brief Write a transfer command to the SPI engine's command fifo
*
* @param desc Decriptor containing SPI Engine's parameters
* @param read_write Read/Write operation flag
* @param bytes_number Number of bytes to transfer
* @return int32_t This function allways returns SUCCESS
*/
static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
uint8_t read_write,
uint8_t bytes_number)
{
uint8_t words_number;
words_number = spi_get_words_number(desc, bytes_number);
desc->offload_tx_len += words_number;
/*
* Engine Wiki:
*
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine
*
* The words number is zero based
*/
spi_engine_write_cmd_reg(desc,
SPI_ENGINE_CMD_TRANSFER(read_write,
words_number - 1));
return SUCCESS;
}
/**
* @brief Change the state of the chip select port
*
* @param desc Decriptor containing SPI interface parameters
* @param assert Chip select state.
* The supported values are :
* -true (HIGH)
* -false (LOW)
*/
static void spi_engine_set_cs(struct spi_desc *desc,
bool assert)
{
uint8_t mask;
struct spi_engine_desc *eng_desc;
eng_desc = desc->extra;
mask = 0xFF;
/* Switch the state only of the selected chip select */
if (!assert)
mask ^= BIT(desc->chip_select);
spi_engine_write_cmd_reg(eng_desc,
SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
mask));
}
/**
* @brief Add a delay between the engine commands
*
* @param desc Decriptor containing SPI interface parameters
* @param sleep_time_ns Number of nanoseconds to sleep between commands
*/
static void spi_gen_sleep_ns(struct spi_desc *desc,
uint32_t sleep_time_ns)
{
uint32_t sleep_div;
struct spi_engine_desc *eng_desc;
eng_desc = desc->extra;
spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
}
/**
* @brief Spi engine command interpreter
*
* @param desc Decriptor containing SPI interface parameters
* @param cmd Command to send to the engine
* @return int32_t - SUCCESS if the command is transferred
* - FAILURE if the command format is invalid
*/
static int32_t spi_engine_write_cmd(struct spi_desc *desc,
uint32_t cmd)
{
uint8_t engine_command;
uint8_t parameter;
uint8_t modifier;
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
engine_command = (cmd >> 12) & 0x0F;
modifier = (cmd >> 8) & 0x0F;
parameter = cmd & 0xFF;
switch(engine_command) {
case SPI_ENGINE_INST_TRANSFER:
spi_engine_transfer(desc_extra, modifier, parameter);
break;
case SPI_ENGINE_INST_ASSERT:
if(parameter == 0xFF) {
/* Set the CS HIGH */
spi_engine_set_cs(desc, true);
} else if(parameter == 0x00) {
/* Set the CS LOW */
spi_engine_set_cs(desc, false);
}
break;
/* The SYNC and SLEEP commands got the same value but different
modifier */
case SPI_ENGINE_INST_SYNC_SLEEP:
/* SYNC instruction */
if(modifier == 0x00) {
spi_engine_write_cmd_reg(desc_extra, cmd);
} else if(modifier == 0x01) {
spi_gen_sleep_ns(desc, parameter);
}
break;
case SPI_ENGINE_INST_CONFIG:
spi_engine_write_cmd_reg(desc_extra, cmd);
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Prepare the command queue before sending it to the engine
*
* @param desc Decriptor containing SPI interface parameters
* @param msg Structure used to store the transfer messages
* @return int32_t This function allways returns SUCCESS
*/
static int32_t spi_engine_compile_message(struct spi_desc *desc,
struct spi_engine_msg *msg)
{
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
/* Configure the prescaler */
spi_engine_queue_append_cmd(&msg->cmds,
SPI_ENGINE_CMD_CONFIG(
SPI_ENGINE_CMD_REG_CLK_DIV,
desc_extra->clk_div));
/* Set the data transfer length */
spi_engine_queue_append_cmd(&msg->cmds,
SPI_ENGINE_CMD_CONFIG(
SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
desc_extra->data_width));
/*
* Configure the spi mode :
* - 3 wire
* - CPOL
* - CPHA
*/
spi_engine_queue_append_cmd(&msg->cmds,
SPI_ENGINE_CMD_CONFIG(
SPI_ENGINE_CMD_REG_CONFIG,
desc->mode));
/* Add a sync command to signal that the transfer has finished */
spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
return SUCCESS;
}
/**
* @brief Initiate a spi transfer (Blocking)
*
* @param desc Decriptor containing SPI interface parameters
* @param msg Structure used to store the transfer messages
* @return int32_t - SUCCESS if the transfer finished
* - FAILURE if the memory allocation failed
*/
static int32_t spi_engine_transfer_message(struct spi_desc *desc,
struct spi_engine_msg *msg)
{
uint32_t i;
uint32_t data;
uint32_t sync_id;
bool offload_en;
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
spi_engine_compile_message(desc, msg);
offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
(desc_extra->offload_config & OFFLOAD_RX_EN);
/* Write the command fifo buffer */
while(msg->cmds != NULL) {
spi_engine_queue_get_cmd(&msg->cmds, &data);
spi_engine_write_cmd(desc, data);
}
/* Write a number of tx_length WORDS on the SDO line */
if(offload_en) {
for(i = 0; i < desc_extra->offload_tx_len; i++)
spi_engine_write(desc_extra,
SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
msg->tx_buf[i]);
} else {
if(msg->tx_buf != NULL){
for(i = 0; i < msg->tx_length; i++)
spi_engine_write(desc_extra,
SPI_ENGINE_REG_SDO_DATA_FIFO,
msg->tx_buf[i]);
}
do {
spi_engine_read(desc_extra,
SPI_ENGINE_REG_SYNC_ID,
&sync_id);
}
/* Wait for the end sync signal */
while(sync_id != _sync_id);
_sync_id++;
/* Read a number of rx_length WORDS from the SDI line and store
them */
for(i = 0; i < msg->rx_length; i++) {
spi_engine_read(desc_extra,
SPI_ENGINE_REG_SDI_DATA_FIFO,
&data);
/* Store the rx data if rx buffer valid, flush sdi_fifo if
rx buffer is invalid.*/
if(msg->rx_buf != NULL){
msg->rx_buf[i] = data;
}
}
}
return SUCCESS;
}
/**
* @brief Initialize the spi engine
*
* @param desc Decriptor containing SPI interface parameters
* @param param Structure containing the spi init parameters
* @return int32_t - SUCCESS if the transfer finished
* - FAILURE if the memory allocation failed
*/
int32_t spi_engine_init(struct spi_desc **desc,
const struct spi_init_param *param)
{
uint32_t data_width = 0;
uint32_t spi_engine_version = 0;
struct spi_engine_desc *eng_desc;
struct spi_engine_init_param *spi_engine_init;
if (!param) {
return FAILURE;
}
*desc = malloc(sizeof(**desc));
if(! *desc) {
free(*desc);
return FAILURE;
}
eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
if (!eng_desc)
return FAILURE;
spi_engine_init = param->extra;
(*desc)->max_speed_hz = param->max_speed_hz;
(*desc)->chip_select = param->chip_select;
(*desc)->mode = param->mode;
(*desc)->extra = eng_desc;
eng_desc->offload_config = OFFLOAD_DISABLED;
eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
eng_desc->type = spi_engine_init->type;
eng_desc->cs_delay = spi_engine_init->cs_delay;
eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
eng_desc->clk_div = eng_desc->ref_clk_hz /
(2 * param->max_speed_hz) - 1;
/* Perform a reset */
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
usleep(1000);
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
/* Get current data width */
spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
eng_desc->max_data_width = data_width;
spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
/* Get spi engine version */
spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
(spi_engine_version >> 16),
((spi_engine_version >> 8) & 0xFF),
(spi_engine_version & 0xFF));
return SUCCESS;
}
/**
* @brief Write and read on the spi interface in 4-wire mode (full-duplex)
*
* @param desc Decriptor containing SPI interface parameters
* @param data Pointer to data buffer
* @param bytes_number Number of bytes to transfer
* @return int32_t - SUCCESS if the transfer finished
* - FAILURE if the memory allocation or transfer failed
*/
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
uint8_t *data,
uint16_t bytes_number)
{
uint8_t word_len;
uint8_t words_number;
int32_t ret;
struct spi_engine_msg msg;
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
/* If we want to access SPI interface and SPI engine offload module was
* activated, we need to disable it
* This is set in spi_engine_offload_init() */
desc_extra->offload_config = OFFLOAD_DISABLED;
/* This is set in spi_engine_offload_transfer() */
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
words_number = spi_get_words_number(desc_extra, bytes_number);
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
if (!msg.cmds)
return FAILURE;
msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
msg.tx_length = words_number;
msg.rx_length = words_number;
/* Get the length of transferred word */
word_len = spi_get_word_length(desc_extra);
/* Make sure the CS is HIGH before starting a transaction */
msg.cmds->next = NULL;
msg.cmds->cmd = CS_HIGH;
// Assert select.
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
// add read/write command
spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
// Disable select.
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
/* Pack the bytes into engine WORDS */
for (int i = 0; i < bytes_number; i++)
msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
(i % word_len + 1) * 8);
ret = spi_engine_transfer_message(desc, &msg);
for (int i = 0; i < bytes_number; i++)
data[i] = msg.rx_buf[(i) / word_len] >>
(desc_extra->data_width -
((i) % word_len + 1) * 8);
spi_engine_queue_free(&msg.cmds);
free(msg.tx_buf);
free(msg.rx_buf);
return ret;
}
/**
* @brief Write and read on the spi interface in 3-wire mode (half-duplex)
*
* @param desc Decriptor containing SPI interface parameters
* @param data Pointer to data buffer
* @param bytes_number Number of bytes to transfer
* @return int32_t - SUCCESS if the transfer finished
* - FAILURE if the memory allocation or transfer failed
*/
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
uint8_t *write_data,
uint8_t *read_data,
uint16_t write_bytes_number,
uint16_t read_bytes_number)
{
uint8_t word_len;
uint8_t wr_words_number;
uint8_t rd_words_number;
int32_t ret;
struct spi_engine_msg msg;
struct spi_engine_desc *desc_extra;
desc_extra = desc->extra;
/* If we want to access SPI interface and SPI engine offload module was
* activated, we need to disable it
* This is set in spi_engine_offload_init() */
desc_extra->offload_config = OFFLOAD_DISABLED;
/* This is set in spi_engine_offload_transfer() */
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
if (!msg.cmds)
return FAILURE;
msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
msg.tx_length = wr_words_number;
msg.rx_length = rd_words_number;
/* Get the length of transferred word */
word_len = spi_get_word_length(desc_extra);
/* Make sure the CS is HIGH before starting a transaction */
msg.cmds->next = NULL;
msg.cmds->cmd = CS_HIGH;
// Assert select.
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
// add read/write command
if(write_bytes_number > 0)
spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
if(read_bytes_number > 0)
spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
// Disable select.
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
/* Pack the bytes into engine WORDS */
for (int i = 0; i < write_bytes_number; i++)
msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
(i % word_len + 1) * 8);
ret = spi_engine_transfer_message(desc, &msg);
for (int i = 0; i < read_bytes_number; i++)
read_data[i] = msg.rx_buf[(i) / word_len] >>
(desc_extra->data_width -
((i) % word_len + 1) * 8);
spi_engine_queue_free(&msg.cmds);
free(msg.tx_buf);
free(msg.rx_buf);
return ret;
}
/**
* @brief Initialize the SPI engine's offload module
*
* @param desc Decriptor containing SPI interface parameters
* @param param Structure containing the offload init parameters
* @return int32_t This function allways returns SUCCESS
*/
int32_t spi_engine_offload_init(struct spi_desc *desc,
const struct spi_engine_offload_init_param *param)
{
struct spi_engine_desc *eng_desc;
struct axi_dmac_init dmac_init;
uint32_t dma_flags;
eng_desc = desc->extra;
eng_desc->offload_config = param->offload_config;
if(!(param->dma_flags))
dma_flags = DMA_CYCLIC;
else
dma_flags = *(param->dma_flags);
if(param->offload_config & OFFLOAD_TX_EN) {
dmac_init.name = "DAC DMAC";
dmac_init.base = param->tx_dma_baseaddr;
dmac_init.direction = DMA_MEM_TO_DEV;
dmac_init.flags = dma_flags;
axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
if(!eng_desc->offload_tx_dma)
return FAILURE;
}
if(param->offload_config & OFFLOAD_RX_EN) {
dmac_init.name = "ADC DMAC";
dmac_init.base = param->rx_dma_baseaddr;
dmac_init.direction = DMA_DEV_TO_MEM;
dmac_init.flags = dma_flags;
axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
if(!eng_desc->offload_rx_dma)
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Initiate a SPI transfer in offload mode
*
* @param desc Decriptor containing SPI interface parameters
* @param msg Offload message that get's to be transferred
* @param no_samples Number of time the messages will be transferred
* @return int32_t This function allways returns SUCCESS
*/
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
struct spi_engine_offload_message msg,
uint32_t no_samples)
{
struct spi_engine_msg transfer;
struct spi_engine_desc *eng_desc;
uint32_t i;
uint8_t word_length;
eng_desc = desc->extra;
/* Check if offload is disabled */
if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
(eng_desc->offload_config & OFFLOAD_RX_EN)))
return FAILURE;
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
eng_desc->offload_tx_len = 0;
eng_desc->offload_rx_len = 0;
transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
if (!transfer.cmds)
return FAILURE;
transfer.tx_buf = msg.commands_data;
/* Load the commands into the message */
transfer.cmds->next = NULL;
transfer.cmds->cmd = msg.commands[0];
i = 1;
while(i < msg.no_commands) {
spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
}
spi_engine_transfer_message(desc, &transfer);
/* Start transfer */
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
word_length = spi_get_word_length(eng_desc);
if(eng_desc->offload_config & OFFLOAD_TX_EN) {
axi_dmac_transfer(eng_desc->offload_tx_dma,
msg.tx_addr,
word_length * eng_desc->offload_tx_len *
no_samples);
}
if(eng_desc->offload_config & OFFLOAD_RX_EN) {
axi_dmac_transfer(eng_desc->offload_rx_dma,
msg.rx_addr,
word_length * eng_desc->offload_tx_len *
no_samples);
}
usleep(1000);
spi_engine_queue_free(&transfer.cmds);
return SUCCESS;
}
/**
* @brief Free the resources allocated by spi_init().
*
* @param desc Decriptor containing SPI interface parameters
* @return int32_t This function allways returns SUCCESS
*/
int32_t spi_engine_remove(struct spi_desc *desc)
{
struct spi_engine_desc *eng_desc;
eng_desc = desc->extra;
if(eng_desc->offload_config & OFFLOAD_TX_EN)
axi_dmac_remove(eng_desc->offload_tx_dma);
if(eng_desc->offload_config & OFFLOAD_RX_EN)
axi_dmac_remove(eng_desc->offload_rx_dma);
free(desc->extra);
free(desc);
return SUCCESS;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h
+231
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/*******************************************************************************
* @file spi_engine.h
* @brief Header file of SPI Engine core features.
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef SPI_ENGINE_H
#define SPI_ENGINE_H
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "spi_engine_private.h"
#include "../../platform/spi_extra.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define OFFLOAD_DISABLED 0x00
#define OFFLOAD_TX_EN BIT(0)
#define OFFLOAD_RX_EN BIT(1)
#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN
#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF
/* Spi engine commands */
#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
((mode) << 8) | (no_bytes))
#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF)
/* The delay and chip select parmeters are passed over the engine descriptor
and will be used inside the function call */
#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
/**
* @struct spi_engine_init_param
* @brief Structure containing the init parameters needed by the SPI engine
*/
struct spi_engine_init_param {
/** SPI engine reference clock */
uint32_t ref_clk_hz;
/** Type of implementation */
enum xil_spi_type type;
/** Base address where the HDL core is situated */
uint32_t spi_engine_baseaddr;
/** Delay between the CS toggle and the start of SCLK */
uint32_t cs_delay;
/** Data with of one SPI transfer ( in bits ) */
uint8_t data_width;
};
/**
* @struct spi_engine_desc
* @brief Structure representing an SPI engine device
*/
struct spi_engine_desc {
/** SPI engine reference clock */
uint32_t ref_clk_hz;
/** Type of implementation */
enum xil_spi_type type;
/** Pointer to a DMAC used in transmission */
struct axi_dmac *offload_tx_dma;
/** Pointer to a DMAC used in reception */
struct axi_dmac *offload_rx_dma;
/** Offload's module transfer direction : TX, RX or both */
uint8_t offload_config;
/** Number of words that the module has to send */
uint8_t offload_tx_len;
/** Number of words that the module has to receive */
uint8_t offload_rx_len;
/** Base address where the HDL core is situated */
uint32_t spi_engine_baseaddr;
/** Base address where the RX DMAC core is situated */
uint32_t rx_dma_baseaddr;
/** Base address where the TX DMAC core is situated */
uint32_t tx_dma_baseaddr;
/** Delay between the CS toggle and the start of SCLK */
uint8_t cs_delay;
/** Clock divider used in transmission delays */
uint32_t clk_div;
/** Data with of one SPI transfer ( in bits ) */
uint8_t data_width;
/** The maximum data width supported by the engine */
uint8_t max_data_width;
};
/**
* @struct spi_engine_offload_init_param
* @brief Structure containing the init parameters needed by the offload module
*/
struct spi_engine_offload_init_param {
/** Base address where the RX DMAC core is situated */
uint32_t rx_dma_baseaddr;
/** Base address where the TX DMAC core is situated */
uint32_t tx_dma_baseaddr;
/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
uint32_t *dma_flags;
/** Offload's module transfer direction : TX, RX or both */
uint8_t offload_config;
};
/**
* @struct spi_engine_offload_message
* @brief Structure representing an offload message
*/
struct spi_engine_offload_message {
/** Pointer to the SPI engine commands buffer that will be sent.
* The available commands can be found at:
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
*/
uint32_t *commands;
/** Length of the SPI engine commands buffer */
uint32_t no_commands;
/** Pointer of the data that will be sent over spi */
uint32_t *commands_data;
/** The address where the data that will be transmitted is situated */
uint32_t tx_addr;
/** The address where the data that will be received is situated */
uint32_t rx_addr;
};
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
/**
* @brief Spi engine platform specific SPI platform ops structure
*/
extern const struct spi_platform_ops xil_spi_ops;
/* Write SPI Engine's axi registers */
int32_t spi_engine_write(struct spi_engine_desc *desc,
uint32_t reg_addr,
uint32_t reg_data);
/* Read SPI Engine's axi registers */
int32_t spi_engine_read(struct spi_engine_desc *desc,
uint32_t reg_addr,
uint32_t *reg_data);
/* Initialize the SPI engine device */
int32_t spi_engine_init(struct spi_desc **desc,
const struct spi_init_param *param);
/* Write and read data over SPI using the SPI engine */
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
uint8_t *data,
uint16_t bytes_number);
/* Write and read data over SPI using the SPI engine in 3-wire mode */
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
uint8_t *write_data,
uint8_t *read_data,
uint16_t write_bytes_number,
uint16_t read_bytes_number);
/* Free the resources used by the SPI engine device */
int32_t spi_engine_remove(struct spi_desc *desc);
/* Initialize the SPI engine offload module */
int32_t spi_engine_offload_init(struct spi_desc *desc,
const struct spi_engine_offload_init_param *param);
/* Write and read data over SPI using the offload module */
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
struct spi_engine_offload_message msg,
uint32_t no_samples);
/* Set SPI transfer width */
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
uint8_t data_wdith);
/* Set SPI transfer speed */
void spi_engine_set_speed(struct spi_desc *desc,
uint32_t speed_hz);
#endif // SPI_ENGINE_H
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h
+154
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@@ -0,0 +1,154 @@
/*******************************************************************************
* @file spi_engine_private.h
* @brief Private definitions of the SPI Engine
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef SPI_ENGINE_PRIVATE_H
#define SPI_ENGINE_PRIVATE_H
#include <stdint.h>
#include <stdbool.h>
#include "../../../include/spi.h"
#include "../../../include/util.h"
/******************************************************************************/
/*************************** Spi Engine registers *****************************/
/******************************************************************************/
#define SPI_ENGINE_REG_VERSION 0x00
#define SPI_ENGINE_REG_DATA_WIDTH 0x0C
#define SPI_ENGINE_REG_RESET 0x40
#define SPI_ENGINE_REG_INT_ENABLE 0x80
#define SPI_ENGINE_REG_INT_PENDING 0x84
#define SPI_ENGINE_REG_INT_SOURCE 0x88
#define SPI_ENGINE_REG_SYNC_ID 0xC0
#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0
#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4
#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8
#define SPI_ENGINE_REG_CMD_FIFO 0xE0
#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4
#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8
#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC
/******************************************************************************/
/************************ Spi Engine register parameters **********************/
/******************************************************************************/
#define SPI_ENGINE_INST_TRANSFER 0x00
#define SPI_ENGINE_INST_ASSERT 0x01
#define SPI_ENGINE_INST_CONFIG 0x02
#define SPI_ENGINE_INST_SYNC_SLEEP 0x03
#define SPI_ENGINE_INST_MISC 0x03
#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00
#define SPI_ENGINE_CMD_REG_CONFIG 0x01
#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02
#define SPI_ENGINE_MISC_SYNC 0x00
#define SPI_ENGINE_MISC_SLEEP 0x01
#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1)
#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2)
#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
#define SPI_ENGINE_INT_SYNC BIT(3)
#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0)
#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0)
#define SPI_ENGINE_CONFIG_CPHA BIT(0)
#define SPI_ENGINE_CONFIG_CPOL BIT(1)
#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
/******************************************************************************/
/**************************** Spi Engine commands *****************************/
/******************************************************************************/
#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01
#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02
#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x))
#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x))
#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x))
#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x))
#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x))
#define SPI_ENGINE_CMD(inst, arg1, arg2) \
(((inst & 0x03) << 12) | \
((arg1 & 0x03) << 8) | arg2 )
#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \
SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \
(readwrite), (n))
#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \
(delay), (cs))
#define SPI_ENGINE_CMD_CONFIG(reg, val) \
SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \
(reg), (val))
#define SPI_ENGINE_CMD_SLEEP(delay) \
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
SPI_ENGINE_MISC_SLEEP, \
(delay))
#define SPI_ENGINE_CMD_SYNC(id) \
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
SPI_ENGINE_MISC_SYNC, \
(id))
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
typedef struct spi_engine_cmd_queue {
uint32_t cmd;
struct spi_engine_cmd_queue *next;
} spi_engine_cmd_queue;
typedef struct spi_engine_msg {
uint32_t *tx_buf;
uint32_t *rx_buf;
uint32_t tx_length;
uint32_t rx_length;
struct spi_engine_cmd_queue *cmds;
} spi_engine_msg;
#endif // SPI_ENGINE_PRIVATE_H
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/frequency/lmk04828/lmk04828.c
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/***************************************************************************//**
* @file lmk04828.c
* @brief Implementation of AD9680 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include "lmk04828.h"
#include "../../../include/error.h"
/***************************************************************************//**
* @brief lmk04828_read
*******************************************************************************/
int32_t lmk04828_read(struct lmk04828_dev *dev,
uint16_t reg_addr,
uint8_t *reg_data)
{
uint8_t tx_buf[2];
uint8_t rx_buf[1];
int32_t ret;
tx_buf[0] = 0x80 | (reg_addr >> 8);
tx_buf[1] = reg_addr & 0xFF;
ret = spi_write_and_read_3wire(dev->spi_desc,
tx_buf, rx_buf, 2, 1);
*reg_data = rx_buf[0];
return ret;
}
/***************************************************************************//**
* @brief lmk04828_write
*******************************************************************************/
int32_t lmk04828_write(struct lmk04828_dev *dev,
uint16_t reg_addr,
uint8_t reg_data)
{
uint8_t buf[3];
int32_t ret;
buf[0] = reg_addr >> 8;
buf[1] = reg_addr & 0xFF;
buf[2] = reg_data;
ret = spi_write_and_read_3wire(dev->spi_desc,
buf, NULL, 3, 0);
return ret;
}
/***************************************************************************//**
* @brief lmk04828_init
*******************************************************************************/
int32_t lmk04828_init(struct lmk04828_dev **device,
const struct lmk04828_init_param *init_param)
{
int ret = SUCCESS;
struct lmk04828_dev *dev;
dev = (struct lmk04828_dev *)malloc(sizeof(*dev));
if (!dev)
return FAILURE;
/* SPI */
ret = spi_init(&dev->spi_desc, init_param->spi_init);
*device = dev;
return ret;
}
/***************************************************************************//**
* @brief Free the resources allocated by lmk04828_setup().
*
* @param dev - The device structure.
*
* @return SUCCESS in case of success, negative error code otherwise.
*******************************************************************************/
int32_t lmk04828_remove(struct lmk04828_dev *dev)
{
int32_t ret;
ret = spi_remove(dev->spi_desc);
free(dev);
return ret;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/frequency/lmk04828/lmk04828.h
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/***************************************************************************//**
* @file lmk04828.h
* @brief Header file of lmk04828 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef LMK04828_H_
#define LMK04828_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../../include/delay.h"
#include "../../../include/spi.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
struct lmk04828_dev {
/* SPI */
spi_desc *spi_desc;
};
struct lmk04828_init_param {
/* SPI */
spi_init_param *spi_init;
};
struct lmk04828_config {
uint16_t addr;
uint8_t value;
};
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
int32_t lmk04828_read(struct lmk04828_dev *dev,
uint16_t reg_addr,
uint8_t *reg_data);
int32_t lmk04828_write(struct lmk04828_dev *dev,
uint16_t reg_addr,
uint8_t reg_data);
int32_t lmk04828_init(struct lmk04828_dev **device,
const struct lmk04828_init_param *init_param);
int32_t lmk04828_remove(struct lmk04828_dev *dev);
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/frequency/lmx2594/lmx2594.c
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/***************************************************************************//**
* @file lmx2594.c
* @brief Implementation of AD9680 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include "../lmx2594/lmx2594.h"
#include <stdlib.h>
#include <stdio.h>
#include "../../../include/error.h"
/***************************************************************************//**
* @brief lmx2594_read
*******************************************************************************/
int32_t lmx2594_read(struct lmx2594_dev *dev,
uint8_t reg_addr,
uint16_t *reg_data)
{
uint8_t tx_buf[1];
uint8_t rx_buf[2];
int32_t ret;
tx_buf[0] = 0x80 | reg_addr;
ret = spi_write_and_read_3wire(dev->spi_desc,
tx_buf, rx_buf, 1, 2);
*reg_data = rx_buf[1];
*reg_data |= ((uint16_t)rx_buf[0]) << 8;
return ret;
}
/***************************************************************************//**
* @brief lmx2594_write
*******************************************************************************/
int32_t lmx2594_write(struct lmx2594_dev *dev,
uint8_t reg_addr,
uint16_t reg_data)
{
uint8_t buf[3];
int32_t ret;
buf[0] = reg_addr;
buf[1] = reg_data >> 8;
buf[2] = reg_data & 0xFF;
ret = spi_write_and_read_3wire(dev->spi_desc,
buf, NULL, 3, 0);
return ret;
}
/***************************************************************************//**
* @brief lmx2594_init
*******************************************************************************/
int32_t lmx2594_init(struct lmx2594_dev **device,
const struct lmx2594_init_param *init_param)
{
int ret = SUCCESS;
struct lmx2594_dev *dev;
dev = (struct lmx2594_dev *)malloc(sizeof(*dev));
if (!dev)
return FAILURE;
/* SPI */
ret = spi_init(&dev->spi_desc, init_param->spi_init);
*device = dev;
return ret;
}
/***************************************************************************//**
* @brief Free the resources allocated by lmx2594_setup().
*
* @param dev - The device structure.
*
* @return SUCCESS in case of success, negative error code otherwise.
*******************************************************************************/
int32_t lmx2594_remove(struct lmx2594_dev *dev)
{
int32_t ret;
ret = spi_remove(dev->spi_desc);
free(dev);
return ret;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/frequency/lmx2594/lmx2594.h
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/***************************************************************************//**
* @file lmx2594.h
* @brief Header file of lmx2594 Driver.
* @author DBogdan (dragos.bogdan@analog.com)
********************************************************************************
* Copyright 2014-2016(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef LMX2594_H_
#define LMX2594_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../../include/delay.h"
#include "../../../include/spi.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
struct lmx2594_dev {
/* SPI */
spi_desc *spi_desc;
};
struct lmx2594_init_param {
/* SPI */
spi_init_param *spi_init;
};
struct lmx2594_config {
uint8_t addr;
uint16_t value;
};
/******************************************************************************/
/************************ Functions Declarations ******************************/
/******************************************************************************/
int32_t lmx2594_read(struct lmx2594_dev *dev,
uint8_t reg_addr,
uint16_t *reg_data);
int32_t lmx2594_write(struct lmx2594_dev *dev,
uint8_t reg_addr,
uint16_t reg_data);
int32_t lmx2594_init(struct lmx2594_dev **device,
const struct lmx2594_init_param *init_param);
int32_t lmx2594_remove(struct lmx2594_dev *dev);
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/axi_io.c
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/***************************************************************************//**
* @file xilinx/axi_io.c
* @brief Implementation of Xilinx AXI IO.
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <xil_io.h>
#include "../../include/error.h"
#include "../../include/axi_io.h"
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief AXI IO Xilinx specific read function.
* @param base - Base address
* @param offset - Address offset
* @param data - variable where returned data is stored
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
{
*data = Xil_In32(base + offset);
return SUCCESS;
}
/**
* @brief AXI IO Xilinx specific write function.
* @param base - Base address
* @param offset - Address offset
* @param data - data to be written.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
{
Xil_Out32(base + offset, data);
return SUCCESS;
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/delay.c
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/***************************************************************************//**
* @file xilinx/delay.c
* @brief Implementation of Xilinx Delay Functions.
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include "../../include/delay.h"
#include <sleep.h>
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief Generate microseconds delay.
* @param usecs - Delay in microseconds.
* @return None.
*/
void udelay(uint32_t usecs)
{
#ifdef _XPARAMETERS_PS_H_
usleep(usecs);
#else
usleep(usecs / 20); // FIXME
#endif
}
/**
* @brief Generate miliseconds delay.
* @param msecs - Delay in miliseconds.
* @return None.
*/
void mdelay(uint32_t msecs)
{
#ifdef _XPARAMETERS_PS_H_
usleep(msecs * 1000);
#else
usleep(msecs * 50); // FIXME
#endif
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/gpio_extra.h
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/*******************************************************************************
* @file xilinx/gpio_extra.h
* @brief Header containing extra types used in the gpio driver
* @author scuciurean (sergiu.cuciurean@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef GPIO_EXTRA_H_
#define GPIO_EXTRA_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
/**
* @enum xil_gpio_type
* @brief Xilinx platform architecture sections
*/
typedef enum xil_gpio_type {
/** Programmable Logic */
GPIO_PL,
/** Processing System */
GPIO_PS
} xil_gpio_type;
/**
* @struct xil_gpio_init_param
* @brief Structure holding the initialization parameters for Xilinx platform
* specific GPIO parameters.
*/
typedef struct xil_gpio_init_param {
/** Xilinx architecture */
enum xil_gpio_type type;
/** Device ID */
uint32_t device_id;
} xil_gpio_init_param;
/**
* @struct xil_gpio_desc
* @brief Xilinx platform specific GPIO descriptor
*/
typedef struct xil_gpio_desc {
/** Xilinx architecture */
enum xil_gpio_type type;
/** Xilinx GPIO configuration */
void *config;
/** Xilinx GPIO Instance */
void *instance;
} xil_gpio_desc;
/**
* @brief Xilinx platform specific gpio platform ops structure
*/
extern const struct gpio_platform_ops xil_gpio_ops;
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/irq_extra.h
+91
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/*******************************************************************************
* @file irq_extra.h
* @brief Header containing types used in the irq driver.
* @author Cristian Pop (cristian.pop@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef IRQ_EXTRA_H_
#define IRQ_EXTRA_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../include/irq.h"
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
/**
* @enum xil_irq_type
* @brief Xilinx platform architecture sections
*/
enum xil_irq_type {
/** Programmable Logic */
IRQ_PL,
/** Processing System */
IRQ_PS
};
/**
* @struct xil_irq_init_param
* @brief Structure holding the initialization parameters for Xilinx platform
* specific IRQ parameters.
*/
struct xil_irq_init_param {
/** Xilinx architecture */
enum xil_irq_type type;
};
/**
* @struct xil_irq_desc
* @brief Xilinx platform specific IRQ descriptor
*/
struct xil_irq_desc {
/** Xilinx architecture */
enum xil_irq_type type;
/** Xilinx IRQ Instance */
void *instance;
};
/**
* @brief Xilinx specific IRQ platform ops structure
*/
extern const struct irq_platform_ops xil_irq_ops;
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/spi_extra.h
+115
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/*******************************************************************************
* @file xilinx/spi_extra.h
* @brief Header containing extra types used in the spi driver.
* @author scuciurean (sergiu.cuciurean@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef SPI_EXTRA_H_
#define SPI_EXTRA_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdint.h>
#include "../../include/spi.h"
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define SPI_CS_DECODE 0x01
#define SPI_DEASSERT_CURRENT_SS 0x0F
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
/**
* @enum xil_spi_type
* @brief Xilinx platform architecture sections
*/
enum xil_spi_type {
/** Programmable Logic */
SPI_PL,
/** Processing System */
SPI_PS,
/** SPI Engine */
SPI_ENGINE
};
/**
* @struct xil_spi_init_param
* @brief Structure holding the initialization parameters for Xilinx platform
* specific SPI parameters when using xil_spi_ops.
*/
typedef struct xil_spi_init_param {
/** Xilinx architecture */
enum xil_spi_type type;
/** SPI flags */
uint32_t flags;
} xil_spi_init_param;
/**
* @struct xil_spi_desc
* @brief Xilinx platform specific SPI descriptor
*/
typedef struct xil_spi_desc {
/** Xilinx architecture */
enum xil_spi_type type;
/** SPI flags */
uint32_t flags;
/** SPI configuration */
void *config;
/** SPI instance */
void *instance;
} xil_spi_desc;
/**
* @brief SPI engine platform ops structure
*/
extern const struct spi_platform_ops spi_eng_platform_ops;
/**
* @brief Xilinx specific SPI platform ops structure
*/
extern const struct spi_platform_ops xil_spi_ops;
/**
* @brief Xilinx SPI PS register functions. No extra param needed
*/
extern const struct spi_platform_ops xil_spi_reg_ops_pl;
#endif // SPI_EXTRA_H_
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/uart_extra.h
+107
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/*******************************************************************************
* @file xilinx/uart_extra.h
* @brief Header containing types used in the uart driver.
* @author Cristian Pop (cristian.pop@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef UART_EXTRA_H_
#define UART_EXTRA_H_
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
/******************************************************************************/
/********************** Macros and Constants Definitions **********************/
/******************************************************************************/
#define UART_BUFF_LENGTH 256
/******************************************************************************/
/*************************** Types Declarations *******************************/
/******************************************************************************/
/**
* @enum xil_uart_type
* @brief Xilinx platform architecture sections
*/
enum xil_uart_type {
/** Programmable Logic */
UART_PL,
/** Processing System */
UART_PS
};
/**
* @struct xil_uart_init_param
* @brief Structure holding the initialization parameters for Xilinx platform
* specific UART parameters.
*/
struct xil_uart_init_param {
/** Xilinx architecture */
enum xil_uart_type type;
/** Interrupt Request ID */
uint32_t irq_id;
/** Interrupt Request Descriptor */
struct irq_ctrl_desc *irq_desc;
};
/**
* @struct xil_uart_desc
* @brief Xilinx platform specific UART descriptor
*/
struct xil_uart_desc {
/** Xilinx architecture */
enum xil_uart_type type;
/** Interrupt Request ID */
uint32_t irq_id;
/** Interrupt Request Descriptor */
struct irq_ctrl_desc *irq_desc;
/** FIFO */
struct fifo_element *fifo;
/** FIFO read offset */
uint32_t fifo_read_offset;
/** UART Buffer */
char buff[UART_BUFF_LENGTH];
/** Number of bytes received */
uint32_t bytes_received;
/** Total number of errors */
uint32_t total_error_count;
/** UART Instance */
void *instance;
};
#endif
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/xilinx_gpio.c
+464
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/***************************************************************************//**
* @file xilinx/xilinx_gpio.c
* @brief Implementation of Xilinx GPIO Generic Driver.
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <stdlib.h>
#include <xparameters.h>
#ifdef XPAR_XGPIO_NUM_INSTANCES
#include <xgpio.h>
#endif
#ifdef XPAR_XGPIOPS_NUM_INSTANCES
#include <xgpiops.h>
#endif
#include "gpio_extra.h"
#include "../../include/error.h"
#include "../../include/gpio.h"
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief Prepare the GPIO decriptor.
* @param desc - The GPIO descriptor.
* @param param - The structure that contains the GPIO parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t _gpio_init(struct gpio_desc *desc,
const struct gpio_init_param *param)
{
int32_t ret;
struct xil_gpio_desc *xdesc;
struct xil_gpio_init_param *xinit;
ret = FAILURE;
xdesc = desc->extra;
xinit = param->extra;
xdesc->type = xinit->type;
desc->number = param->number;
switch (xinit->type) {
case GPIO_PL:
#ifdef XGPIO_H
xdesc->instance = (XGpio *)malloc(sizeof(XGpio));
if(!xdesc->instance)
goto pl_error;
xdesc->config = XGpio_LookupConfig(xinit->device_id);
if(xdesc->config == NULL)
goto pl_error;
ret = XGpio_CfgInitialize(xdesc->instance,
xdesc->config,
((XGpio_Config*)xdesc->config)
->BaseAddress);
if(ret < 0)
goto pl_error;
break;
pl_error:
free(xdesc->instance);
#endif
goto error;
case GPIO_PS:
#ifdef XGPIOPS_H
xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs));
if(!xdesc->instance)
goto ps_error;
xdesc->config = XGpioPs_LookupConfig(xinit->device_id);
if(xdesc->config == NULL)
goto ps_error;
ret = XGpioPs_CfgInitialize(xdesc->instance,
xdesc->config,
((XGpioPs_Config*)xdesc->config)->BaseAddr);
if(ret < 0)
goto ps_error;
break;
ps_error:
free(xdesc->instance);
#endif
goto error;
error:
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Obtain the GPIO decriptor.
* @param desc - The GPIO descriptor.
* @param param - GPIO initialization parameters
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_get(struct gpio_desc **desc,
const struct gpio_init_param *param)
{
struct gpio_desc *descriptor;
struct xil_gpio_desc *extra;
int32_t ret;
descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor));
extra = (struct xil_gpio_desc*)malloc(sizeof(*extra));
if (!descriptor || !extra)
return FAILURE;
descriptor->extra = extra;
ret = _gpio_init(descriptor, param);
if(ret != SUCCESS)
goto error;
*desc = descriptor;
return SUCCESS;
error:
free(extra);
free(descriptor);
return FAILURE;
}
/**
* @brief Get the value of an optional GPIO.
* @param desc - The GPIO descriptor.
* @param param - GPIO Initialization parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_get_optional(struct gpio_desc **desc,
const struct gpio_init_param *param)
{
if(param == NULL) {
*desc = NULL;
return SUCCESS;
}
return xil_gpio_get(desc, param);
}
/**
* @brief Free the resources allocated by gpio_get().
* @param desc - The GPIO descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_remove(struct gpio_desc *desc)
{
if (desc != NULL) {
free(((xil_gpio_desc *)(desc->extra))->instance);
free(desc->extra);
free(desc);
}
return SUCCESS;
}
/**
* @brief Enable the input direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_direction_input(struct gpio_desc *desc)
{
struct xil_gpio_desc *extra;
#ifdef XGPIO_H
uint8_t pin = desc->number;
uint32_t channel = 1;
uint32_t config = 0;
#endif
extra = desc->extra;
switch (extra->type) {
case GPIO_PL:
#ifdef XGPIO_H
/* We assume that pin 32 is the first pin from channel 2 */
if (pin >= 32) {
channel = 2;
pin -= 32;
}
config = XGpio_GetDataDirection((XGpio *)extra->instance,
channel);
config |= (1 << pin);
XGpio_SetDataDirection((XGpio *)extra->instance,
channel,
config);
#endif
break;
case GPIO_PS:
#ifdef XGPIOPS_H
XGpioPs_SetDirectionPin(extra->instance,
desc->number,
GPIO_IN);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Enable the output direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_direction_output(struct gpio_desc *desc,
uint8_t value)
{
struct xil_gpio_desc *extra;
#ifdef XGPIO_H
uint8_t pin = desc->number;
uint8_t channel;
uint32_t reg_val;
#endif
extra = desc->extra;
switch (extra->type) {
case GPIO_PL:
#ifdef XGPIO_H
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
reg_val = XGpio_GetDataDirection(extra->instance,
channel);
reg_val &= ~(1 << pin);
XGpio_SetDataDirection(extra->instance,
channel,
reg_val);
reg_val = XGpio_DiscreteRead(extra->instance,
channel);
if(value)
reg_val |= (1 << pin);
else
reg_val &= ~(1 << pin);
XGpio_DiscreteWrite(extra->instance,
channel,
reg_val);
#endif
break;
case GPIO_PS:
#ifdef XGPIOPS_H
XGpioPs_SetDirectionPin(extra->instance,
desc->number,
GPIO_OUT);
XGpioPs_SetOutputEnablePin(extra->instance,
desc->number,
GPIO_OUT);
XGpioPs_WritePin(extra->instance,
desc->number,
value);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Get the direction of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param direction - The direction.
* Example: GPIO_OUT
* GPIO_IN
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_get_direction(struct gpio_desc *desc,
uint8_t *direction)
{
if (!desc)
return FAILURE;
struct xil_gpio_desc *extra;
uint8_t pin = desc->number;
#ifdef XGPIO_H
uint8_t channel;
#endif
extra = desc->extra;
switch (extra->type) {
case GPIO_PL:
#ifdef XGPIO_H
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
*direction = ((XGpio_GetDataDirection(extra->instance,
channel) >> pin) & 0x1) ^ 0x1;
#endif
break;
case GPIO_PS:
#ifdef XGPIOPS_H
*direction = XGpioPs_GetDirectionPin(extra->instance, pin);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Set the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_set_value(struct gpio_desc *desc,
uint8_t value)
{
struct xil_gpio_desc *extra;
#ifdef XGPIO_H
uint8_t pin = desc->number;
uint8_t channel;
uint32_t reg_val;
#endif
extra = desc->extra;
switch (extra->type) {
case GPIO_PL:
#ifdef XGPIO_H
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
reg_val = XGpio_DiscreteRead(extra->instance, channel);
if(value)
reg_val |= (1 << pin);
else
reg_val &= ~(1 << pin);
XGpio_DiscreteWrite(extra->instance, channel, reg_val);
#endif
break;
case GPIO_PS:
#ifdef XGPIOPS_H
XGpioPs_WritePin(extra->instance, desc->number, value);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Get the value of the specified GPIO.
* @param desc - The GPIO descriptor.
* @param value - The value.
* Example: GPIO_HIGH
* GPIO_LOW
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_gpio_get_value(struct gpio_desc *desc,
uint8_t *value)
{
if (!desc)
return FAILURE;
struct xil_gpio_desc *extra;
uint8_t pin = desc->number;
#ifdef XGPIO_H
uint8_t channel;
#endif
extra = desc->extra;
switch (extra->type) {
case GPIO_PL:
#ifdef XGPIO_H
if (pin >= 32) {
channel = 2;
pin -= 32;
} else
channel = 1;
*value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01;
#endif
break;
case GPIO_PS:
#ifdef XGPIOPS_H
*value = XGpioPs_ReadPin(extra->instance, pin);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Xilinx platform specific GPIO platform ops structure
*/
const struct gpio_platform_ops xil_gpio_ops = {
.gpio_ops_get = &xil_gpio_get,
.gpio_ops_get_optional = &xil_gpio_get_optional,
.gpio_ops_remove = &xil_gpio_remove,
.gpio_ops_direction_input = &xil_gpio_direction_input,
.gpio_ops_direction_output = &xil_gpio_direction_output,
.gpio_ops_get_direction = &xil_gpio_get_direction,
.gpio_ops_set_value = &xil_gpio_set_value,
.gpio_ops_get_value = &xil_gpio_get_value,
};
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/platform/xilinx_irq.c
+384
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@@ -0,0 +1,384 @@
/***************************************************************************//**
* @file xilinx/xilinx_irq.c
* @brief Implementation of Xilinx IRQ Generic Driver.
* @author Cristian Pop (cristian.pop@analog.com)
********************************************************************************
* Copyright 2019(c) Analog Devices, Inc.
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of Analog Devices, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
* - The use of this software may or may not infringe the patent rights
* of one or more patent holders. This license does not release you
* from the requirement that you obtain separate licenses from these
* patent holders to use this software.
* - Use of the software either in source or binary form, must be run
* on or directly connected to an Analog Devices Inc. component.
*
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/******************************************************************************/
/***************************** Include Files **********************************/
/******************************************************************************/
#include <xparameters.h>
#include <stdlib.h>
#include "irq_extra.h"
#include "../../include/irq.h"
#include "../../include/error.h"
#ifdef XPAR_XSCUGIC_NUM_INSTANCES
#include <xscugic.h>
#endif
#ifdef XPAR_XINTC_NUM_INSTANCES
#include <xintc.h>
#endif
#ifdef XPAR_XTMRCTR_NUM_INSTANCES
#include <xtmrctr.h>
#endif
/******************************************************************************/
/************************ Functions Definitions *******************************/
/******************************************************************************/
/**
* @brief Initialize the IRQ interrupts.
* @param desc - The IRQ controller descriptor.
* @param param - The structure that contains the IRQ parameters.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
const struct irq_init_param *param)
{
int32_t status;
struct irq_ctrl_desc *descriptor;
struct xil_irq_desc *xil_dev;
#ifdef XSCUGIC_H
void *config;
#endif
descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
if(!descriptor)
return FAILURE;
xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
if(!xil_dev) {
free(descriptor);
return FAILURE;
}
Xil_ExceptionInit();
descriptor->irq_ctrl_id = param->irq_ctrl_id;
descriptor->extra = xil_dev;
xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
xil_dev->instance = calloc(1, sizeof(XScuGic));
if(!xil_dev->instance)
goto error;
config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
if(!config)
goto ps_error;
status = XScuGic_CfgInitialize(xil_dev->instance, config,
((XScuGic_Config *)config)->CpuBaseAddress);
if (status != SUCCESS)
goto ps_error;
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
xil_dev->instance);
break;
ps_error:
free(xil_dev->instance);
#endif
goto error;
case IRQ_PL:
#ifdef XINTC_H
xil_dev->instance = calloc(1, sizeof(XIntc));
if(!xil_dev->instance)
goto error;
status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
if(status != SUCCESS)
goto pl_error;
status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
if(status != SUCCESS)
goto pl_error;
break;
pl_error:
free(xil_dev->instance);
#endif
goto error;
default:
goto error;
break;
}
*desc = descriptor;
return SUCCESS;
error:
free(xil_dev);
free(descriptor);
return FAILURE;
}
/**
* @brief Enable global interrupts.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
{
/* Enable interrupts */
Xil_ExceptionEnable();
return SUCCESS;
}
/**
* @brief Disable global interrupts.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
{
/* Disable interrupts */
Xil_ExceptionDisable();
return SUCCESS;
}
/**
* @brief Enable specific interrupt.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
struct xil_irq_desc *xil_dev = desc->extra;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
XScuGic_Enable(xil_dev->instance, irq_id);
#endif
break;
case IRQ_PL:
#ifdef XINTC_H
XIntc_Enable(xil_dev->instance, irq_id);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Disable specific interrupt.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
struct xil_irq_desc *xil_dev = desc->extra;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
XScuGic_Disable(xil_dev->instance, irq_id);
#endif
break;
case IRQ_PL:
#ifdef XINTC_H
XIntc_Disable(xil_dev->instance, irq_id);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Register a callback to handle the irq events.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @param callback_desc - Callback descriptor
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
struct callback_desc *callback_desc)
{
struct xil_irq_desc *xil_dev = desc->extra;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
return XScuGic_Connect(xil_dev->instance, irq_id,
(Xil_InterruptHandler) callback_desc->callback,
callback_desc->ctx);
#endif
break;
case IRQ_PL:
#ifdef XINTC_H
if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
int32_t ret;
ret = XIntc_Connect(xil_dev->instance, irq_id,
XTmrCtr_InterruptHandler, callback_desc->config);
if (IS_ERR_VALUE(ret))
return FAILURE;
XTmrCtr_SetHandler(callback_desc->config,
(XTmrCtr_Handler)callback_desc->callback,
callback_desc->ctx);
return SUCCESS;
}
return XIntc_Connect(xil_dev->instance, irq_id,
(XInterruptHandler) callback_desc->callback,
callback_desc->ctx);
#endif
break;
default:
break;
}
return FAILURE;
}
/**
* @brief Set interrupt trigger level.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @param trig - New trigger level for the interrupt.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
enum irq_trig_level trig)
{
struct xil_irq_desc *xil_dev = desc->extra;
if(trig == IRQ_EDGE_BOTH)
return -EINVAL;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
;
uint8_t priority, trigger;
XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
&trigger);
trigger = trig;
XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
trigger);
return SUCCESS;
#endif
break;
case IRQ_PL:
#ifdef XINTC_H
/* Interrupt trigger determined in hardware. TODO: verify */
return SUCCESS;
#endif
break;
default:
break;
}
return FAILURE;
}
/**
* @brief Unregisters a generic IRQ handling function.
* @param desc - The IRQ controller descriptor.
* @param irq_id - Interrupt identifier.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
{
struct xil_irq_desc *xil_dev = desc->extra;
switch(xil_dev->type) {
case IRQ_PS:
#ifdef XSCUGIC_H
XScuGic_Disconnect(xil_dev->instance, irq_id);
#endif
break;
case IRQ_PL:
#ifdef XINTC_H
XIntc_Disconnect(xil_dev->instance, irq_id);
#endif
break;
default:
return FAILURE;
}
return SUCCESS;
}
/**
* @brief Free the resources allocated by irq_ctrl_init().
* @param desc - The IRQ control descriptor.
* @return SUCCESS in case of success, FAILURE otherwise.
*/
int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
{
struct xil_irq_desc *xil_dev = desc->extra;
free(xil_dev->instance);
free(desc->extra);
free(desc);
return SUCCESS;
}
/**
* @brief Xilinx platform specific IRQ platform ops structure
*/
const struct irq_platform_ops xil_irq_ops = {
.init = &xil_irq_ctrl_init,
.register_callback = &xil_irq_register_callback,
.unregister = &xil_irq_unregister,
.global_enable = &xil_irq_global_enable,
.global_disable = &xil_irq_global_disable,
.trigger_level_set = &xil_irq_trigger_level_set,
.enable = &xil_irq_enable,
.disable = &xil_irq_disable,
.remove = &xil_irq_ctrl_remove
};

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