test ad9361_mapping with vcs, update broken file

cmos mode works fine, but the timing of lvds mode needs more test

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v

@@ -0,0 +1,109 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 04:42:03 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_cmos_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_cmos_dual;
+
+reg clk_2x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_ch1_i = 'b0;
+reg [11:0] tx_ch1_q = 'b0;
+reg [11:0] tx_ch2_i = 'b0;
+reg [11:0] tx_ch2_q = 'b0;
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+
+wire clk_out;
+wire tx_frame;
+wire [11:0] tx_data;
+
+ad9361_tx_map_cmos_dual dut_tx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_ch1_i       (tx_ch1_i       ),
+    .tx_ch1_q       (tx_ch1_q       ),
+    .tx_ch2_i       (tx_ch2_i       ),
+    .tx_ch2_q       (tx_ch2_q       ),
+
+    .clk_out        (clk_out        ),
+    .tx_frame       (tx_frame       ),
+    .tx_data        (tx_data        )
+);
+
+ad9361_rx_map_cmos_dual dut_rx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ), // sync to output data
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),  // async fifo reset
+
+    .rx_frame       (tx_frame       ),
+    .rx_data        (tx_data        ),
+
+    .rx_ch1_i       (rx_ch1_i       ),
+    .rx_ch1_q       (rx_ch1_q       ),
+    .rx_ch2_i       (rx_ch2_i       ),
+    .rx_ch2_q       (rx_ch2_q       )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_2x_in = ~clk_2x_in;
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_ch1_i <= 'b0;
+        tx_ch1_q <= 'b0;
+        tx_ch2_i <= 'b0;
+        tx_ch2_q <= 'b0;
+    end
+    else begin
+        tx_ch1_i <= tx_ch1_i + 3'd1;
+        tx_ch1_q <= tx_ch1_q + 3'd2;
+        tx_ch2_i <= tx_ch2_i + 3'd3;
+        tx_ch2_q <= tx_ch2_q + 3'd4;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v

@@ -0,0 +1,94 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 04:34:43 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_cmos_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_cmos_single;
+
+reg clk_in = 'b0;
+reg clk_in_rst = 'b0;
+wire data_clk;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+wire [11:0] rx_data_i;
+wire [11:0] rx_data_q;
+
+wire clk_out;
+wire tx_frame;
+wire [11:0] tx_data;
+
+ad9361_tx_map_cmos_single dut_tx
+(
+    .clk_in         (clk_in         ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+
+    .clk_out        (clk_out        ),
+    .tx_frame       (tx_frame       ),
+    .tx_data        (tx_data        )
+);
+
+ad9361_rx_map_cmos_single dut_rx
+(
+    .clk_in         (clk_in         ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame       (tx_frame       ),
+    .rx_data        (tx_data        ),
+
+    .rx_data_i      (rx_data_i      ),
+    .rx_data_q      (rx_data_q      )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_in = ~clk_in;
+assign #7 data_clk = clk_in;
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else begin
+        tx_data_i <= tx_data_i + 2'd1;
+        tx_data_q <= tx_data_q + 2'd2;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v

@@ -0,0 +1,123 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 05:23:01 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_lvds_dual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_lvds_dual;
+
+reg clk_4x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_ch1_i = 'b0;
+reg [11:0] tx_ch1_q = 'b0;
+reg [11:0] tx_ch2_i = 'b0;
+reg [11:0] tx_ch2_q = 'b0;
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+
+wire clk_out_p;
+wire clk_out_n;
+wire tx_frame_p;
+wire tx_frame_n;
+wire [5:0] tx_data_p;
+wire [5:0] tx_data_n;
+
+ad9361_tx_map_lvds_dual dut_tx
+(
+    .clk_4x_in      (clk_4x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_ch1_i       (tx_ch1_i       ),
+    .tx_ch1_q       (tx_ch1_q       ),
+    .tx_ch2_i       (tx_ch2_i       ),
+    .tx_ch2_q       (tx_ch2_q       ),
+
+    .clk_out_p      (clk_out_p      ),
+    .clk_out_n      (clk_out_n      ),
+    .tx_frame_p     (tx_frame_p     ),
+    .tx_frame_n     (tx_frame_n     ),
+    .tx_data_p      (tx_data_p      ),
+    .tx_data_n      (tx_data_n      )
+);
+
+ad9361_rx_map_lvds_dual dut_rx
+(
+    .clk_4x_in      (clk_4x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame_p     (tx_frame_p     ),
+    .rx_frame_n     (tx_frame_n     ),
+    .rx_data_p      (tx_data_p      ),
+    .rx_data_n      (tx_data_n      ),
+
+    .rx_ch1_i       (rx_ch1_i       ),
+    .rx_ch1_q       (rx_ch1_q       ),
+    .rx_ch2_i       (rx_ch2_i       ),
+    .rx_ch2_q       (rx_ch2_q       )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+reg clk_2x_in = 'b0;
+
+always #40 clk_4x_in = ~clk_4x_in;
+
+always @(posedge clk_4x_in) begin
+    clk_2x_in <= ~clk_2x_in;
+end
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_ch1_i <= 'b0;
+        tx_ch1_q <= 'b0;
+        tx_ch2_i <= 'b0;
+        tx_ch2_q <= 'b0;
+    end
+    else begin
+        tx_ch1_i <= tx_ch1_i + 3'd1;
+        tx_ch1_q <= tx_ch1_q + 3'd2;
+        tx_ch2_i <= tx_ch2_i + 3'd3;
+        tx_ch2_q <= tx_ch2_q + 3'd4;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 03:43:52 PM
+// Design Name:
+// Module Name: tb_ad9361_trx_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_ad9361_trx_lvds_single;
+
+reg clk_2x_in = 'b0;
+reg clk_in_rst = 'b0;
+reg data_clk = 'b0;
+reg data_clk_rst = 'b0;
+reg [11:0] tx_data_i = 'b0;
+reg [11:0] tx_data_q = 'b0;
+wire [11:0] rx_data_i;
+wire [11:0] rx_data_q;
+
+wire clk_out_p;
+wire clk_out_n;
+wire tx_frame_p;
+wire tx_frame_n;
+wire [5:0] tx_data_p;
+wire [5:0] tx_data_n;
+
+ad9361_tx_map_lvds_single dut_tx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .tx_data_clk    (data_clk       ),
+    .tx_data_clk_rst(data_clk_rst   ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+
+    .clk_out_p      (clk_out_p      ),
+    .clk_out_n      (clk_out_n      ),
+    .tx_frame_p     (tx_frame_p     ),
+    .tx_frame_n     (tx_frame_n     ),
+    .tx_data_p      (tx_data_p      ),
+    .tx_data_n      (tx_data_n      )
+);
+
+ad9361_rx_map_lvds_single dut_rx
+(
+    .clk_2x_in      (clk_2x_in      ),
+    .clk_in_rst     (clk_in_rst     ),
+
+    .rx_data_clk    (data_clk       ),
+    .rx_data_clk_rst(data_clk_rst   ),
+
+    .rx_fifo_rst    (1'b0           ),
+
+    .rx_frame_p     (tx_frame_p     ),
+    .rx_frame_n     (tx_frame_n     ),
+    .rx_data_p      (tx_data_p      ),
+    .rx_data_n      (tx_data_n      ),
+
+    .rx_data_i      (rx_data_i      ),
+    .rx_data_q      (rx_data_q      )
+);
+
+initial begin
+    clk_in_rst = 1'b1;
+    data_clk_rst = 1'b1;
+    #102
+    clk_in_rst = 'b0;
+    #333
+    data_clk_rst = 'b0;
+end
+
+always #20 clk_2x_in = ~clk_2x_in;
+
+always @(posedge clk_2x_in) begin
+    #7 data_clk <= ~data_clk;
+end
+
+always @(posedge data_clk) begin
+    if (data_clk_rst) begin
+        tx_data_i <= 'b0;
+        tx_data_q <= 'b0;
+    end
+    else begin
+        tx_data_i <= tx_data_i + 2'd1;
+        tx_data_q <= tx_data_q + 2'd2;
+    end
+end
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v

@@ -45,13 +45,14 @@ module ad9361_rx_map_cmos_dual
     output  [11:0]  rx_ch2_q
 );
 
-genvar          m;
+genvar mm;
 
 // rx data
-wire [11:0] rx_data_i, rx_data_q;
+wire [11:0] rx_data_pos;
+wire [11:0] rx_data_neg;
 
 generate
-for (m=0; m<12; m=m+1) begin : rx_data_iddr
+for (mm = 0; mm < 12; mm = mm + 1) begin
 
 IDDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
@@ -63,17 +64,17 @@ IDDR #(
     .R              (1'b0           ),
     .S              (1'b0           ),
     .C              (clk_2x_in      ),
-    .D              (rx_data[m]     ),
-    .Q1             (rx_data_q[m]   ),
-    .Q2             (rx_data_i[m]   )
+    .D              (rx_data[mm]    ),
+    .Q1             (rx_data_pos[mm]),
+    .Q2             (rx_data_neg[mm])
 );
 
 end
 endgenerate
 
 // rx frame
-wire        rx_frame_i;
-wire        rx_frame_q;
+wire rx_frame_pos;
+wire rx_frame_neg;
 
 IDDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
@@ -86,49 +87,52 @@ IDDR #(
     .S              (1'b0           ),
     .C              (clk_2x_in      ),
     .D              (rx_frame       ),
-    .Q1             (rx_frame_q     ),
-    .Q2             (rx_frame_i     )
+    .Q1             (rx_frame_pos   ),
+    .Q2             (rx_frame_neg   )
 );
 
 // divide rx_data to dual channel
-reg     [11:0]  rx1_data_i = 'b0;
-reg     [11:0]  rx1_data_q = 'b0;
-reg     [11:0]  rx2_data_i = 'b0;
-reg     [11:0]  rx2_data_q = 'b0;
+reg [11:0] rx1_data_i = 'b0;
+reg [11:0] rx1_data_q = 'b0;
+reg [11:0] rx2_data_i = 'b0;
+reg [11:0] rx2_data_q = 'b0;
 
-wire            rx_fifo_wr_en;
-reg             rx_fifo_rd_en = 'b0;
+reg rx_fifo_wr_en = 'b0;
+reg rx_fifo_rd_en = 'b0;
 
-wire            rx_fifo_empty_1;
-wire            rx_fifo_empty_2;
-wire            rx_fifo_empty_3;
-wire            rx_fifo_empty_4;
-
-assign rx_fifo_wr_en = rx_frame_i; // align data & write enable
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
 
 always @ (posedge clk_2x_in) begin
     if (clk_in_rst) begin
         rx1_data_i <= 'b0;
-        rx2_data_i <= 'b0;
-    end
-    else if(rx_frame_i) begin
-        rx1_data_i <= rx_data_i;
-    end
-    else begin
-        rx2_data_i <= rx_data_i;
-    end
-end
-
-always @ (posedge clk_2x_in) begin
-    if (clk_in_rst) begin
         rx1_data_q <= 'b0;
+        rx2_data_i <= 'b0;
         rx2_data_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
     end
-    else if(rx_frame_q) begin
-        rx1_data_q <= rx_data_q;
+    else if({rx_frame_neg,rx_frame_pos} == 2'b11) begin
+        rx1_data_i <= rx_data_neg;
+        rx1_data_q <= rx_data_pos;
+        rx2_data_i <= rx2_data_i;
+        rx2_data_q <= rx2_data_q;
+        rx_fifo_wr_en <= 'b0;
+    end
+    else if({rx_frame_neg,rx_frame_pos} == 2'b00) begin
+        rx1_data_i <= rx1_data_i;
+        rx1_data_q <= rx1_data_q;
+        rx2_data_i <= rx_data_neg;
+        rx2_data_q <= rx_data_pos;
+        rx_fifo_wr_en <= 'b1;
     end
     else begin
-        rx2_data_q <= rx_data_q;
+        rx1_data_i <= 'd1234; // error
+        rx1_data_q <= 'd4321; // error
+        rx2_data_i <= 'd5678; // error
+        rx2_data_q <= 'd8765; // error
+        rx_fifo_wr_en <= 'b0;
     end
 end
 
@@ -143,54 +147,54 @@ end
 
 ad9361_fifo u_rx_fifo_ch1_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_2x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx1_data_i     ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx1_data_i                 ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch1_i                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch1_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_2x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx1_data_q     ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx1_data_q                 ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch1_q                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_2x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx2_data_i     ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_3)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx2_data_i                 ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch2_i                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_3            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_2x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx2_data_q     ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_4)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx2_data_q                 ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch2_q                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_4            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v

@@ -43,32 +43,71 @@ module ad9361_rx_map_cmos_single
     output  [11:0]  rx_data_q
 );
 
-genvar          m;
+genvar mm;
 
-// rx data
-wire [11:0] rx_raw_i, rx_raw_q;
+// rx data from port
+wire [11:0] rx_data_pos;
+wire [11:0] rx_data_neg;
 
 generate
-for (m=0; m<12; m=m+1) begin : rx_data_iddr
-
+for (mm = 0; mm < 12; mm = mm + 1) begin : rx_data_iddr
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
-    .INIT_Q1        (1'b0           ),
-    .INIT_Q2        (1'b0           ),
-    .SRTYPE         ("ASYNC"        )
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
 ) i_rx_data_iddr (
-    .CE             (1'b1           ),
-    .R              (1'b0           ),
-    .S              (1'b0           ),
-    .C              (clk_in         ),
-    .D              (rx_data[m]     ),
-    .Q1             (rx_raw_q[m]    ),
-    .Q2             (rx_raw_i[m]    )
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_in         ), // 1-bit clock input
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
 );
 
 end
 endgenerate
 
+// rx frame from port
+wire rx_frame_pos;
+wire rx_frame_neg;
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_frame_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_in         ), // 1-bit clock input
+    .D              (rx_frame       ), // 1-bit DDR data input
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
+);
+
+// rx data
+reg [11:0] rx_fifo_i = 'b0;
+reg [11:0] rx_fifo_q = 'b0;
+
+always @(posedge clk_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_i <= 'b0;
+        rx_fifo_q <= 'b0;
+    end
+    else begin
+        if ({rx_frame_neg,rx_frame_pos} == 2'b10) begin
+            rx_fifo_i <= rx_data_neg;
+            rx_fifo_q <= rx_data_pos;
+        end
+        else begin
+            rx_fifo_i <= 'd1234; // error
+            rx_fifo_q <= 'd4321; // error
+        end
+    end
+end
 
 // divide rx_data to dual channel
 reg             rx_fifo_wr_en = 1'b0;
@@ -97,28 +136,28 @@ end
 
 ad9361_fifo u_rx_fifo_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_in         ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx_raw_i       ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_data_i      ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_in                     ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_i                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_data_i                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_in         ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx_raw_q       ), // input wire [11 : 0] din
-    .wr_en      (rx_fifo_wr_en  ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
-    .dout       (rx_data_q      ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_in                     ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_q                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_data_q                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v

@@ -8,10 +8,9 @@
 // | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
-// Create Date: 2022/07/01 17:37:27
-// Last Modified Date: 2023/03/06 10:54
+// Create Date: 09/27/2024 04:49:13 PM
 // Design Name:
-// Module Name: ad9361_rx_mapping_dual
+// Module Name: ad9361_rx_map_lvds_dual
 // Project Name:
 // Target Devices:
 // Tool Versions:
@@ -47,155 +46,84 @@ module ad9361_rx_map_lvds_dual
     output  [11:0]  rx_ch2_q
 );
 
-genvar          m;
+genvar mm;
 
-// rx data
+// rx data from port
 wire [5:0] rx_data;
-wire [5:0] rx_data_i, rx_data_q;
+wire [5:0] rx_data_pos;
+wire [5:0] rx_data_neg;
 
 generate
-for (m=0; m<6; m=m+1) begin : rx_data_iddr
+for (mm = 0; mm < 6; mm = mm + 1) begin
 
 IBUFDS #(
-    .DIFF_TERM  ("TRUE"         )
-) u_ibufds_rx_data
+    .DIFF_TERM  ("TRUE"         )  // Differential Termination
+) u_rx_data_ibufds
 (
-    .I          (rx_data_p[m]   ),
-    .IB         (rx_data_n[m]   ),
-    .O          (rx_data[m]     )
+    .I          (rx_data_p[mm]  ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_data_n[mm]  ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_data[mm]    )  // Buffer output
 );
 
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
-    .INIT_Q1        (1'b0           ),
-    .INIT_Q2        (1'b0           ),
-    .SRTYPE         ("ASYNC"        )
-) u_rx_data_iddr (
-    .CE             (1'b1           ), // clock enable
-    .R              (1'b0           ), // iddr reset
-    .S              (1'b0           ), // iddr set
-    .C              (clk_4x_in      ), // iddr clock
-    .D              (rx_data[m]     ), // ddr data
-    .Q1             (rx_data_q[m]   ), // sdr data at rising edge
-    .Q2             (rx_data_i[m]   )  // sdr data at falling edge
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_data_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_4x_in      ), // 1-bit clock input
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
 );
 
 end
 endgenerate
 
-// rx frame
-wire            rx_frame;
-wire            rx_frame_i;
-wire            rx_frame_q;
+// rx frame from port
+wire rx_frame;
+wire rx_frame_pos;
+wire rx_frame_neg;
 
 IBUFDS #(
-    .DIFF_TERM  ("TRUE"     )
-) u_ibufds_rx_frame
+    .DIFF_TERM  ("TRUE"     )  // Differential Termination
+) u_rx_frame_ibufds
 (
-    .I          (rx_frame_p ),
-    .IB         (rx_frame_n ),
-    .O          (rx_frame   )
+    .I          (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_frame   )  // Buffer output
 );
 
 IDDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
-    .INIT_Q1        (1'b0           ),
-    .INIT_Q2        (1'b0           ),
-    .SRTYPE         ("ASYNC"        )
-) u_rx_frame_iddr (
-    .CE             (1'b1           ), // clock enable
-    .R              (1'b0           ), // iddr reset
-    .S              (1'b0           ), // iddr set
-    .C              (clk_4x_in      ), // iddr clock
-    .D              (rx_frame       ), // ddr data
-    .Q1             (rx_frame_q     ), // sdr data at rising edge
-    .Q2             (rx_frame_i     )  // sdr data at falling edge
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_frame_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_4x_in      ), // 1-bit clock input
+    .D              (rx_frame       ), // 1-bit DDR data input
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
 );
 
 // unpack rx frame & data
-reg             rx_frame_i_d1   = 'b0;
-reg     [ 5:0]  rx_data_i_d1    = 'b0;
-reg     [ 5:0]  rx_data_q_d1    = 'b0;
-reg             rx_flag         = 'b0; // rx frame rising edge indicator
-reg     [ 1:0]  rx_cnt          = 'b0; // unpack stage counter
+reg rx_frame_pos_d = 'b0;
+reg rx_frame_neg_d = 'b0;
 
-always @(posedge clk_4x_in) begin
-    // wait for [rx_flag]
-    rx_frame_i_d1 <= rx_frame_i;
-     rx_data_i_d1 <=  rx_data_i;
-     rx_data_q_d1 <=  rx_data_q;
-end
+reg [11:0] rx_fifo_ch1_i = 'b0;
+reg [11:0] rx_fifo_ch1_q = 'b0;
+reg [11:0] rx_fifo_ch2_i = 'b0;
+reg [11:0] rx_fifo_ch2_q = 'b0;
 
-always @(posedge clk_4x_in) begin
-    if (clk_in_rst) begin
-        rx_flag <= 'b0;
-    end
-    else if (~rx_frame_i_d1 & rx_frame_i) begin
-        // assert when rising edge of rx frame is detected
-        rx_flag <= 'b1;
-    end
-    else begin
-        rx_flag <= rx_flag;
-    end
-end
+reg rx_fifo_wr_en = 'b0;
+reg rx_fifo_rd_en = 'b0;
 
-always @(posedge clk_4x_in) begin
-    if (clk_in_rst) begin
-        rx_cnt <= 'b0;
-    end
-    else begin
-        rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt;
-    end
-end
-
-reg     [11:0]  rx1_data_i = 'b0;
-reg     [11:0]  rx1_data_q = 'b0;
-reg     [11:0]  rx2_data_i = 'b0;
-reg     [11:0]  rx2_data_q = 'b0;
-
-always @(posedge clk_4x_in) begin
-    if (clk_in_rst) begin
-        rx1_data_i <= 'b0;
-        rx1_data_q <= 'b0;
-        rx2_data_i <= 'b0;
-        rx2_data_q <= 'b0;
-    end
-    else begin
-        case (rx_cnt)
-            3'd0: begin
-                // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data
-                rx1_data_i[11:6] <= rx_data_i_d1;
-                rx1_data_q[11:6] <= rx_data_q_d1;
-            end
-            3'd1: begin
-                // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data
-                rx1_data_i[ 5:0] <= rx_data_i_d1;
-                rx1_data_q[ 5:0] <= rx_data_q_d1;
-            end
-            3'd2: begin
-                // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data
-                rx2_data_i[11:6] <= rx_data_i_d1;
-                rx2_data_q[11:6] <= rx_data_q_d1;
-            end
-            3'd3: begin
-                // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data
-                rx2_data_i[ 5:0] <= rx_data_i_d1;
-                rx2_data_q[ 5:0] <= rx_data_q_d1;
-            end
-            default: begin
-                rx1_data_i <= 'b0;
-                rx1_data_q <= 'b0;
-                rx2_data_i <= 'b0;
-                rx2_data_q <= 'b0;
-            end
-        endcase
-    end
-end
-
-// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock
-// read fifo at every clock cycle with 48MHz clock
-reg fifo_wr_en = 'b0;
-reg fifo_rd_en = 'b0;
 wire rx_fifo_empty_1;
 wire rx_fifo_empty_2;
 wire rx_fifo_empty_3;
@@ -203,75 +131,122 @@ wire rx_fifo_empty_4;
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        fifo_wr_en <= 'b0;
-    end
-    else if (rx_cnt == 2'd3) begin
-        fifo_wr_en <= 1'b1;
+        rx_frame_pos_d <= 'b0;
+        rx_frame_neg_d <= 'b0;
     end
     else begin
-        fifo_wr_en <= 'b0;
+        rx_frame_pos_d <= rx_frame_pos;
+        rx_frame_neg_d <= rx_frame_neg;
     end
 end
 
-always @(posedge rx_data_clk) begin
-    if (rx_data_clk_rst) begin
-        fifo_rd_en <= 1'b0;
+always @(posedge clk_4x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_ch1_i <= 'b0;
+        rx_fifo_ch1_q <= 'b0;
+        rx_fifo_ch2_i <= 'b0;
+        rx_fifo_ch2_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
     end
     else begin
-        fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4};
+        case ({rx_frame_neg_d,rx_frame_pos_d,rx_frame_neg,rx_frame_pos})
+            4'b0011: begin
+                rx_fifo_ch1_i[11:6] <= rx_data_neg;
+                rx_fifo_ch1_q[11:6] <= rx_data_pos;
+                rx_fifo_ch2_i <= rx_fifo_ch2_i;
+                rx_fifo_ch2_q <= rx_fifo_ch2_q;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b1111: begin
+                rx_fifo_ch1_i[5:0] <= rx_data_neg;
+                rx_fifo_ch1_q[5:0] <= rx_data_pos;
+                rx_fifo_ch2_i <= rx_fifo_ch2_i;
+                rx_fifo_ch2_q <= rx_fifo_ch2_q;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b1100: begin
+                rx_fifo_ch1_i <= rx_fifo_ch1_i;
+                rx_fifo_ch1_q <= rx_fifo_ch1_q;
+                rx_fifo_ch2_i[11:6] <= rx_data_neg;
+                rx_fifo_ch2_q[11:6] <= rx_data_pos;
+                rx_fifo_wr_en <= 'b0;
+            end
+            4'b0000: begin
+                rx_fifo_ch1_i <= rx_fifo_ch1_i;
+                rx_fifo_ch1_q <= rx_fifo_ch1_q;
+                rx_fifo_ch2_i[5:0] <= rx_data_neg;
+                rx_fifo_ch2_q[5:0] <= rx_data_pos;
+                rx_fifo_wr_en <= 1'b1;
+            end
+            default: begin
+                rx_fifo_ch1_i <= 'd1234; // error
+                rx_fifo_ch1_q <= 'd4321; // error
+                rx_fifo_ch2_i <= 'd5678; // error
+                rx_fifo_ch2_q <= 'd8765; // error
+                rx_fifo_wr_en <= 'b0;
+            end
+        endcase
+    end
+end
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2,~rx_fifo_empty_3, ~rx_fifo_empty_4};
     end
 end
 
 ad9361_fifo u_rx_fifo_ch1_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_4x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx1_data_i     ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
-    .dout       (rx_ch1_i       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_1)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_4x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_ch1_i              ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch1_i                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_1            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch1_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_4x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx1_data_q     ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
-    .dout       (rx_ch1_q       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_2)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_4x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_ch1_q              ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch1_q                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_2            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_i
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_4x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx2_data_i     ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
-    .dout       (rx_ch2_i       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_3)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_4x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_ch2_i              ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch2_i                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_3            )  // output wire empty
 );
 
 ad9361_fifo u_rx_fifo_ch2_q
 (
-    .rst        (rx_fifo_rst    ), // input wire rst
-    .wr_clk     (clk_4x_in      ), // input wire wr_clk
-    .rd_clk     (rx_data_clk    ), // input wire rd_clk
-    .din        (rx2_data_q     ), // input wire [11 : 0] din
-    .wr_en      (fifo_wr_en     ), // input wire wr_en
-    .rd_en      (fifo_rd_en     ), // input wire rd_en
-    .dout       (rx_ch2_q       ), // output wire [11 : 0] dout
-    .full       (               ), // output wire full
-    .empty      (rx_fifo_empty_4)  // output wire empty
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_4x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_ch2_q              ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_ch2_q                   ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_4            )  // output wire empty
 );
 
 endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v

@@ -0,0 +1,182 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/07/01 17:37:27
+// Last Modified Date: 2023/03/03 13:01
+// Design Name:
+// Module Name: ad9361_rx_map_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_rx_map_lvds_single
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           rx_data_clk     ,
+    input           rx_data_clk_rst ,
+
+    input           rx_fifo_rst     ,
+
+    input           rx_frame_p      ,
+    input           rx_frame_n      ,
+    input   [ 5:0]  rx_data_p       ,
+    input   [ 5:0]  rx_data_n       ,
+
+    output  [11:0]  rx_data_i       ,
+    output  [11:0]  rx_data_q
+);
+
+genvar mm;
+
+// rx data from port
+wire [5:0] rx_data;
+wire [5:0] rx_data_pos;
+wire [5:0] rx_data_neg;
+
+generate
+for (mm = 0; mm < 6; mm = mm + 1) begin
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"         )  // Differential Termination
+) u_rx_data_ibufds
+(
+    .I          (rx_data_p[mm]  ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_data_n[mm]  ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_data[mm]    )  // Buffer output
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_data_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_2x_in      ), // 1-bit clock input
+    .D              (rx_data[mm]    ), // 1-bit DDR data input
+    .Q1             (rx_data_pos[mm]), // 1-bit output for positive edge of clock
+    .Q2             (rx_data_neg[mm])  // 1-bit output for negative edge of clock
+);
+
+end
+endgenerate
+
+// rx frame from port
+wire rx_frame;
+wire rx_frame_pos;
+wire rx_frame_neg;
+
+IBUFDS #(
+    .DIFF_TERM  ("TRUE"     )  // Differential Termination
+) u_rx_frame_ibufds
+(
+    .I          (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port)
+    .IB         (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port)
+    .O          (rx_frame   )  // Buffer output
+);
+
+IDDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED"
+    .INIT_Q1        (1'b0           ), // Initial value of Q1: 1'b0 or 1'b1
+    .INIT_Q2        (1'b0           ), // Initial value of Q2: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
+) i_rx_frame_iddr (
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_2x_in      ), // 1-bit clock input
+    .D              (rx_frame       ), // 1-bit DDR data input
+    .Q1             (rx_frame_pos   ), // 1-bit output for positive edge of clock
+    .Q2             (rx_frame_neg   )  // 1-bit output for negative edge of clock
+);
+
+// unpack rx frame & data
+reg [11:0] rx_fifo_i = 'b0;
+reg [11:0] rx_fifo_q = 'b0;
+reg rx_fifo_wr_en = 'b0;
+reg rx_fifo_rd_en = 'b0;
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        rx_fifo_i <= 'b0;
+        rx_fifo_q <= 'b0;
+        rx_fifo_wr_en <= 'b0;
+    end
+    else begin
+        if ({rx_frame_neg,rx_frame_pos} == 2'b11) begin
+            rx_fifo_i[11:6] <= rx_data_neg;
+            rx_fifo_q[11:6] <= rx_data_pos;
+            rx_fifo_wr_en <= 'b0;
+        end
+        else if ({rx_frame_neg,rx_frame_pos} == 2'b00) begin
+            rx_fifo_i[5:0] <= rx_data_neg;
+            rx_fifo_q[5:0] <= rx_data_pos;
+            rx_fifo_wr_en <= 1'b1;
+        end
+        else begin
+            rx_fifo_i <= 'd1234; // error
+            rx_fifo_q <= 'd4321; // error
+            rx_fifo_wr_en <= 'b0;
+        end
+    end
+end
+
+always @(posedge rx_data_clk) begin
+    if (rx_data_clk_rst) begin
+        rx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2};
+    end
+end
+
+ad9361_fifo u_rx_fifo_i
+(
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_i                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (1'b1                       ), // input wire rd_en
+    .dout       (rx_data_i                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_1            )  // output wire empty
+);
+
+ad9361_fifo u_rx_fifo_q
+(
+    .rst        (clk_in_rst || rx_fifo_rst  ), // input wire rst
+    .wr_clk     (clk_2x_in                  ), // input wire wr_clk
+    .rd_clk     (rx_data_clk                ), // input wire rd_clk
+    .din        (rx_fifo_q                  ), // input wire [11 : 0] din
+    .wr_en      (rx_fifo_wr_en              ), // input wire wr_en
+    .rd_en      (rx_fifo_rd_en              ), // input wire rd_en
+    .dout       (rx_data_q                  ), // output wire [11 : 0] dout
+    .full       (                           ), // output wire full
+    .empty      (rx_fifo_empty_2            )  // output wire empty
+);
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v

@@ -9,7 +9,7 @@
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
 // Create Date: 2022/07/01 16:39:19
-// Last Modified Date: 2023/03/06 11:45
+// Last Modified Date: 2024/09/27 16:22
 // Design Name:
 // Module Name: ad9361_tx_map_cmos_dual
 // Project Name:
@@ -44,21 +44,31 @@ module ad9361_tx_map_cmos_dual
     output  [11:0]  tx_data
 );
 
-genvar m;
+genvar mm;
 
 // input data fifo
-reg rx_fifo_rd_en = 'b0;
+reg tx_fifo_rd_en = 'b0;
 wire [11:0] tx_fifo_ch1_i;
 wire [11:0] tx_fifo_ch1_q;
 wire [11:0] tx_fifo_ch2_i;
 wire [11:0] tx_fifo_ch2_q;
 
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
 always @(posedge clk_2x_in) begin
     if (clk_in_rst) begin
-        rx_fifo_rd_en <= 'b0;
+        tx_fifo_rd_en <= 'b0;
     end
     else begin
-        rx_fifo_rd_en <= ~rx_fifo_rd_en;
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
+            tx_fifo_rd_en <= ~tx_fifo_rd_en;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
     end
 end
 
@@ -69,10 +79,10 @@ ad9361_fifo u_tx_fifo_ch1_i
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch1_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_1)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch1_q
@@ -82,10 +92,10 @@ ad9361_fifo u_tx_fifo_ch1_q
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch1_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_2)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_i
@@ -95,10 +105,10 @@ ad9361_fifo u_tx_fifo_ch2_i
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch2_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_3)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_q
@@ -108,10 +118,10 @@ ad9361_fifo u_tx_fifo_ch2_q
     .rd_clk     (clk_2x_in      ), // input wire rd_clk
     .din        (tx_ch2_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_4)  // output wire empty
 );
 
 // frame and data control
@@ -127,7 +137,7 @@ always @(posedge clk_2x_in) begin
         tx_data_i <= 'b0;
         tx_data_q <= 'b0;
     end
-    else if (rx_fifo_rd_en == 1'b0) begin
+    else if (tx_fifo_rd_en == 1'b0) begin
         tx_frame_i <= 1'b1;
         tx_frame_q <= 1'b1;
         tx_data_i <= tx_fifo_ch1_i;
@@ -159,22 +169,22 @@ ODDR #(
     .Q              (tx_frame       )
 );
 
-// output tx data to port
 generate
-for (m=0; m<12; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 12; mm = mm + 1) begin
 
+// output tx data to port
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"   ),
     .INIT           (1'b0          ),
     .SRTYPE         ("ASYNC"       )
-) u_tx_data_oddr  (
+) u_tx_data_oddr (
     .CE             (1'b1          ),
     .R              (1'b0          ),
     .S              (1'b0          ),
     .C              (clk_2x_in     ),
-    .D1             (tx_data_i[m]  ),
-    .D2             (tx_data_q[m]  ),
-    .Q              (tx_data[m]    )
+    .D1             (tx_data_i[mm] ),
+    .D2             (tx_data_q[mm] ),
+    .Q              (tx_data[mm]   )
 );
 
 end

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v

@@ -41,7 +41,7 @@ module ad9361_tx_map_cmos_single
     output  [11:0]  tx_data
 );
 
-genvar m;
+genvar mm;
 
 // inout data fifo
 wire [11:0] tx_fifo_i;
@@ -82,35 +82,35 @@ assign clk_out = clk_in;
 
 // output tx frame to port
 ODDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
-    .INIT           (1'b0           ),
-    .SRTYPE         ("ASYNC"        )
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ), // "OPPOSITE_EDGE" or "SAME_EDGE"
+    .INIT           (1'b0           ), // Initial value of Q: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"        )  // Set/Reset type: "SYNC" or "ASYNC"
 ) u_tx_frame_oddr (
-    .CE             (1'b1           ),
-    .R              (1'b0           ),
-    .S              (1'b0           ),
-    .C              (clk_in         ),
-    .D1             (tx_frame_i     ),
-    .D2             (tx_frame_q     ),
-    .Q              (tx_frame       )
+    .CE             (1'b1           ), // 1-bit clock enable input
+    .R              (1'b0           ), // 1-bit reset
+    .S              (1'b0           ), // 1-bit set
+    .C              (clk_in         ), // 1-bit clock input
+    .D1             (tx_frame_i     ), // 1-bit data input (positive edge)
+    .D2             (tx_frame_q     ), // 1-bit data input (negative edge)
+    .Q              (tx_frame       )  // 1-bit DDR output
 );
 
 // output tx data to port
 generate
-for (m=0; m<12; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 12; mm = mm + 1) begin: tx_data_oddr
 
 ODDR #(
-    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
-    .INIT           (1'b0          ),
-    .SRTYPE         ("ASYNC"       )
-) u_tx_data_oddr  (
-    .CE             (1'b1          ),
-    .R              (1'b0          ),
-    .S              (1'b0          ),
-    .C              (clk_in        ),
-    .D1             (tx_fifo_i[m]  ),
-    .D2             (tx_fifo_q[m]  ),
-    .Q              (tx_data[m]    )
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ), // "OPPOSITE_EDGE" or "SAME_EDGE"
+    .INIT           (1'b0          ), // Initial value of Q: 1'b0 or 1'b1
+    .SRTYPE         ("ASYNC"       )  // Set/Reset type: "SYNC" or "ASYNC"
+) u_tx_data_oddr (
+    .CE             (1'b1          ), // 1-bit clock enable input
+    .R              (1'b0          ), // 1-bit reset
+    .S              (1'b0          ), // 1-bit set
+    .C              (clk_in        ), // 1-bit clock input
+    .D1             (tx_fifo_i[mm] ), // 1-bit data input (positive edge)
+    .D2             (tx_fifo_q[mm] ), // 1-bit data input (negative edge)
+    .Q              (tx_data[mm]   )  // 1-bit DDR output
 );
 
 end

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v

@@ -8,8 +8,7 @@
 // | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
 //  \___/ \___/|___/_| |_|  \____|\__,_|\___/
 //
-// Create Date: 2023/03/05 23:21:27
-// Last Modified Date: 2023/03/06 11:01
+// Create Date: 09/27/2024 03:26:45 PM
 // Design Name:
 // Module Name: ad9361_tx_map_lvds_dual
 // Project Name:
@@ -47,34 +46,41 @@ module ad9361_tx_map_lvds_dual
     output  [ 5:0]  tx_data_n
 );
 
-genvar m;
+genvar mm;
 
 // input data fifo
-reg [1:0] tx_control_cnt = 'b0;
-reg rx_fifo_rd_en = 'b0;
+reg [1:0] tx_fifo_rd_en_cnt = 'b0;
+reg tx_fifo_rd_en = 'b0;
 wire [11:0] tx_fifo_ch1_i;
 wire [11:0] tx_fifo_ch1_q;
 wire [11:0] tx_fifo_ch2_i;
 wire [11:0] tx_fifo_ch2_q;
 
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+wire rx_fifo_empty_3;
+wire rx_fifo_empty_4;
+
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        tx_control_cnt <= 'b0;
+        tx_fifo_rd_en_cnt <= 'b0;
     end
     else begin
-        tx_control_cnt <= tx_control_cnt + 1'b1;
+        tx_fifo_rd_en_cnt <= tx_fifo_rd_en_cnt + 1'b1;
     end
 end
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        rx_fifo_rd_en <= 'b0;
-    end
-    else if (tx_control_cnt == 2'd2) begin
-        rx_fifo_rd_en <= 1'b1;
+        tx_fifo_rd_en <= 'b0;
     end
     else begin
-        rx_fifo_rd_en <= 'b0;
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin
+            tx_fifo_rd_en <= (tx_fifo_rd_en_cnt == 2'd3) ? 1'b1 : 'b0;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
     end
 end
 
@@ -85,10 +91,10 @@ ad9361_fifo u_tx_fifo_ch1_i
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch1_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_1)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch1_q
@@ -98,10 +104,10 @@ ad9361_fifo u_tx_fifo_ch1_q
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch1_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch1_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_2)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_i
@@ -111,10 +117,10 @@ ad9361_fifo u_tx_fifo_ch2_i
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch2_i       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_i  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_3)  // output wire empty
 );
 
 ad9361_fifo u_tx_fifo_ch2_q
@@ -124,57 +130,56 @@ ad9361_fifo u_tx_fifo_ch2_q
     .rd_clk     (clk_4x_in      ), // input wire rd_clk
     .din        (tx_ch2_q       ), // input wire [11 : 0] din
     .wr_en      (1'b1           ), // input wire wr_en
-    .rd_en      (rx_fifo_rd_en  ), // input wire rd_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
     .dout       (tx_fifo_ch2_q  ), // output wire [11 : 0] dout
     .full       (               ), // output wire full
-    .empty      (               )  // output wire empty
+    .empty      (rx_fifo_empty_4)  // output wire empty
 );
 
-
 // frame and data control
-reg tx_frame_r = 'b0; // rising edge data
-reg tx_frame_f = 'b0; // falling edge data
-reg [5:0] tx_data_r = 'b0;
-reg [5:0] tx_data_f = 'b0;
+reg tx_frame_i = 'b0;
+reg tx_frame_q = 'b0;
+reg [5:0] tx_buf_i = 'b0;
+reg [5:0] tx_buf_q = 'b0;
 
 always @(posedge clk_4x_in) begin
     if (clk_in_rst) begin
-        tx_frame_r <= 'b0;
-        tx_frame_f <= 'b0;
-        tx_data_r <= 'b0;
-        tx_data_f <= 'b0;
+        tx_frame_i <= 'b0;
+        tx_frame_q <= 'b0;
+        tx_buf_i <= 'b0;
+        tx_buf_q <= 'b0;
     end
     else begin
-        case (tx_control_cnt)
+        case (tx_fifo_rd_en_cnt)
             2'd0: begin
-                tx_frame_r <= 1'b1;
-                tx_frame_f <= 1'b1;
-                tx_data_r <= tx_fifo_ch1_i[11: 6];
-                tx_data_f <= tx_fifo_ch1_q[11: 6];
+                tx_frame_i <= 1'b1;
+                tx_frame_q <= 1'b1;
+                tx_buf_i <= tx_fifo_ch1_i[11:6];
+                tx_buf_q <= tx_fifo_ch1_q[11:6];
             end
             2'd1: begin
-                tx_frame_r <= 1'b1;
-                tx_frame_f <= 1'b1;
-                tx_data_r <= tx_fifo_ch1_i[5:0];
-                tx_data_f <= tx_fifo_ch1_q[5:0];
+                tx_frame_i <= 1'b1;
+                tx_frame_q <= 1'b1;
+                tx_buf_i <= tx_fifo_ch1_i[5:0];
+                tx_buf_q <= tx_fifo_ch1_q[5:0];
             end
             2'd2: begin
-                tx_frame_r <= 1'b0;
-                tx_frame_f <= 1'b0;
-                tx_data_r <= tx_fifo_ch2_i[11:6];
-                tx_data_f <= tx_fifo_ch2_q[11:6];
+                tx_frame_i <= 1'b0;
+                tx_frame_q <= 1'b0;
+                tx_buf_i <= tx_fifo_ch2_i[11:6];
+                tx_buf_q <= tx_fifo_ch2_q[11:6];
             end
             2'd3: begin
-                tx_frame_r <= 1'b0;
-                tx_frame_f <= 1'b0;
-                tx_data_r <= tx_fifo_ch2_i[5:0];
-                tx_data_f <= tx_fifo_ch2_q[5:0];
+                tx_frame_i <= 1'b0;
+                tx_frame_q <= 1'b0;
+                tx_buf_i <= tx_fifo_ch2_i[5:0];
+                tx_buf_q <= tx_fifo_ch2_q[5:0];
             end
             default: begin
-                tx_frame_r <= 'b0;
-                tx_frame_f <= 'b0;
-                tx_data_r <= 'b0;
-                tx_data_f <= 'b0;
+                tx_frame_i <= 'b0; // error
+                tx_frame_q <= 'b0; // error
+                tx_buf_i <= 'b0; // error
+                tx_buf_q <= 'b0; // error
             end
         endcase
     end
@@ -182,9 +187,10 @@ end
 
 // output clock to port
 wire clk_out;
+
 assign clk_out = clk_4x_in;
 
-OBUFDS u_obufds_clk_out
+OBUFDS u_clk_out_obufds
 (
     .I  (clk_out    ),
     .O  (clk_out_p  ),
@@ -192,6 +198,8 @@ OBUFDS u_obufds_clk_out
 );
 
 // output tx frame to port
+wire tx_frame;
+
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"    ),
     .INIT           (1'b0           ),
@@ -201,46 +209,46 @@ ODDR #(
     .R              (1'b0           ),
     .S              (1'b0           ),
     .C              (clk_4x_in      ),
-    .D1             (tx_frame_r     ),
-    .D2             (tx_frame_f     ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
     .Q              (tx_frame       )
 );
 
-OBUFDS u_obufds_tx_frame
+OBUFDS u_tx_frame_obufds
 (
-    .I  (tx_frame   ),
-    .O  (tx_frame_p ),
-    .OB (tx_frame_n )
+    .O  (tx_frame_p ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_frame   )  // Buffer input
 );
 
-// output tx data to port
+// ouput tx data to port
 wire [5:0] tx_data;
 
 generate
-for (m=0; m<6; m=m+1) begin: tx_data_oddr
+for (mm = 0; mm < 6; mm = mm + 1) begin
 
 ODDR #(
     .DDR_CLK_EDGE   ("SAME_EDGE"   ),
     .INIT           (1'b0          ),
     .SRTYPE         ("ASYNC"       )
-) u_tx_data_oddr  (
+) u_tx_data_oddr (
     .CE             (1'b1          ),
     .R              (1'b0          ),
     .S              (1'b0          ),
     .C              (clk_4x_in     ),
-    .D1             (tx_data_r[m]  ),
-    .D2             (tx_data_f[m]  ),
-    .Q              (tx_data[m]    )
+    .D1             (tx_buf_i[mm]  ),
+    .D2             (tx_buf_q[mm]  ),
+    .Q              (tx_data[mm]   )
 );
 
-OBUFDS u_obufds_tx_data
+OBUFDS u_tx_data_obufds
 (
-    .I  (tx_data[m]     ),
-    .O  (tx_data_p[m]   ),
-    .OB (tx_data_n[m]   )
+    .O  (tx_data_p[mm]  ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_data_n[mm]  ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_data[mm]    )  // Buffer input
 );
 
 end
 endgenerate
 
-endmodule
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v

@@ -0,0 +1,187 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09/27/2024 03:26:45 PM
+// Design Name:
+// Module Name: ad9361_tx_map_lvds_single
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_tx_map_lvds_single
+(
+    input           clk_2x_in       ,
+    input           clk_in_rst      ,
+
+    input           tx_data_clk     ,
+    input           tx_data_clk_rst ,
+
+    input   [11:0]  tx_data_i       ,
+    input   [11:0]  tx_data_q       ,
+
+    output          clk_out_p       ,
+    output          clk_out_n       ,
+    output          tx_frame_p      ,
+    output          tx_frame_n      ,
+    output  [ 5:0]  tx_data_p       ,
+    output  [ 5:0]  tx_data_n
+);
+
+genvar mm;
+
+// input data fifo
+reg tx_fifo_rd_en = 'b0;
+wire [11:0] tx_fifo_i;
+wire [11:0] tx_fifo_q;
+
+wire rx_fifo_empty_1;
+wire rx_fifo_empty_2;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_fifo_rd_en <= 'b0;
+    end
+    else begin
+        if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2}) begin
+            tx_fifo_rd_en <= ~tx_fifo_rd_en;
+        end
+        else begin
+            tx_fifo_rd_en <= 'b0;
+        end
+    end
+end
+
+ad9361_fifo u_tx_fifo_i
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_data_i      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_i      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_1)  // output wire empty
+);
+
+ad9361_fifo u_tx_fifo_q
+(
+    .rst        (clk_in_rst     ), // input wire rst
+    .wr_clk     (tx_data_clk    ), // input wire wr_clk
+    .rd_clk     (clk_2x_in      ), // input wire rd_clk
+    .din        (tx_data_q      ), // input wire [11 : 0] din
+    .wr_en      (1'b1           ), // input wire wr_en
+    .rd_en      (tx_fifo_rd_en  ), // input wire rd_en
+    .dout       (tx_fifo_q      ), // output wire [11 : 0] dout
+    .full       (               ), // output wire full
+    .empty      (rx_fifo_empty_2)  // output wire empty
+);
+
+// frame and data control
+reg tx_frame_i = 'b0;
+reg tx_frame_q = 'b0;
+reg [ 5:0] tx_buf_i = 'b0;
+reg [ 5:0] tx_buf_q = 'b0;
+
+always @(posedge clk_2x_in) begin
+    if (clk_in_rst) begin
+        tx_frame_i <= 'b0;
+        tx_frame_q <= 'b0;
+        tx_buf_i <= 'b0;
+        tx_buf_q <= 'b0;
+    end
+    else begin
+        if (tx_fifo_rd_en == 1'b0) begin
+            tx_frame_i <= 1'b1;
+            tx_frame_q <= 1'b1;
+            tx_buf_i <= tx_fifo_i[11:6];
+            tx_buf_q <= tx_fifo_q[11:6];
+        end
+        else begin
+            tx_frame_i <= 1'b0;
+            tx_frame_q <= 1'b0;
+            tx_buf_i <= tx_fifo_i[5:0];
+            tx_buf_q <= tx_fifo_q[5:0];
+        end
+    end
+end
+
+// output clock to port
+wire clk_out;
+
+assign clk_out = clk_2x_in;
+
+OBUFDS u_clk_out_obufds
+(
+    .I  (clk_out    ),
+    .O  (clk_out_p  ),
+    .OB (clk_out_n  )
+);
+
+// output tx frame to port
+wire tx_frame;
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"    ),
+    .INIT           (1'b0           ),
+    .SRTYPE         ("ASYNC"        )
+) u_tx_frame_oddr (
+    .CE             (1'b1           ),
+    .R              (1'b0           ),
+    .S              (1'b0           ),
+    .C              (clk_2x_in      ),
+    .D1             (tx_frame_i     ),
+    .D2             (tx_frame_q     ),
+    .Q              (tx_frame       )
+);
+
+OBUFDS u_tx_frame_obufds
+(
+    .O  (tx_frame_p ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_frame   )  // Buffer input
+);
+
+// ouput tx data to port
+wire [5:0] tx_data;
+
+generate
+for (mm = 0; mm < 6; mm = mm + 1) begin
+
+ODDR #(
+    .DDR_CLK_EDGE   ("SAME_EDGE"   ),
+    .INIT           (1'b0          ),
+    .SRTYPE         ("ASYNC"       )
+) u_tx_data_oddr (
+    .CE             (1'b1          ),
+    .R              (1'b0          ),
+    .S              (1'b0          ),
+    .C              (clk_2x_in     ),
+    .D1             (tx_buf_i[mm]  ),
+    .D2             (tx_buf_q[mm]  ),
+    .Q              (tx_data[mm]   )
+);
+
+OBUFDS u_tx_data_obufds
+(
+    .O  (tx_data_p[mm]  ), // Diff_p output (connect directly to top-level port)
+    .OB (tx_data_n[mm]  ), // Diff_n output (connect directly to top-level port)
+    .I  (tx_data[mm]    )  // Buffer input
+);
+
+end
+endgenerate
+
+endmodule

modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr

@@ -9,12 +9,12 @@
   <Configuration>
     <Option Name="Id" Val="56c7290e44de4c80a4f826edd9352d43"/>
     <Option Name="Part" Val="xc7z100ffg900-2"/>
-    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../Tools/Xilinx/CompLib/vcs/2024.1"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
     <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
     <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
     <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirVCS" Val="$PPRDIR/../../../../../../Tools/Xilinx/CompLib/vcs/2024.1"/>
     <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
     <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
     <Option Name="SimulatorInstallDirModelSim" Val=""/>
@@ -43,6 +43,7 @@
     <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="TargetSimulator" Val="VCS"/>
     <Option Name="BoardPart" Val=""/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
@@ -62,7 +63,7 @@
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
-    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="4"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
     <Option Name="WTXSimExportSim" Val="1"/>
@@ -89,13 +90,29 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_single.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_lvds_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
@@ -104,7 +121,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_rx_map_cmos_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -112,7 +129,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_lvds_dual.v">
+      <File Path="$PSRCDIR/sources_1/new/ad9361_tx_map_cmos_dual.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -138,8 +155,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TopModule" Val="ad9361_tx_map_lvds_single"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -150,9 +166,40 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_cmos_dual.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_lvds_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_cmos_single.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_ad9361_trx_lvds_dual.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="ad9361_rx_map_cmos_dual"/>
+        <Option Name="TopModule" Val="tb_ad9361_trx_cmos_dual"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -163,10 +210,20 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="vcs.compile.vlogan.more_options" Val="-v2005 -kdb"/>
+        <Option Name="vcs.elaborate.vcs.more_options" Val="-debug_access+all"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
       <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
@@ -207,9 +264,11 @@
     </Simulator>
   </Simulators>
   <Runs Version="1" Minor="22">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -229,7 +288,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/constrs_1/new/dj_47dr.xdc

@@ -6,15 +6,15 @@ set_property  -dict  {PACKAGE_PIN A13   IOSTANDARD LVCMOS33}  [get_ports lmk_spi
 set_property  -dict  {PACKAGE_PIN C14   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_mosi           ] ;# LMK_SPI_SDI
 set_property  -dict  {PACKAGE_PIN A14   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_miso           ] ;# LMK_SPI_SDO
 
-set_property  -dict  {PACKAGE_PIN H14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_sck        ] ;# LMX_RF_ADC_SCK
-set_property  -dict  {PACKAGE_PIN H15   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_cs         ] ;# LMX_RF_ADC_CS
-set_property  -dict  {PACKAGE_PIN G13   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_mosi       ] ;# LMX_RF_ADC_SDI
-set_property  -dict  {PACKAGE_PIN K14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_miso       ] ;# LMX_RF_ADC_SDO
+set_property  -dict  {PACKAGE_PIN H13   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_sck        ] ;# LMX_RF_ADC_SCK
+set_property  -dict  {PACKAGE_PIN K14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_cs         ] ;# LMX_RF_ADC_CS
+set_property  -dict  {PACKAGE_PIN J13   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_mosi       ] ;# LMX_RF_ADC_SDI
+set_property  -dict  {PACKAGE_PIN H14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_miso       ] ;# LMX_RF_ADC_SDO
 
-set_property  -dict  {PACKAGE_PIN H13   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_sck        ] ;# LMX_RF_DAC_SCK
-set_property  -dict  {PACKAGE_PIN J14   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_cs         ] ;# LMX_RF_DAC_CS
-set_property  -dict  {PACKAGE_PIN K15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_mosi       ] ;# LMX_RF_DAC_SDI
-set_property  -dict  {PACKAGE_PIN J13   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_miso       ] ;# LMX_RF_DAC_SDO
+set_property  -dict  {PACKAGE_PIN K15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_sck        ] ;# LMX_RF_DAC_CLK
+set_property  -dict  {PACKAGE_PIN G13   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_cs         ] ;# LMX_RF_DAC_CS
+set_property  -dict  {PACKAGE_PIN J14   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_mosi       ] ;# LMX_RF_DAC_SDI
+set_property  -dict  {PACKAGE_PIN H15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_miso       ] ;# LMX_RF_DAC_SDO
 
 # Route HDGC clock through BUFG to adjacent CMT
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]

projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci

@@ -128,13 +128,13 @@
             "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci

@@ -12,7 +12,7 @@
         "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "NUM_OF_SDI": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -23,7 +23,7 @@
         "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "NUM_OF_SDI": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
         "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
@@ -66,14 +66,14 @@
         "sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
         "sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
         "sdi_data_valid": [ { "direction": "out" } ],
-        "sdi_data": [ { "direction": "out", "size_left": "23", "size_right": "0" } ],
+        "sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
         "sync_ready": [ { "direction": "in" } ],
         "sync_valid": [ { "direction": "out" } ],
         "sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
         "sclk": [ { "direction": "out" } ],
         "sdo": [ { "direction": "out" } ],
         "sdo_t": [ { "direction": "out" } ],
-        "sdi": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
+        "sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
         "cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
         "three_wire": [ { "direction": "out" } ]
       },

projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/bd/system_bd/system_bd.bd

@@ -1,7 +1,7 @@
 {
   "design": {
     "design_info": {
-      "boundary_crc": "0xF2A321F5CFA5E97D",
+      "boundary_crc": "0x15EB8843C4739D6C",
       "device": "xczu47dr-ffve1156-2-i",
       "gen_directory": "../../../../dj_47dr_demo.gen/sources_1/bd/system_bd",
       "name": "system_bd",
@@ -50,7 +50,7 @@
           "sdi": {
             "physical_name": "spi_sdi",
             "direction": "I",
-            "left": "2",
+            "left": "0",
             "right": "0"
           },
           "sdo": {
@@ -3173,7 +3173,7 @@
                 "value": "3"
               },
               "NUM_OF_SDI": {
-                "value": "3"
+                "value": "1"
               }
             }
           }

projects/dj_47dr/dj_47dr_demo/dj_47dr_demo.srcs/sources_1/new/system_top.v

@@ -113,7 +113,7 @@ wire sys_rstn;
 // spi interface
 wire spi_sclk      ;
 wire [2:0] spi_cs  ;
-wire [2:0] spi_sdi ;
+reg spi_sdi        ;
 wire spi_sdo       ;
 wire spi_sdo_t     ;
 wire spi_three_wire;
@@ -121,19 +121,25 @@ wire spi_active    ;
 
 assign lmk_spi_sck = spi_sclk;
 assign lmk_spi_cs = spi_cs[0];
-assign spi_sdi[0] = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
 assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
 
 assign lmx_adc_spi_sck = spi_sclk;
 assign lmx_adc_spi_cs = spi_cs[1];
-assign spi_sdi[1] = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
 assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
 
 assign lmx_dac_spi_sck = spi_sclk;
 assign lmx_dac_spi_cs = spi_cs[2];
-assign spi_sdi[2] = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
 assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
 
+always @(*) begin
+    case (spi_cs)
+        3'b110:  spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
+        3'b101:  spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
+        3'b011:  spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
+        default: spi_sdi = 1'bz;
+    endcase
+end
+
 // -----------------------------------------------------------------------------
 // ADC Tile & Channel Mapping (Dual RF-ADC)
 // -----------------------------------------------------------------------------

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/_ide/hwspec.checksum

@@ -1 +1 @@
-1826953298
+168373126

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/dj_47dr_basic.prj

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="ASCII"?>
 <sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_basic" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_basic_system" sysConfig="dj_47dr_platform" runtime="cpp" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0">
-  <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.2086016496">
+  <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.2086016496" dirty="true">
     <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
     <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
   </configuration>

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/src/dev_profile/lmk04828_profile.c

@@ -17,8 +17,9 @@ struct lmk04828_init_param lmk04828_default_init_param = {
 	.spi_init = &lmk04828_spi_init
 };
 
-const uint32_t lmk04828_default_config_len = 136;
+const uint32_t lmk04828_default_config_len = 137;
 const struct lmk04828_config lmk04828_default_config[] = {
+	{0x0000, 0x90}, // [7] reset; [4] 3-wire mode disabled
 	{0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled
 	{0x0002, 0x00}, // [0] normal operation
 	{0x0003, 0x06}, // [7-0] product device type, read only, default: 6

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic_system/_ide/scripts/debugger_dj_47dr_basic-default.tcl

@@ -24,11 +24,12 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
 targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
 rst -processor
 dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
-set bp_54_45_fsbl_bp [bpadd -addr &XFsbl_Exit]
+set bp_20_42_fsbl_bp [bpadd -addr &XFsbl_Exit]
 con -block -timeout 60
-bpremove $bp_54_45_fsbl_bp
+bpremove $bp_20_42_fsbl_bp
 targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
 rst -processor
 dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_basic/Debug/dj_47dr_basic.elf
 configparams force-mem-access 0
-bpadd -addr &main
+targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
+con

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/_ide/hwspec.checksum

@@ -1 +1 @@
-1826953298
+168373126

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/src/dev_profile/lmk04828_profile.c

@@ -17,8 +17,9 @@ struct lmk04828_init_param lmk04828_default_init_param = {
 	.spi_init = &lmk04828_spi_init
 };
 
-const uint32_t lmk04828_default_config_len = 136;
+const uint32_t lmk04828_default_config_len = 137;
 const struct lmk04828_config lmk04828_default_config[] = {
+	{0x0000, 0x90}, // [7] reset; [4] 3-wire mode disabled
 	{0x0000, 0x10}, // [7] normal operation; [4] 3-wire mode disabled
 	{0x0002, 0x00}, // [0] normal operation
 	{0x0003, 0x06}, // [7-0] product device type, read only, default: 6

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts_system/_ide/scripts/debugger_dj_47dr_mts-default.tcl

@@ -24,11 +24,12 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
 targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
 rst -processor
 dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
-set bp_0_12_fsbl_bp [bpadd -addr &XFsbl_Exit]
+set bp_22_58_fsbl_bp [bpadd -addr &XFsbl_Exit]
 con -block -timeout 60
-bpremove $bp_0_12_fsbl_bp
+bpremove $bp_22_58_fsbl_bp
 targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
 rst -processor
 dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_mts/Debug/dj_47dr_mts.elf
 configparams force-mem-access 0
-bpadd -addr &main
+targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
+con

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/platform.spr

@@ -1 +1 @@
-{"platformName":"dj_47dr_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"dj_47dr_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynqMP","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","platFsblTarget":"psu_cortexa53_0","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP      -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects  ","pmufwExtraCompilerFlags":"-MMD -MP      -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -Os -flto -ffat-lto-objects  ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"dj_47dr_platform","systems":[{"systemName":"dj_47dr_platform","systemDesc":"dj_47dr_platform","sysIsBootAutoGen":"true","systemDispName":"dj_47dr_platform","sysActiveDom":"standalone_psu_cortexa53_0","sysDefaultDom":"standalone_psu_cortexa53_0","domains":[{"domainName":"zynqmp_fsbl","domainDispName":"zynqmp_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"34f9144051f817f481e1243bae5bfc58","compatibleApp":"zynqmp_fsbl","domType":"bootDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilsecure:5.3","xilpm:5.2"],"libOptions":{"standalone":{"zynqmp_fsbl_bsp":"true","libOptionNames":["zynqmp_fsbl_bsp"]},"xilffs":{"read_only":"true","use_mkfs":"false","libOptionNames":["read_only","use_mkfs"]},"xilsecure":{"tpm_support":"true","libOptionNames":["tpm_support"]},"libsContainingOptions":["standalone","xilffs","xilsecure"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"zynqmp_pmufw","domainDispName":"zynqmp_pmufw","domainDesc":"PMUFW Application BSP - Auto Generated.","processors":"psu_pmu_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"021024173153c25a215a10b82acc64cf","compatibleApp":"zynqmp_pmufw","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilfpga:6.6","xilsecure:5.3","xilskey:7.6"],"libOptions":{"psu_pmu_0":{"extra_compiler_flags":"-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns  -Os -flto -ffat-lto-objects","libOptionNames":["extra_compiler_flags"]},"libsContainingOptions":["psu_pmu_0"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_psu_cortexa53_0","domainDispName":"standalone_psu_cortexa53_0","domainDesc":"standalone_psu_cortexa53_0","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu_args.txt","qemuData":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu","pmuQemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/pmu_args.txt","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"8c89b0a93ea1628441ce7dd0fae33ed2","compatibleApp":"","domType":"mssDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilpm:5.2","xilsecure:5.3","lwip220:1.0"],"libOptions":{"lwip220":{"lwip_dhcp":"true","mem_size":"524288","memp_n_pbuf":"2048","memp_n_tcp_pcb":"1024","memp_n_tcp_seg":"1024","pbuf_pool_size":"4096","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","libOptionNames":["lwip_dhcp","mem_size","memp_n_pbuf","memp_n_tcp_pcb","memp_n_tcp_seg","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd"]},"psu_cortexa53_0":{"extra_compiler_flags":"-g -Wall -Wextra -Os","libOptionNames":["extra_compiler_flags"]},"standalone":{"stdin":"psu_coresight_0","stdout":"psu_coresight_0","libOptionNames":["stdin","stdout"]},"libsContainingOptions":["lwip220","psu_cortexa53_0","standalone"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
+{"platformName":"dj_47dr_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"dj_47dr_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynqMP","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","platFsblTarget":"psu_cortexa53_0","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP      -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects  ","pmufwExtraCompilerFlags":"-MMD -MP      -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v9.2 -mxl-soft-mul -Os -flto -ffat-lto-objects  ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"dj_47dr_platform","systems":[{"systemName":"dj_47dr_platform","systemDesc":"dj_47dr_platform","sysIsBootAutoGen":"true","systemDispName":"dj_47dr_platform","sysActiveDom":"standalone_psu_cortexa53_0","sysDefaultDom":"standalone_psu_cortexa53_0","domains":[{"domainName":"zynqmp_fsbl","domainDispName":"zynqmp_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"34f9144051f817f481e1243bae5bfc581","compatibleApp":"zynqmp_fsbl","domType":"bootDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilsecure:5.3","xilpm:5.2"],"libOptions":{"standalone":{"zynqmp_fsbl_bsp":"true","libOptionNames":["zynqmp_fsbl_bsp"]},"xilffs":{"read_only":"true","use_mkfs":"false","libOptionNames":["read_only","use_mkfs"]},"xilsecure":{"tpm_support":"true","libOptionNames":["tpm_support"]},"libsContainingOptions":["standalone","xilffs","xilsecure"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"zynqmp_pmufw","domainDispName":"zynqmp_pmufw","domainDesc":"PMUFW Application BSP - Auto Generated.","processors":"psu_pmu_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"021024173153c25a215a10b82acc64cf1","compatibleApp":"zynqmp_pmufw","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilfpga:6.6","xilsecure:5.3","xilskey:7.6"],"libOptions":{"psu_pmu_0":{"extra_compiler_flags":"-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns  -Os -flto -ffat-lto-objects","libOptionNames":["extra_compiler_flags"]},"libsContainingOptions":["psu_pmu_0"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_psu_cortexa53_0","domainDispName":"standalone_psu_cortexa53_0","domainDesc":"standalone_psu_cortexa53_0","processors":"psu_cortexa53_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu_args.txt","qemuData":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/qemu","pmuQemuArgs":"<platformDir>/resources/dj_47dr_platform/standalone_psu_cortexa53_0/pmu_args.txt","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.1","mssFile":"","md5Digest":"8c89b0a93ea1628441ce7dd0fae33ed2","compatibleApp":"","domType":"mssDomain","arch":"64-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.2","xilpm:5.2","xilsecure:5.3","lwip220:1.0"],"libOptions":{"lwip220":{"lwip_dhcp":"true","mem_size":"524288","memp_n_pbuf":"2048","memp_n_tcp_pcb":"1024","memp_n_tcp_seg":"1024","pbuf_pool_size":"4096","tcp_ip_rx_checksum_offload":"true","tcp_ip_tx_checksum_offload":"true","tcp_snd_buf":"65535","tcp_wnd":"65535","libOptionNames":["lwip_dhcp","mem_size","memp_n_pbuf","memp_n_tcp_pcb","memp_n_tcp_seg","pbuf_pool_size","tcp_ip_rx_checksum_offload","tcp_ip_tx_checksum_offload","tcp_snd_buf","tcp_wnd"]},"psu_cortexa53_0":{"extra_compiler_flags":"-g -Wall -Wextra -Os","libOptionNames":["extra_compiler_flags"]},"standalone":{"stdin":"psu_coresight_0","stdout":"psu_coresight_0","libOptionNames":["stdin","stdout"]},"libsContainingOptions":["lwip220","psu_cortexa53_0","standalone"]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/platform.tcl

@@ -84,3 +84,8 @@ bsp write
 bsp reload
 catch {bsp regenerate}
 platform generate -domains standalone_psu_cortexa53_0 
+platform active {dj_47dr_platform}
+platform generate
+platform active {dj_47dr_platform}
+platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/system_top.xsa}
+platform generate -domains 

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/psu_cortexa53_0/standalone_psu_cortexa53_0/bsp/system_1.mss

@@ -0,0 +1,636 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 9.1
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+ PARAMETER stdin = psu_coresight_0
+ PARAMETER stdout = psu_coresight_0
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa53
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = psu_cortexa53_0
+ PARAMETER extra_compiler_flags = -g -Wall -Wextra -Os
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 5.3
+ PARAMETER HW_INSTANCE = psu_acpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_adma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_afi_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sysmonpsu
+ PARAMETER DRIVER_VER = 2.10
+ PARAMETER HW_INSTANCE = psu_ams
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.11
+ PARAMETER HW_INSTANCE = psu_apm_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.11
+ PARAMETER HW_INSTANCE = psu_apm_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.11
+ PARAMETER HW_INSTANCE = psu_apm_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.11
+ PARAMETER HW_INSTANCE = psu_apm_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_apu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_cci_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_cci_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.10
+ PARAMETER HW_INSTANCE = psu_coresight_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = resetps
+ PARAMETER DRIVER_VER = 1.7
+ PARAMETER HW_INSTANCE = psu_crf_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_crl_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_csu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = csudma
+ PARAMETER DRIVER_VER = 1.15
+ PARAMETER HW_INSTANCE = psu_csudma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ctrl_ipi
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.6
+ PARAMETER HW_INSTANCE = psu_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.6
+ PARAMETER HW_INSTANCE = psu_ddr_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_phy
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_qos_ctrl
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu0_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu1_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu2_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu3_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu4_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu5_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.6
+ PARAMETER HW_INSTANCE = psu_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_efuse
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.20
+ PARAMETER HW_INSTANCE = psu_ethernet_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_fpd_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_fpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_fpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.18
+ PARAMETER HW_INSTANCE = psu_gdma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.13
+ PARAMETER HW_INSTANCE = psu_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_i2c_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_iou_scntr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_iou_scntrs
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_iousecure_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_iouslcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ipipsu
+ PARAMETER DRIVER_VER = 2.15
+ PARAMETER HW_INSTANCE = psu_ipi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_lpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_lpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_lpd_xppu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_lpd_xppu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_mbistjtag
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_message_buffers
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ocm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ocm_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspipsu
+ PARAMETER DRIVER_VER = 1.19
+ PARAMETER HW_INSTANCE = psu_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_r5_1_atcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_r5_1_btcm_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_r5_tcm_ram_global
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 5.3
+ PARAMETER HW_INSTANCE = psu_rcpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_rpu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_rsa
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = rtcpsu
+ PARAMETER DRIVER_VER = 1.14
+ PARAMETER HW_INSTANCE = psu_rtc
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_serdes
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_siou
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_smmu_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_smmu_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.14
+ PARAMETER HW_INSTANCE = psu_uart_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = rfdc
+ PARAMETER DRIVER_VER = 12.2
+ PARAMETER HW_INSTANCE = usp_rf_data_converter
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_ttc_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_ttc_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.19
+ PARAMETER HW_INSTANCE = psu_ttc_3
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = xilffs
+ PARAMETER LIBRARY_VER = 5.2
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = xilpm
+ PARAMETER LIBRARY_VER = 5.2
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = xilsecure
+ PARAMETER LIBRARY_VER = 5.3
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+END
+
+
+BEGIN LIBRARY
+ PARAMETER LIBRARY_NAME = lwip220
+ PARAMETER LIBRARY_VER = 1.0
+ PARAMETER PROC_INSTANCE = psu_cortexa53_0
+ PARAMETER lwip_dhcp = true
+ PARAMETER mem_size = 524288
+ PARAMETER memp_n_pbuf = 2048
+ PARAMETER memp_n_tcp_pcb = 1024
+ PARAMETER memp_n_tcp_seg = 1024
+ PARAMETER pbuf_pool_size = 4096
+ PARAMETER tcp_ip_rx_checksum_offload = true
+ PARAMETER tcp_ip_tx_checksum_offload = true
+ PARAMETER tcp_snd_buf = 65535
+ PARAMETER tcp_wnd = 65535
+END
+
+

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_tcp_perf_server/_ide/hwspec.checksum

@@ -1 +1 @@
-1826953298
+168373126

projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_tcp_perf_server/dj_47dr_tcp_perf_server.prj

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="ASCII"?>
 <sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_tcp_perf_server" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_tcp_perf_server" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_demo/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_tcp_perf_server_system" sysConfig="dj_47dr_platform" runtime="C/C++" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="e5137af98a8637d675be0f97061d31f0">
-  <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.459719114" dirty="true">
+  <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.459719114">
     <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
     <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
   </configuration>

projects/dj_47dr/dj_47dr_demo/vitis_classic/fsbl_debug/_ide/hwspec.checksum

@@ -1 +1 @@
-1826953298
+168373126

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/constrs_1/new/dj_47dr.xdc

@@ -0,0 +1,20 @@
+set_property  -dict  {PACKAGE_PIN F14   IOSTANDARD LVPECL  }  [get_ports pl_refclk_p            ] ;# PL_CLK_P
+set_property  -dict  {PACKAGE_PIN F10   IOSTANDARD LVPECL  }  [get_ports pl_sysref_p            ] ;# PL_SYSREF_P
+
+set_property  -dict  {PACKAGE_PIN B13   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_sck            ] ;# LMK_SPI_SCK
+set_property  -dict  {PACKAGE_PIN A13   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_cs             ] ;# LMK_SPI_CS
+set_property  -dict  {PACKAGE_PIN C14   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_mosi           ] ;# LMK_SPI_SDI
+set_property  -dict  {PACKAGE_PIN A14   IOSTANDARD LVCMOS33}  [get_ports lmk_spi_miso           ] ;# LMK_SPI_SDO
+
+set_property  -dict  {PACKAGE_PIN H13   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_sck        ] ;# LMX_RF_ADC_SCK
+set_property  -dict  {PACKAGE_PIN K14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_cs         ] ;# LMX_RF_ADC_CS
+set_property  -dict  {PACKAGE_PIN J13   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_mosi       ] ;# LMX_RF_ADC_SDI
+set_property  -dict  {PACKAGE_PIN H14   IOSTANDARD LVCMOS33}  [get_ports lmx_adc_spi_miso       ] ;# LMX_RF_ADC_SDO
+
+set_property  -dict  {PACKAGE_PIN K15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_sck        ] ;# LMX_RF_DAC_CLK
+set_property  -dict  {PACKAGE_PIN G13   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_cs         ] ;# LMX_RF_DAC_CS
+set_property  -dict  {PACKAGE_PIN J14   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_mosi       ] ;# LMX_RF_DAC_SDI
+set_property  -dict  {PACKAGE_PIN H15   IOSTANDARD LVCMOS33}  [get_ports lmx_dac_spi_miso       ] ;# LMX_RF_DAC_SDO
+
+# Route HDGC clock through BUFG to adjacent CMT
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_system_bd_wrapper/system_bd_i/mts_clk_gen/util_ds_buf_pl_clk/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O]

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci

@@ -0,0 +1,304 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_auto_pc_0",
+    "cell_name": "ps8_0_axi_periph/s00_couplers/auto_pc",
+    "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
+    "ip_revision": "31",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
+    "parameters": {
+      "component_parameters": {
+        "SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
+        "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ADDR_WIDTH": [ { "value": "40", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ADDR_WIDTH": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "31" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "rtl" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "aresetn": [ { "direction": "in" } ],
+        "s_axi_awid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_awlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
+        "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arid": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0x0000" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "39", "size_right": "0", "driver_value": "0x0000000000" } ],
+        "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ],
+        "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
+        "s_axi_arlock": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arregion": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rid": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rlast": [ { "direction": "out" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_awaddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_awvalid": [ { "direction": "out" } ],
+        "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "m_axi_wvalid": [ { "direction": "out" } ],
+        "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_bready": [ { "direction": "out" } ],
+        "m_axi_araddr": [ { "direction": "out", "size_left": "39", "size_right": "0" } ],
+        "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "m_axi_arvalid": [ { "direction": "out" } ],
+        "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
+        "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
+        "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "m_axi_rready": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "16", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWID": [ { "physical_name": "s_axi_awid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWLEN": [ { "physical_name": "s_axi_awlen" } ],
+            "AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
+            "AWBURST": [ { "physical_name": "s_axi_awburst" } ],
+            "AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
+            "AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWREGION": [ { "physical_name": "s_axi_awregion" } ],
+            "AWQOS": [ { "physical_name": "s_axi_awqos" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WLAST": [ { "physical_name": "s_axi_wlast" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BID": [ { "physical_name": "s_axi_bid" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARID": [ { "physical_name": "s_axi_arid" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARLEN": [ { "physical_name": "s_axi_arlen" } ],
+            "ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
+            "ARBURST": [ { "physical_name": "s_axi_arburst" } ],
+            "ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
+            "ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARREGION": [ { "physical_name": "s_axi_arregion" } ],
+            "ARQOS": [ { "physical_name": "s_axi_arqos" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RID": [ { "physical_name": "s_axi_rid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RLAST": [ { "physical_name": "s_axi_rlast" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "M_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "40", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "m_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "m_axi_awready" } ],
+            "WDATA": [ { "physical_name": "m_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "m_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "m_axi_wready" } ],
+            "BRESP": [ { "physical_name": "m_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "m_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "m_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "m_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "m_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "m_axi_arready" } ],
+            "RDATA": [ { "physical_name": "m_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "m_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "m_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "m_axi_rready" } ]
+          }
+        },
+        "CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci

@@ -0,0 +1,294 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_axi_spi_engine_0_0",
+    "cell_name": "axi_spi_engine/axi_spi_engine",
+    "component_reference": "analog.com:user:axi_spi_engine:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
+    "parameters": {
+      "component_parameters": {
+        "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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+        "BOARD_CONNECTIONS": [ { "value": "" } ],
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+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "spi_engine_ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "cmd_ready": [ { "physical_name": "cmd_ready" } ],
+            "cmd_valid": [ { "physical_name": "cmd_valid" } ],
+            "cmd_data": [ { "physical_name": "cmd_data" } ],
+            "sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
+            "sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
+            "sdo_data": [ { "physical_name": "sdo_data" } ],
+            "sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
+            "sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
+            "sdi_data": [ { "physical_name": "sdi_data" } ],
+            "sync_ready": [ { "physical_name": "sync_ready" } ],
+            "sync_valid": [ { "physical_name": "sync_valid" } ],
+            "sync_data": [ { "physical_name": "sync_data" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
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+            "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
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+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "spi_clk" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "spi_resetn" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "axi_lite": {
+              "base_address": "0",
+              "range": "65536"
+            }
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci

@@ -0,0 +1,658 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_clk_wiz_0_0",
+    "cell_name": "mts_clk_gen/clk_wiz_pl_clk",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "14",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "245.76", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "40.69", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "Buffer", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "85.228", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "77.902", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "system_bd_clk_wiz_0_0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "LATENCY", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary__________245.76____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__245.76000______0.000______50.0_______85.228_____77.902", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "245.76", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "245.76000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "4.069", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "4.875", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "40.69", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
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+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_ps8_0_axi_periph_0/system_bd_ps8_0_axi_periph_0.xci

@@ -0,0 +1,353 @@
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+        "S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_ps8_0_axi_periph_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_ps8_0_axi_periph_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0/system_bd_rst_ps8_0_96M_0.xci

@@ -0,0 +1,196 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_rst_ps8_0_96M_0",
+    "cell_name": "rst_ps8_0_96M",
+    "component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
+    "ip_revision": "15",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0",
+    "parameters": {
+      "component_parameters": {
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_rst_ps8_0_96M_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "15" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps8_0_96M_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "slowest_sync_clk": [ { "direction": "in" } ],
+        "ext_reset_in": [ { "direction": "in" } ],
+        "aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
+        "mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
+        "dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
+        "mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
+        "bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
+      },
+      "interfaces": {
+        "clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "slowest_sync_clk" } ]
+          }
+        },
+        "ext_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "ext_reset_in" } ]
+          }
+        },
+        "aux_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aux_reset_in" } ]
+          }
+        },
+        "dbg_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_debug_sys_rst" } ]
+          }
+        },
+        "mb_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_reset" } ]
+          }
+        },
+        "bus_struct_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "bus_struct_reset" } ]
+          }
+        },
+        "interconnect_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "interconnect_aresetn" } ]
+          }
+        },
+        "peripheral_high_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_reset" } ]
+          }
+        },
+        "peripheral_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci

@@ -0,0 +1,176 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_spi_engine_execution_0_0",
+    "cell_name": "axi_spi_engine/spi_engine_execution",
+    "component_reference": "analog.com:user:spi_engine_execution:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "1" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk": [ { "direction": "in" } ],
+        "resetn": [ { "direction": "in" } ],
+        "active": [ { "direction": "out" } ],
+        "cmd_ready": [ { "direction": "out" } ],
+        "cmd_valid": [ { "direction": "in" } ],
+        "cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
+        "sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
+        "sdo_data_ready": [ { "direction": "out" } ],
+        "sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
+        "sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
+        "sdi_data_valid": [ { "direction": "out" } ],
+        "sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sync_ready": [ { "direction": "in" } ],
+        "sync_valid": [ { "direction": "out" } ],
+        "sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sclk": [ { "direction": "out" } ],
+        "sdo": [ { "direction": "out" } ],
+        "sdo_t": [ { "direction": "out" } ],
+        "sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
+        "cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "three_wire": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "cmd_ready": [ { "physical_name": "cmd_ready" } ],
+            "cmd_valid": [ { "physical_name": "cmd_valid" } ],
+            "cmd_data": [ { "physical_name": "cmd" } ],
+            "sdo_ready": [ { "physical_name": "sdo_data_ready" } ],
+            "sdo_valid": [ { "physical_name": "sdo_data_valid" } ],
+            "sdo_data": [ { "physical_name": "sdo_data" } ],
+            "sdi_ready": [ { "physical_name": "sdi_data_ready" } ],
+            "sdi_valid": [ { "physical_name": "sdi_data_valid" } ],
+            "sdi_data": [ { "physical_name": "sdi_data" } ],
+            "sync_ready": [ { "physical_name": "sync_ready" } ],
+            "sync_valid": [ { "physical_name": "sync_valid" } ],
+            "sync_data": [ { "physical_name": "sync" } ]
+          }
+        },
+        "ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        },
+        "spi": {
+          "vlnv": "analog.com:interface:spi_engine:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "sclk": [ { "physical_name": "sclk" } ],
+            "sdi": [ { "physical_name": "sdi" } ],
+            "sdo": [ { "physical_name": "sdo" } ],
+            "sdo_t": [ { "physical_name": "sdo_t" } ],
+            "three_wire": [ { "physical_name": "three_wire" } ],
+            "cs": [ { "physical_name": "cs" } ]
+          }
+        },
+        "spi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_zynq_ultra_ps_e_0_1_pl_clk0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "spi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0/system_bd_util_ds_buf_0_0.xci

@@ -0,0 +1,99 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_ds_buf_0_0",
+    "cell_name": "mts_clk_gen/util_ds_buf_pl_clk",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_ds_buf_0_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK_IN_D": {
+          "vlnv": "xilinx.com:interface:diff_clock:1.0",
+          "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
+            "CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
+          }
+        },
+        "IBUF_OUT": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "IBUF_OUT" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1/system_bd_util_ds_buf_0_1.xci

@@ -0,0 +1,102 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_ds_buf_0_1",
+    "cell_name": "mts_clk_gen/util_bufg_pl_clk",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_ds_buf_0_1", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_0_1" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "BUFG_I": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "BUFG_O": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
+      },
+      "interfaces": {
+        "BUFG_I": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "BUFG_I" } ]
+          }
+        },
+        "BUFG_O": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_0_0_IBUF_OUT", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "BUFG_O" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0/system_bd_util_ds_buf_1_0.xci

@@ -0,0 +1,99 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_util_ds_buf_1_0",
+    "cell_name": "mts_clk_gen/util_ds_buf_pl_sysref",
+    "component_reference": "xilinx.com:ip:util_ds_buf:2.2",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_util_ds_buf_1_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BOARD_PARAMETER": [ { "value": " ", "resolve_type": "user", "usage": "all" } ],
+        "FREQ_HZ": [ { "value": "156250000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DIFF_CLK_IN_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_BUF_TYPE": [ { "value": "IBUFDS", "resolve_type": "generated", "usage": "all" } ],
+        "C_SIZE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFGCE_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BUFG_GT_SYNC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SIM_DEVICE": [ { "value": "VERSAL_AI_CORE_ES1", "resolve_type": "generated", "usage": "all" } ],
+        "C_OBUFDS_GTE5_ADV": [ { "value": "\"00\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_REFCLK_ICNTL_TX": [ { "value": "\"00000\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_util_ds_buf_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "IBUF_DS_P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_DS_N": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "IBUF_OUT": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK_IN_D": {
+          "vlnv": "xilinx.com:interface:diff_clock:1.0",
+          "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "DIFF_CLK_IN_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "CAN_DEBUG": [ { "value": "false", "value_permission": "bd", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_P": [ { "physical_name": "IBUF_DS_P" } ],
+            "CLK_N": [ { "physical_name": "IBUF_DS_N" } ]
+          }
+        },
+        "IBUF_OUT": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_util_ds_buf_1_0_IBUF_OUT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "IBUF_OUT" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci

@@ -0,0 +1,308 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xlconcat_0_0",
+    "cell_name": "xlconcat_0",
+    "component_reference": "xilinx.com:ip:xlconcat:2.1",
+    "ip_revision": "6",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
+        "NUM_PORTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN1_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci

@@ -0,0 +1,50 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xlconstant_0_0",
+    "cell_name": "mts_clk_gen/xlconstant_0",
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+    "parameters": {
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+        "CONST_VAL": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
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+        "CONST_VAL": [ { "value": "0x0", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
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+        "STATIC_POWER": [ { "value": "" } ],
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+      },
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+        "IPREVISION": [ { "value": "9" } ],
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+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
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+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0/system_bd_xpm_cdc_gen_0_0.xci

@@ -0,0 +1,126 @@
+{
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+  "ip_inst": {
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+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0",
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+        "DEST_EXT_HSK": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REG_OUTPUT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RST_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_xpm_cdc_gen_0_0", "resolve_type": "user", "usage": "all" } ]
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+        "RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
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+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
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+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
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+    },
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+        "src_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
+        "dest_out": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
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+          }
+        },
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+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "src_clk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci

@@ -0,0 +1,126 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_xpm_cdc_gen_pl_sysref_0",
+    "cell_name": "mts_clk_gen/xpm_cdc_gen_mts_sysref",
+    "component_reference": "xilinx.com:ip:xpm_cdc_gen:1.0",
+    "ip_revision": "4",
+    "gen_directory": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0",
+    "parameters": {
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+        "CDC_TYPE": [ { "value": "xpm_cdc_single", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "SRC_CLK_PERIOD": [ { "value": "5000", "resolve_type": "user", "usage": "all" } ],
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+        "INIT_SYNC_FF": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SRC_INPUT_REG": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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+        "INIT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SRC_SYNC_FF": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "RST_ACTIVE_HIGH": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_xpm_cdc_gen_pl_sysref_0", "resolve_type": "user", "usage": "all" } ]
+      },
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+        "RST_ACTIVE_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
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+        "BASE_BOARD_PART": [ { "value": "" } ],
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+        "DEVICE": [ { "value": "xczu47dr" } ],
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+        "PACKAGE": [ { "value": "ffve1156" } ],
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+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "4" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd/ip/system_bd_xpm_cdc_gen_pl_sysref_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "245760000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_clk_wiz_0_0_clk_out1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "dest_clk" } ]
+          }
+        },
+        "src_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "200000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "src_clk" } ]
+          }
+        },
+        "RST": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bda

@@ -0,0 +1,249 @@
+{
+    "graphjs": {
+        "version": "1.0",
+        "keys": [
+            {
+                "abrv": "VH",
+                "name": "vert_hid",
+                "type": "int",
+                "for": "node"
+            },
+            {
+                "abrv": "VM",
+                "name": "vert_name",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "VT",
+                "name": "vert_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BA",
+                "name": "base_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HA",
+                "name": "high_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BP",
+                "name": "base_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HP",
+                "name": "high_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MA",
+                "name": "master_addrspace",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MX",
+                "name": "master_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MI",
+                "name": "master_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MS",
+                "name": "master_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MV",
+                "name": "master_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SX",
+                "name": "slave_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SI",
+                "name": "slave_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MM",
+                "name": "slave_memmap",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SS",
+                "name": "slave_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SV",
+                "name": "slave_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TM",
+                "name": "memory_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TU",
+                "name": "usage_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "LT",
+                "name": "lock_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BT",
+                "name": "boot_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "EH",
+                "name": "edge_hid",
+                "type": "int",
+                "for": "edge"
+            }
+        ],
+        "vertice_type_order": [
+            {
+                "abrv": "BC",
+                "desc": "Block Container"
+            },
+            {
+                "abrv": "PR",
+                "desc": "Parital Reference"
+            },
+            {
+                "abrv": "VR",
+                "desc": "Variant"
+            },
+            {
+                "abrv": "PM",
+                "desc": "Variant Permutations"
+            },
+            {
+                "abrv": "CX",
+                "desc": "Boundary Connection"
+            },
+            {
+                "abrv": "AC",
+                "desc": "Assignment Coordinate"
+            },
+            {
+                "abrv": "ACE",
+                "desc": "Excluded Assign Coordinate"
+            },
+            {
+                "abrv": "APX",
+                "desc": "Boundary Aperture"
+            },
+            {
+                "abrv": "CIP",
+                "desc": "High level Processing System"
+            }
+        ],
+        "vertices": {
+            "V0": {
+                "VM": "system_bd",
+                "VT": "BC"
+            },
+            "V1": {
+                "VH": "2",
+                "VM": "system_bd",
+                "VT": "VR"
+            },
+            "V2": {
+                "VH": "2",
+                "VT": "PM",
+                "TU": "active"
+            },
+            "V3": {
+                "VT": "AC",
+                "BA": "0x0080000000",
+                "HA": "0x008000FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/zynq_ultra_ps_e",
+                "MI": "M_AXI_HPM0_LPD",
+                "MS": "SEG_axi_spi_engine_axi_lite",
+                "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
+                "SX": "/axi_spi_engine/axi_spi_engine",
+                "SI": "s_axi",
+                "SS": "axi_lite",
+                "SV": "analog.com:user:axi_spi_engine:1.0",
+                "TM": "both",
+                "TU": "register"
+            },
+            "V4": {
+                "VT": "AC",
+                "BA": "0x0080040000",
+                "HA": "0x008007FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/zynq_ultra_ps_e",
+                "MI": "M_AXI_HPM0_LPD",
+                "MS": "SEG_usp_rf_data_converter_Reg",
+                "MV": "xilinx.com:ip:zynq_ultra_ps_e:3.5",
+                "SX": "/usp_rf_data_converter",
+                "SI": "s_axi",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:usp_rf_data_converter:2.6",
+                "TM": "both",
+                "TU": "register"
+            }
+        },
+        "edges": [
+            {
+                "src": "V0",
+                "trg": "V1"
+            },
+            {
+                "src": "V1",
+                "trg": "V2"
+            },
+            {
+                "src": "V3",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V4",
+                "trg": "V2",
+                "EH": "2"
+            }
+        ]
+    }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_2942602e.ui

@@ -0,0 +1,34 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-360,-198",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
+preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
+preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
+preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
+preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
+preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
+preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
+preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
+preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
+preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
+preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
+preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
+preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
+preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
+preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
+preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
+preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
+preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
+preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
+preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
+preplace netloc Conn1 1 0 1 NJ 70
+preplace netloc Conn2 1 0 2 NJ 240 NJ
+levelinfo -pg 1 0 150 410 670 910 1060
+pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
+"
+}
+

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_af01e55c.ui

@@ -0,0 +1,34 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-360,-198",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
+preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 240 -defaultsOSRD
+preplace port port-id_sys_rstn -pg 1 -lvl 5 -x 1060 -y 80 -defaultsOSRD
+preplace port port-id_sys_clk -pg 1 -lvl 5 -x 1060 -y 60 -defaultsOSRD
+preplace portBus mts_sysref -pg 1 -lvl 5 -x 1060 -y 170 -defaultsOSRD
+preplace inst util_ds_buf_pl_clk -pg 1 -lvl 1 -x 150 -y 70 -defaultsOSRD
+preplace inst util_bufg_pl_clk -pg 1 -lvl 2 -x 410 -y 70 -defaultsOSRD -resize 220 88
+preplace inst util_ds_buf_pl_sysref -pg 1 -lvl 2 -x 410 -y 240 -defaultsOSRD -resize 220 88
+preplace inst clk_wiz_pl_clk -pg 1 -lvl 3 -x 670 -y 70 -defaultsOSRD
+preplace inst xpm_cdc_gen_pl_sysref -pg 1 -lvl 3 -x 670 -y 220 -defaultsOSRD
+preplace inst xpm_cdc_gen_mts_sysref -pg 1 -lvl 4 -x 910 -y 160 -defaultsOSRD -resize 200 116
+preplace inst xlconstant_0 -pg 1 -lvl 2 -x 410 -y 350 -defaultsOSRD
+preplace netloc util_ds_buf_pl_clk_IBUF_OUT 1 1 1 NJ 70
+preplace netloc util_bufg_pl_clk_BUFG_O 1 2 1 540 70n
+preplace netloc xlconstant_0_dout 1 2 2 550 140 NJ
+preplace netloc util_ds_buf_pl_sysref_IBUF_OUT 1 2 1 NJ 240
+preplace netloc xpm_cdc_gen_pl_sysref_dest_out 1 3 1 790 180n
+preplace netloc xpm_cdc_gen_mts_sysref_dest_out 1 4 1 1030J 160n
+preplace netloc clk_wiz_pl_clk_locked 1 3 2 NJ 80 N
+preplace netloc clk_wiz_pl_clk_clk_out1 1 3 2 790 60 NJ
+preplace netloc Conn1 1 0 1 NJ 70
+preplace netloc Conn2 1 0 2 NJ 240 NJ
+levelinfo -pg 1 0 150 410 670 910 1060
+pagesize -pg 1 -db -bbox -sgen -120 0 1230 410
+"
+}
+

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui

@@ -0,0 +1,179 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.537304",
+   "Default View_TopLeft":"-1158,4",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port spi -pg 1 -lvl 4 -x 1120 -y 330 -defaultsOSRD
+preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
+preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
+preplace port adc2_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD
+preplace port dac2_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
+preplace port m00_axis -pg 1 -lvl 4 -x 1120 -y 590 -defaultsOSRD
+preplace port m01_axis -pg 1 -lvl 4 -x 1120 -y 610 -defaultsOSRD
+preplace port m02_axis -pg 1 -lvl 4 -x 1120 -y 630 -defaultsOSRD
+preplace port m03_axis -pg 1 -lvl 4 -x 1120 -y 650 -defaultsOSRD
+preplace port m10_axis -pg 1 -lvl 4 -x 1120 -y 670 -defaultsOSRD
+preplace port m11_axis -pg 1 -lvl 4 -x 1120 -y 690 -defaultsOSRD
+preplace port m12_axis -pg 1 -lvl 4 -x 1120 -y 710 -defaultsOSRD
+preplace port m13_axis -pg 1 -lvl 4 -x 1120 -y 730 -defaultsOSRD
+preplace port m20_axis -pg 1 -lvl 4 -x 1120 -y 750 -defaultsOSRD
+preplace port m21_axis -pg 1 -lvl 4 -x 1120 -y 770 -defaultsOSRD
+preplace port m22_axis -pg 1 -lvl 4 -x 1120 -y 790 -defaultsOSRD
+preplace port m23_axis -pg 1 -lvl 4 -x 1120 -y 810 -defaultsOSRD
+preplace port m30_axis -pg 1 -lvl 4 -x 1120 -y 830 -defaultsOSRD
+preplace port m31_axis -pg 1 -lvl 4 -x 1120 -y 850 -defaultsOSRD
+preplace port m32_axis -pg 1 -lvl 4 -x 1120 -y 870 -defaultsOSRD
+preplace port m33_axis -pg 1 -lvl 4 -x 1120 -y 890 -defaultsOSRD
+preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD
+preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
+preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
+preplace port s12_axis -pg 1 -lvl 0 -x 0 -y 600 -defaultsOSRD
+preplace port s20_axis -pg 1 -lvl 0 -x 0 -y 620 -defaultsOSRD
+preplace port s22_axis -pg 1 -lvl 0 -x 0 -y 640 -defaultsOSRD
+preplace port s30_axis -pg 1 -lvl 0 -x 0 -y 660 -defaultsOSRD
+preplace port s32_axis -pg 1 -lvl 0 -x 0 -y 680 -defaultsOSRD
+preplace port sysref_in -pg 1 -lvl 0 -x 0 -y 900 -defaultsOSRD
+preplace port vin0_01 -pg 1 -lvl 0 -x 0 -y 740 -defaultsOSRD
+preplace port vin0_23 -pg 1 -lvl 0 -x 0 -y 760 -defaultsOSRD
+preplace port vin1_01 -pg 1 -lvl 0 -x 0 -y 780 -defaultsOSRD
+preplace port vin1_23 -pg 1 -lvl 0 -x 0 -y 800 -defaultsOSRD
+preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
+preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
+preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD
+preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
+preplace port vout00 -pg 1 -lvl 4 -x 1120 -y 910 -defaultsOSRD
+preplace port vout02 -pg 1 -lvl 4 -x 1120 -y 930 -defaultsOSRD
+preplace port vout10 -pg 1 -lvl 4 -x 1120 -y 950 -defaultsOSRD
+preplace port vout12 -pg 1 -lvl 4 -x 1120 -y 970 -defaultsOSRD
+preplace port vout20 -pg 1 -lvl 4 -x 1120 -y 990 -defaultsOSRD
+preplace port vout22 -pg 1 -lvl 4 -x 1120 -y 1010 -defaultsOSRD
+preplace port vout30 -pg 1 -lvl 4 -x 1120 -y 1030 -defaultsOSRD
+preplace port vout32 -pg 1 -lvl 4 -x 1120 -y 1050 -defaultsOSRD
+preplace port port-id_spi_active -pg 1 -lvl 4 -x 1120 -y 350 -defaultsOSRD
+preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1120 -y 1460 -defaultsOSRD
+preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1120 -y 1480 -defaultsOSRD
+preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1120 -y 540 -defaultsOSRD
+preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1120 -y 1070 -defaultsOSRD
+preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1120 -y 1090 -defaultsOSRD
+preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1120 -y 1110 -defaultsOSRD
+preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1120 -y 1130 -defaultsOSRD
+preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1120 -y 1150 -defaultsOSRD
+preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1120 -y 1170 -defaultsOSRD
+preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1120 -y 1190 -defaultsOSRD
+preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1120 -y 1210 -defaultsOSRD
+preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1020 -defaultsOSRD
+preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1000 -defaultsOSRD
+preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1060 -defaultsOSRD
+preplace port port-id_m1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1040 -defaultsOSRD
+preplace port port-id_m2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1100 -defaultsOSRD
+preplace port port-id_m2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1080 -defaultsOSRD
+preplace port port-id_m3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1140 -defaultsOSRD
+preplace port port-id_m3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1120 -defaultsOSRD
+preplace port port-id_s0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1180 -defaultsOSRD
+preplace port port-id_s0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1160 -defaultsOSRD
+preplace port port-id_s1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1220 -defaultsOSRD
+preplace port port-id_s1_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1200 -defaultsOSRD
+preplace port port-id_s2_axis_aclk -pg 1 -lvl 0 -x 0 -y 1260 -defaultsOSRD
+preplace port port-id_s2_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1240 -defaultsOSRD
+preplace port port-id_s3_axis_aclk -pg 1 -lvl 0 -x 0 -y 1300 -defaultsOSRD
+preplace port port-id_s3_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1280 -defaultsOSRD
+preplace inst usp_rf_data_converter -pg 1 -lvl 1 -x 360 -y 910 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 2 -x 880 -y 350 -defaultsOSRD
+preplace inst ps8_0_axi_periph -pg 1 -lvl 1 -x 360 -y 340 -defaultsOSRD
+preplace inst rst_ps8_0_96M -pg 1 -lvl 2 -x 880 -y 170 -defaultsOSRD
+preplace inst mts_clk_gen -pg 1 -lvl 1 -x 360 -y 1460 -defaultsOSRD
+preplace inst xlconcat_0 -pg 1 -lvl 2 -x 880 -y 470 -defaultsOSRD -orient R180
+preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 360 -y 110 -defaultsOSRD
+preplace netloc adi_spi_engine_active_0 1 2 2 N 350 N
+preplace netloc adi_spi_engine_irq 1 2 1 1060 370n
+preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1020
+preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1000
+preplace netloc m1_axis_aclk_0_1 1 0 1 NJ 1060
+preplace netloc m1_axis_aresetn_0_1 1 0 1 NJ 1040
+preplace netloc m2_axis_aclk_0_1 1 0 1 NJ 1100
+preplace netloc m2_axis_aresetn_0_1 1 0 1 NJ 1080
+preplace netloc m3_axis_aclk_0_1 1 0 1 NJ 1140
+preplace netloc m3_axis_aresetn_0_1 1 0 1 NJ 1120
+preplace netloc mts_sysref_gen_clk_out1_0 1 1 3 N 1460 NJ 1460 N
+preplace netloc mts_sysref_gen_locked_0 1 1 3 N 1480 NJ 1480 N
+preplace netloc mts_sysref_gen_mts_sysref 1 0 2 20 1380 670
+preplace netloc rst_ps8_0_96M_peripheral_aresetn 1 0 3 40 1360 700J 270 1060
+preplace netloc s0_axis_aclk_0_1 1 0 1 NJ 1180
+preplace netloc s0_axis_aresetn_0_1 1 0 1 NJ 1160
+preplace netloc s1_axis_aclk_0_1 1 0 1 NJ 1220
+preplace netloc s1_axis_aresetn_0_1 1 0 1 NJ 1200
+preplace netloc s2_axis_aclk_0_1 1 0 1 NJ 1260
+preplace netloc s2_axis_aresetn_0_1 1 0 1 NJ 1240
+preplace netloc s3_axis_aclk_0_1 1 0 1 NJ 1300
+preplace netloc s3_axis_aresetn_0_1 1 0 1 N 1280
+preplace netloc usp_rf_data_converter_clk_adc0 1 1 3 N 1070 NJ 1070 N
+preplace netloc usp_rf_data_converter_clk_adc1 1 1 3 N 1090 NJ 1090 N
+preplace netloc usp_rf_data_converter_clk_adc2 1 1 3 N 1110 NJ 1110 N
+preplace netloc usp_rf_data_converter_clk_adc3 1 1 3 N 1130 NJ 1130 N
+preplace netloc usp_rf_data_converter_clk_dac0 1 1 3 N 1150 NJ 1150 N
+preplace netloc usp_rf_data_converter_clk_dac1 1 1 3 N 1170 NJ 1170 N
+preplace netloc usp_rf_data_converter_clk_dac2 1 1 3 N 1190 NJ 1190 N
+preplace netloc usp_rf_data_converter_clk_dac3 1 1 3 N 1210 NJ 1210 N
+preplace netloc usp_rf_data_converter_irq 1 1 2 N 1230 1060
+preplace netloc xlconcat_0_dout 1 0 2 20 10 680J
+preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 540 NJ 540 N
+preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 670 110n
+preplace netloc adc2_clk_1 1 0 1 N 700
+preplace netloc adi_spi_engine_spi_0 1 2 2 N 330 N
+preplace netloc dac2_clk_1 1 0 1 N 720
+preplace netloc pl_clk_0_1 1 0 1 N 1450
+preplace netloc pl_sysref_0_1 1 0 1 N 1470
+preplace netloc ps8_0_axi_periph_M00_AXI 1 1 1 NJ 330
+preplace netloc ps8_0_axi_periph_M01_AXI 1 0 2 50 200 670J
+preplace netloc s00_axis_0_1 1 0 1 NJ 540
+preplace netloc s02_axis_0_1 1 0 1 NJ 560
+preplace netloc s10_axis_0_1 1 0 1 NJ 580
+preplace netloc s12_axis_0_1 1 0 1 NJ 600
+preplace netloc s20_axis_0_1 1 0 1 NJ 620
+preplace netloc s22_axis_0_1 1 0 1 NJ 640
+preplace netloc s30_axis_0_1 1 0 1 NJ 660
+preplace netloc s32_axis_0_1 1 0 1 NJ 680
+preplace netloc sysref_in_0_1 1 0 1 NJ 900
+preplace netloc usp_rf_data_converter_m00_axis 1 1 3 N 590 NJ 590 N
+preplace netloc usp_rf_data_converter_m01_axis 1 1 3 N 610 NJ 610 N
+preplace netloc usp_rf_data_converter_m02_axis 1 1 3 N 630 NJ 630 N
+preplace netloc usp_rf_data_converter_m03_axis 1 1 3 N 650 NJ 650 N
+preplace netloc usp_rf_data_converter_m10_axis 1 1 3 N 670 NJ 670 N
+preplace netloc usp_rf_data_converter_m11_axis 1 1 3 N 690 NJ 690 N
+preplace netloc usp_rf_data_converter_m12_axis 1 1 3 N 710 NJ 710 N
+preplace netloc usp_rf_data_converter_m13_axis 1 1 3 N 730 NJ 730 N
+preplace netloc usp_rf_data_converter_m20_axis 1 1 3 N 750 NJ 750 N
+preplace netloc usp_rf_data_converter_m21_axis 1 1 3 N 770 NJ 770 N
+preplace netloc usp_rf_data_converter_m22_axis 1 1 3 N 790 NJ 790 N
+preplace netloc usp_rf_data_converter_m23_axis 1 1 3 N 810 NJ 810 N
+preplace netloc usp_rf_data_converter_m30_axis 1 1 3 N 830 NJ 830 N
+preplace netloc usp_rf_data_converter_m31_axis 1 1 3 N 850 NJ 850 N
+preplace netloc usp_rf_data_converter_m32_axis 1 1 3 N 870 NJ 870 N
+preplace netloc usp_rf_data_converter_m33_axis 1 1 3 N 890 NJ 890 N
+preplace netloc usp_rf_data_converter_vout00 1 1 3 N 910 NJ 910 N
+preplace netloc usp_rf_data_converter_vout02 1 1 3 N 930 NJ 930 N
+preplace netloc usp_rf_data_converter_vout10 1 1 3 N 950 NJ 950 N
+preplace netloc usp_rf_data_converter_vout12 1 1 3 N 970 NJ 970 N
+preplace netloc usp_rf_data_converter_vout20 1 1 3 N 990 NJ 990 N
+preplace netloc usp_rf_data_converter_vout22 1 1 3 N 1010 NJ 1010 N
+preplace netloc usp_rf_data_converter_vout30 1 1 3 N 1030 NJ 1030 N
+preplace netloc usp_rf_data_converter_vout32 1 1 3 N 1050 NJ 1050 N
+preplace netloc vin0_01_0_1 1 0 1 NJ 740
+preplace netloc vin0_23_0_1 1 0 1 NJ 760
+preplace netloc vin1_01_0_1 1 0 1 NJ 780
+preplace netloc vin1_23_0_1 1 0 1 NJ 800
+preplace netloc vin2_01_0_1 1 0 1 NJ 820
+preplace netloc vin2_23_0_1 1 0 1 NJ 840
+preplace netloc vin3_01_0_1 1 0 1 NJ 860
+preplace netloc vin3_23_0_1 1 0 1 NJ 880
+preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_LPD 1 0 2 40 20 670
+levelinfo -pg 1 0 360 880 1080 1120
+pagesize -pg 1 -db -bbox -sgen -170 0 1240 1530
+"
+}
+{
+   "da_axi4_cnt":"4",
+   "da_board_cnt":"1"
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui

@@ -0,0 +1,28 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-578,-657",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
+preplace port spi -pg 1 -lvl 3 -x 740 -y -250 -defaultsOSRD
+preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
+preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
+preplace port port-id_active -pg 1 -lvl 3 -x 740 -y -230 -defaultsOSRD
+preplace port port-id_irq -pg 1 -lvl 3 -x 740 -y -320 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
+preplace inst spi_engine_execution -pg 1 -lvl 2 -x 600 -y -240 -defaultsOSRD
+preplace netloc axi_spi_engine_irq 1 1 2 480J -320 NJ
+preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
+preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 490J
+preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
+preplace netloc spi_engine_execution_active 1 2 1 NJ -230
+preplace netloc Conn1 1 0 1 NJ -270
+preplace netloc Conn2 1 2 1 NJ -250
+preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
+levelinfo -pg 1 0 340 600 740
+pagesize -pg 1 -db -bbox -sgen -150 -630 840 180
+"
+}
+0

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_ea40ff00.ui

@@ -0,0 +1,26 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-578,-657",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
+#  -string -flagsOSRD
+preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
+preplace port spi -pg 1 -lvl 3 -x 710 -y -250 -defaultsOSRD
+preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
+preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
+preplace port port-id_active -pg 1 -lvl 3 -x 710 -y -230 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
+preplace inst spi_engine_execution -pg 1 -lvl 2 -x 590 -y -240 -defaultsOSRD
+preplace netloc axi_spi_engine_spi_resetn 1 1 1 N -220
+preplace netloc s_axi_aclk_0_1 1 0 2 200 -150 480J
+preplace netloc spi_engine_execution_active 1 2 1 NJ -230
+preplace netloc s_axi_aresetn_1 1 0 1 NJ -230
+preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
+preplace netloc Conn1 1 0 1 NJ -270
+preplace netloc Conn2 1 2 1 NJ -250
+levelinfo -pg 1 0 340 590 710
+pagesize -pg 1 -db -bbox -sgen -150 -630 810 180
+"
+}
+

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci

@@ -0,0 +1,213 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "cmpy_18x8",
+    "component_reference": "xilinx.com:ip:cmpy:6.0",
+    "ip_revision": "24",
+    "gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "cmpy_18x8", "resolve_type": "user", "usage": "all" } ],
+        "APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasATUSER": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "BPortWidth": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MultType": [ { "value": "Use_LUTs", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
+        "FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
+        "RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
+        "OutputWidth": [ { "value": "27", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
+        "LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
+        "MinimumLatency": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "zynquplus", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICE": [ { "value": "xczu47dr", "resolve_type": "generated", "usage": "all" } ],
+        "C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_B_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OUT_WIDTH": [ { "value": "27", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MULT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TDATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "24" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dj_47dr_lmx.gen/sources_1/ip/cmpy_18x8" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
+        "s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_b_tdata": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_dout_tdata": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "8", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci

@@ -0,0 +1,358 @@
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+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
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+        "STATIC_POWER": [ { "value": "" } ],
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+      },
+      "runtime_parameters": {
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+        "IPREVISION": [ { "value": "25" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dj_47dr_lmx.gen/sources_1/ip/dds_32b_8b" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
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+      }
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+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
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+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
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+          }
+        },
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+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
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+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_phase_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
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+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
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+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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+          },
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+            "TVALID": [ { "physical_name": "s_axis_config_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/hop_rom/hop_rom.xci

@@ -0,0 +1,254 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "hop_rom",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "8",
+    "gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/ip/hop_rom",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "hop_rom", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
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+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Single_Port_ROM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "Write_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+        "Read_Width_A": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
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+        "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "../sweep_freq.coe", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "C_COEF_MEM_PACKING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_FILTS_PACKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LATENCY": [ { "value": "17", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ARESETn": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_FIFO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TREADY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_HAS_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TDATA_WIDTH": [ { "value": "24", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_M_DATA_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_HAS_CONFIG_CHANNEL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_SYNC_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_PACKET_SIZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CONFIG_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RELOAD_TDATA_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xczu47dr" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
+        "PACKAGE": [ { "value": "ffve1156" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "I" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "22" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dj_47dr_lmx.gen/sources_1/ip/hrc_64_12_025" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "aclk": [ { "direction": "in" } ],
+        "s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
+        "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ],
+        "s_axis_data_tdata": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
+        "m_axis_data_tdata": [ { "direction": "out", "size_left": "23", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "event_s_data_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_data_chanid_incorrect_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_config_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_missing_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "event_s_reload_tlast_unexpected_intf": {
+          "vlnv": "xilinx.com:signal:interrupt:1.0",
+          "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
+            "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_data_tdata" } ],
+            "TREADY": [ { "physical_name": "s_axis_data_tready" } ],
+            "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ]
+          }
+        },
+        "M_AXIS_DATA": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "3", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_data_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/ip/sweep_freq.coe

@@ -0,0 +1,258 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR = 
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v

@@ -0,0 +1,716 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 03/15/2022 08:34:01 PM
+// Design Name:
+// Module Name: system_top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module system_top
+(
+    // *************************************************************************
+    // *************************** Clocks and SYSREF ***************************
+    // *************************************************************************
+    // adc clock
+    input       adc1_clk_in_p       ,
+    input       adc1_clk_in_n       ,
+    input       adc2_clk_in_p       ,
+    input       adc2_clk_in_n       ,
+    // dac clock
+    input       dac0_clk_in_p       ,
+    input       dac0_clk_in_n       ,
+    input       dac2_clk_in_p       ,
+    input       dac2_clk_in_n       ,
+    // sysref for rf
+    input       rf_sysref_p         ,
+    input       rf_sysref_n         ,
+    // sysref for pl
+    input       pl_sysref_p         ,
+    input       pl_sysref_n         ,
+    // fpga clock
+    input       pl_refclk_p         ,
+    input       pl_refclk_n         ,
+    // *************************************************************************
+    // ******************************** RF-DAC *********************************
+    // *************************************************************************
+    input       adc0_01_in_p        ,
+    input       adc0_01_in_n        ,
+    input       adc0_23_in_p        ,
+    input       adc0_23_in_n        ,
+    input       adc1_01_in_p        ,
+    input       adc1_01_in_n        ,
+    input       adc1_23_in_p        ,
+    input       adc1_23_in_n        ,
+    input       adc2_01_in_p        ,
+    input       adc2_01_in_n        ,
+    input       adc2_23_in_p        ,
+    input       adc2_23_in_n        ,
+    input       adc3_01_in_p        ,
+    input       adc3_01_in_n        ,
+    input       adc3_23_in_p        ,
+    input       adc3_23_in_n        ,
+    // *************************************************************************
+    // ******************************** RF-DAC *********************************
+    // *************************************************************************
+    output      dac00_out_p         ,
+    output      dac00_out_n         ,
+    output      dac02_out_p         ,
+    output      dac02_out_n         ,
+    output      dac10_out_p         ,
+    output      dac10_out_n         ,
+    output      dac12_out_p         ,
+    output      dac12_out_n         ,
+    output      dac20_out_p         ,
+    output      dac20_out_n         ,
+    output      dac22_out_p         ,
+    output      dac22_out_n         ,
+    output      dac30_out_p         ,
+    output      dac30_out_n         ,
+    output      dac32_out_p         ,
+    output      dac32_out_n         ,
+    // *************************************************************************
+    // ***************************** SPI Interface *****************************
+    // *************************************************************************
+    // lmk04828
+    output      lmk_spi_sck         ,
+    output      lmk_spi_cs          ,
+    inout       lmk_spi_mosi        ,
+    input       lmk_spi_miso        ,
+    // lmx2594-adc
+    output      lmx_adc_spi_sck     ,
+    output      lmx_adc_spi_cs      ,
+    inout       lmx_adc_spi_mosi    ,
+    input       lmx_adc_spi_miso    ,
+    // lmx2594-dac
+    output      lmx_dac_spi_sck     ,
+    output      lmx_dac_spi_cs      ,
+    inout       lmx_dac_spi_mosi    ,
+    input       lmx_dac_spi_miso
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Block Design Interface ////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+wire ps_clk0;
+wire sys_clk;
+wire sys_rstn;
+
+// spi interface
+wire spi_sclk      ;
+wire [2:0] spi_cs  ;
+reg spi_sdi        ;
+wire spi_sdo       ;
+wire spi_sdo_t     ;
+wire spi_three_wire;
+wire spi_active    ;
+
+assign lmk_spi_sck = spi_sclk;
+assign lmk_spi_cs = spi_cs[0];
+assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
+
+assign lmx_adc_spi_sck = spi_sclk;
+assign lmx_adc_spi_cs = spi_cs[1];
+assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
+
+assign lmx_dac_spi_sck = spi_sclk;
+assign lmx_dac_spi_cs = spi_cs[2];
+assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
+
+always @(*) begin
+    case (spi_cs)
+        3'b110:  spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
+        3'b101:  spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
+        3'b011:  spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
+        default: spi_sdi = 1'bz;
+    endcase
+end
+
+// -----------------------------------------------------------------------------
+// ADC Tile & Channel Mapping (Dual RF-ADC)
+// -----------------------------------------------------------------------------
+// m00_axis     adc00       adc tile 224 (adc0), channel 0
+// m01_axis     adc01       adc tile 224 (adc0), channel 1
+// m02_axis     adc02       adc tile 224 (adc0), channel 2
+// m03_axis     adc03       adc tile 224 (adc0), channel 3
+// -----------------------------------------------------------------------------
+// m10_axis     adc10       adc tile 225 (adc1), channel 0
+// m11_axis     adc11       adc tile 225 (adc1), channel 1
+// m12_axis     adc12       adc tile 225 (adc1), channel 2
+// m13_axis     adc13       adc tile 225 (adc1), channel 3
+// -----------------------------------------------------------------------------
+// m20_axis     adc20       adc tile 226 (adc2), channel 0
+// m21_axis     adc21       adc tile 226 (adc2), channel 1
+// m22_axis     adc22       adc tile 226 (adc2), channel 2
+// m23_axis     adc23       adc tile 226 (adc2), channel 3
+// -----------------------------------------------------------------------------
+// m30_axis     adc30       adc tile 227 (adc3), channel 0
+// m31_axis     adc31       adc tile 227 (adc3), channel 1
+// m32_axis     adc32       adc tile 227 (adc3), channel 2
+// m33_axis     adc33       adc tile 227 (adc3), channel 3
+// -----------------------------------------------------------------------------
+// Note:
+// 1) If digital output data is set to real, only channel 0/2 is enabled; if
+// digital output data is set to i/q, both channel 0/2 and 1/3 are enabled,
+// since i/q data are transferred in different channels.
+// 2) When modify the following wire definition, **ONLY** change the data width.
+// The extra definition will be optimized automatically.
+// -----------------------------------------------------------------------------
+wire [15:0] adc00_data, adc01_data;
+wire adc00_data_ready, adc01_data_ready;
+wire adc00_data_valid, adc01_data_valid;
+
+wire [15:0] adc02_data, adc03_data;
+wire adc02_data_ready, adc03_data_ready;
+wire adc02_data_valid, adc03_data_valid;
+
+wire [15:0] adc10_data, adc11_data;
+wire adc10_data_ready, adc11_data_ready;
+wire adc10_data_valid, adc11_data_valid;
+
+wire [15:0] adc12_data, adc13_data;
+wire adc12_data_ready, adc13_data_ready;
+wire adc12_data_valid, adc13_data_valid;
+
+wire [15:0] adc20_data, adc21_data;
+wire adc20_data_ready, adc21_data_ready;
+wire adc20_data_valid, adc21_data_valid;
+
+wire [15:0] adc22_data, adc23_data;
+wire adc22_data_ready, adc23_data_ready;
+wire adc22_data_valid, adc23_data_valid;
+
+wire [15:0] adc30_data, adc31_data;
+wire adc30_data_ready, adc31_data_ready;
+wire adc30_data_valid, adc31_data_valid;
+
+wire [15:0] adc32_data, adc33_data;
+wire adc32_data_ready, adc33_data_ready;
+wire adc32_data_valid, adc33_data_valid;
+
+// -----------------------------------------------------------------------------
+// DAC Tile & Channel Mapping (Dual RF-DAC)
+// -----------------------------------------------------------------------------
+// s00_axis     dac00       dac tile 228 (dac0), channel 0
+// s01_axis     dac00       dac tile 228 (dac0), channel 1
+// s02_axis     dac02       dac tile 228 (dac0), channel 2
+// s03_axis     dac02       dac tile 228 (dac0), channel 3
+// -----------------------------------------------------------------------------
+// s10_axis     dac10       dac tile 229 (dac1), channel 0
+// s11_axis     dac10       dac tile 229 (dac1), channel 1
+// s12_axis     dac12       dac tile 229 (dac1), channel 2
+// s13_axis     dac12       dac tile 229 (dac1), channel 3
+// -----------------------------------------------------------------------------
+// s20_axis     dac20       dac tile 230 (dac2), channel 0
+// s21_axis     dac20       dac tile 230 (dac2), channel 1
+// s22_axis     dac22       dac tile 230 (dac2), channel 2
+// s23_axis     dac22       dac tile 230 (dac2), channel 3
+// -----------------------------------------------------------------------------
+// s30_axis     dac30       dac tile 231 (dac3), channel 0
+// s31_axis     dac30       dac tile 231 (dac3), channel 1
+// s32_axis     dac32       dac tile 231 (dac3), channel 2
+// s33_axis     dac32       dac tile 231 (dac3), channel 3
+// -----------------------------------------------------------------------------
+// Note:
+// 1) In most single-band cases, only channel 0/2 is enabled since i/q data are
+// transferred in one signle channel; when multi-band is used, multiple digital
+// channel may be enabled.
+// 2) When modify the following wire definition, **ONLY** change the data width.
+// The extra definition will be optimized automatically.
+// -----------------------------------------------------------------------------
+wire [31:0] dac00_data, dac01_data;
+wire dac00_data_ready, dac01_data_ready;
+wire dac00_data_valid, dac01_data_valid;
+
+wire [31:0] dac02_data, dac03_data;
+wire dac02_data_ready, dac03_data_ready;
+wire dac02_data_valid, dac03_data_valid;
+
+wire [31:0] dac10_data, dac11_data;
+wire dac10_data_ready, dac11_data_ready;
+wire dac10_data_valid, dac11_data_valid;
+
+wire [31:0] dac12_data, dac13_data;
+wire dac12_data_ready, dac13_data_ready;
+wire dac12_data_valid, dac13_data_valid;
+
+wire [31:0] dac20_data, dac21_data;
+wire dac20_data_ready, dac21_data_ready;
+wire dac20_data_valid, dac21_data_valid;
+
+wire [31:0] dac22_data, dac23_data;
+wire dac22_data_ready, dac23_data_ready;
+wire dac22_data_valid, dac23_data_valid;
+
+wire [31:0] dac30_data, dac31_data;
+wire dac30_data_ready, dac31_data_ready;
+wire dac30_data_valid, dac31_data_valid;
+
+wire [31:0] dac32_data, dac33_data;
+wire dac32_data_ready, dac33_data_ready;
+wire dac32_data_valid, dac33_data_valid;
+
+system_bd_wrapper u_system_bd_wrapper
+(
+    // *************************************************************************
+    // ********************* PL SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    .ps_clk0            (ps_clk0            ),
+
+    .pl_clk_clk_p       (pl_refclk_p        ),
+    .pl_clk_clk_n       (pl_refclk_n        ),
+
+    .pl_sysref_clk_p    (pl_sysref_p        ),
+    .pl_sysref_clk_n    (pl_sysref_n        ),
+
+    .sys_clk            (sys_clk            ),
+    .sys_rstn           (sys_rstn           ),
+
+    // *************************************************************************
+    // ********************* RF SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    .spi_sclk           (spi_sclk           ),
+    .spi_cs             (spi_cs             ),
+    .spi_sdi            (spi_sdi            ),
+    .spi_sdo            (spi_sdo            ),
+    .spi_sdo_t          (spi_sdo_t          ),
+    .spi_three_wire     (spi_three_wire     ),
+    .spi_active         (spi_active         ),
+
+    // *************************************************************************
+    // ********************* RF SYSREF & Reference Clocks **********************
+    // *************************************************************************
+    // rf sysref
+    .sysref_in_diff_p   (rf_sysref_p        ), // input sysref_in_diff_p
+    .sysref_in_diff_n   (rf_sysref_n        ), // input sysref_in_diff_n
+
+    // -------------------------------------------------------------------------
+    // RF ADC Reference Clocks Mapping
+    // -------------------------------------------------------------------------
+    // adc0_clk_clk     adc tile 224 (adc0) ref clock input, nc on borad
+    // adc1_clk_clk     adc tile 225 (adc1) ref clock input, from lmk04828
+    // adc2_clk_clk     adc tile 226 (adc2) ref clock input, from sma
+    // adc3_clk_clk     adc tile 227 (adc3) ref clock input, nc on borad
+    // clk_adc0         adc tile 224 (adc0) clock output
+    // clk_adc1         adc tile 225 (adc1) clock output
+    // clk_adc2         adc tile 226 (adc2) clock output
+    // clk_adc3         adc tile 227 (adc3) clock output
+    // -------------------------------------------------------------------------
+    // Note:
+    // When modify the following wire connections, **ONLY** uncomment the needed
+    // ports and comment the not-needed ones.
+    // -------------------------------------------------------------------------
+    // .adc1_clk_clk_p     (adc1_clk_in_p      ), // input adc1_clk_clk_p
+    // .adc1_clk_clk_n     (adc1_clk_in_n      ), // input adc1_clk_clk_n
+    .adc2_clk_clk_p     (adc2_clk_in_p      ), // input adc2_clk_clk_p
+    .adc2_clk_clk_n     (adc2_clk_in_n      ), // input adc2_clk_clk_n
+    .clk_adc0           (                   ), // output clk_adc0
+    .clk_adc1           (                   ), // output clk_adc1
+    .clk_adc2           (                   ), // output clk_adc2
+    .clk_adc3           (                   ), // output clk_adc3
+
+    // -------------------------------------------------------------------------
+    // RF DAC Reference Clocks Mapping
+    // -------------------------------------------------------------------------
+    // dac0_clk_clk     dac tile 228 (dac0) ref clock input, from lmk04828
+    // dac1_clk_clk     dac tile 229 (dac1) ref clock input, none for zu48dr
+    // dac2_clk_clk     dac tile 230 (dac2) ref clock input, from sma
+    // dac3_clk_clk     dac tile 231 (dac3) ref clock input, none for zu48dr
+    // clk_dac0         dac tile 228 (dac0) clock output
+    // clk_dac1         dac tile 229 (dac1) clock output
+    // clk_dac2         dac tile 230 (dac2) clock output
+    // clk_dac3         dac tile 231 (dac3) clock output
+    // -------------------------------------------------------------------------
+    // Note:
+    // When modify the following wire connections, **ONLY** uncomment the needed
+    // ports and comment the not-needed ones.
+    // -------------------------------------------------------------------------
+    // .dac0_clk_clk_p     (dac0_clk_in_p      ), // input dac0_clk_clk_p
+    // .dac0_clk_clk_n     (dac0_clk_in_n      ), // input dac0_clk_clk_n
+    .dac2_clk_clk_p     (dac2_clk_in_p      ), // input dac2_clk_clk_p
+    .dac2_clk_clk_n     (dac2_clk_in_n      ), // input dac2_clk_clk_n
+    .clk_dac0           (                   ), // output clk_dac0
+    .clk_dac1           (                   ), // output clk_dac1
+    .clk_dac2           (                   ), // output clk_dac2
+    .clk_dac3           (                   ), // output clk_dac3
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 224 (adc0) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m0_axis_aclk       (sys_clk            ), // input m0_axis_aclk
+    .m0_axis_aresetn    (sys_rstn           ), // input m0_axis_aresetn
+
+    // channel 0 data
+    .m00_axis_tdata     (adc00_data         ), // output [15:0]m00_axis_tdata
+    .m00_axis_tready    (adc00_data_ready   ), // input m00_axis_tready
+    .m00_axis_tvalid    (adc00_data_valid   ), // output m00_axis_tvalid
+    // channel 1 data
+    .m01_axis_tdata     (adc01_data         ), // output [15:0]m01_axis_tdata
+    .m01_axis_tready    (adc01_data_ready   ), // input m01_axis_tready
+    .m01_axis_tvalid    (adc01_data_valid   ), // output m01_axis_tvalid
+    // analog input signal, J3 on board
+    .vin0_01_v_p        (adc0_01_in_p       ), // input vin0_01_v_p
+    .vin0_01_v_n        (adc0_01_in_n       ), // input vin0_01_v_n
+
+    // channel 2 data
+    .m02_axis_tdata     (adc02_data         ), // output [15:0]m02_axis_tdata
+    .m02_axis_tready    (adc02_data_ready   ), // input m02_axis_tready
+    .m02_axis_tvalid    (adc02_data_valid   ), // output m02_axis_tvalid
+    // channel 3 data
+    .m03_axis_tdata     (adc03_data         ), // output [15:0]m03_axis_tdata
+    .m03_axis_tready    (adc03_data_ready   ), // input m03_axis_tready
+    .m03_axis_tvalid    (adc03_data_valid   ), // output m03_axis_tvalid
+    // analog input signal, J5 on board
+    .vin0_23_v_p        (adc0_23_in_p       ), // input vin0_23_v_p
+    .vin0_23_v_n        (adc0_23_in_n       ), // input vin0_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 225 (adc1) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m1_axis_aclk       (sys_clk            ), // input m1_axis_aclk
+    .m1_axis_aresetn    (sys_rstn           ), // input m1_axis_aresetn
+
+    // channel 0 data
+    .m10_axis_tdata     (adc10_data         ), // output [15:0]m10_axis_tdata
+    .m10_axis_tready    (adc10_data_ready   ), // input m10_axis_tready
+    .m10_axis_tvalid    (adc10_data_valid   ), // output m10_axis_tvalid
+    // channel 1 data
+    .m11_axis_tdata     (adc11_data         ), // output [15:0]m11_axis_tdata
+    .m11_axis_tready    (adc11_data_ready   ), // input m11_axis_tready
+    .m11_axis_tvalid    (adc11_data_valid   ), // output m11_axis_tvalid
+    // analog input signal, J6 on board
+    .vin1_01_v_p        (adc1_01_in_p       ), // input vin1_01_v_p
+    .vin1_01_v_n        (adc1_01_in_n       ), // input vin1_01_v_n
+
+    // channel 2 data
+    .m12_axis_tdata     (adc12_data         ), // output [15:0]m12_axis_tdata
+    .m12_axis_tready    (adc12_data_ready   ), // input m12_axis_tready
+    .m12_axis_tvalid    (adc12_data_valid   ), // output m12_axis_tvalid
+    // channel 3 data
+    .m13_axis_tdata     (adc13_data         ), // output [15:0]m13_axis_tdata
+    .m13_axis_tready    (adc13_data_ready   ), // input m13_axis_tready
+    .m13_axis_tvalid    (adc13_data_valid   ), // output m13_axis_tvalid
+    // analog input signal, J7 on board
+    .vin1_23_v_p        (adc1_23_in_p       ), // input vin1_23_v_p
+    .vin1_23_v_n        (adc1_23_in_n       ), // input vin1_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 226 (adc2) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m2_axis_aclk       (sys_clk            ), // input m2_axis_aclk
+    .m2_axis_aresetn    (sys_rstn           ), // input m2_axis_aresetn
+
+    // channel 0 data
+    .m20_axis_tdata     (adc20_data         ), // output [15:0]m20_axis_tdata
+    .m20_axis_tready    (adc20_data_ready   ), // input m20_axis_tready
+    .m20_axis_tvalid    (adc20_data_valid   ), // output m20_axis_tvalid
+    // channel 1 data
+    .m21_axis_tdata     (adc21_data         ), // output [15:0]m21_axis_tdata
+    .m21_axis_tready    (adc21_data_ready   ), // input m21_axis_tready
+    .m21_axis_tvalid    (adc21_data_valid   ), // output m21_axis_tvalid
+    // analog input signal, J8 on board
+    .vin2_01_v_p        (adc2_01_in_p       ), // input vin2_01_v_p
+    .vin2_01_v_n        (adc2_01_in_n       ), // input vin2_01_v_n
+
+    // channel 2 data
+    .m22_axis_tdata     (adc22_data         ), // output [15:0]m22_axis_tdata
+    .m22_axis_tready    (adc22_data_ready   ), // input m22_axis_tready
+    .m22_axis_tvalid    (adc22_data_valid   ), // output m22_axis_tvalid
+    // channel 3 data
+    .m23_axis_tdata     (adc23_data         ), // output [15:0]m23_axis_tdata
+    .m23_axis_tready    (adc23_data_ready   ), // input m23_axis_tready
+    .m23_axis_tvalid    (adc23_data_valid   ), // output m23_axis_tvalid
+    // analog input signal, J9 on board
+    .vin2_23_v_p        (adc2_23_in_p       ), // input vin2_23_v_p
+    .vin2_23_v_n        (adc2_23_in_n       ), // input vin2_23_v_n
+
+    // *************************************************************************
+    // *********** RF-ADC Tile 227 (adc3) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .m3_axis_aclk       (sys_clk            ), // input m3_axis_aclk
+    .m3_axis_aresetn    (sys_rstn           ), // input m3_axis_aresetn
+
+    // channel 0 data
+    .m30_axis_tdata     (adc30_data         ), // output [15:0]m30_axis_tdata
+    .m30_axis_tready    (adc30_data_ready   ), // input m30_axis_tready
+    .m30_axis_tvalid    (adc30_data_valid   ), // output m30_axis_tvalid
+    // channel 1 data
+    .m31_axis_tdata     (adc31_data         ), // output [15:0]m31_axis_tdata
+    .m31_axis_tready    (adc31_data_ready   ), // input m31_axis_tready
+    .m31_axis_tvalid    (adc31_data_valid   ), // output m31_axis_tvalid
+    // analog input signal, J10 on board
+    .vin3_01_v_p        (adc3_01_in_p       ), // input vin3_01_v_p
+    .vin3_01_v_n        (adc3_01_in_n       ), // input vin3_01_v_n
+
+    // channel 2 data
+    .m32_axis_tdata     (adc32_data         ), // output [15:0]m32_axis_tdata
+    .m32_axis_tready    (adc32_data_ready   ), // input m32_axis_tready
+    .m32_axis_tvalid    (adc32_data_valid   ), // output m32_axis_tvalid
+    // channel 3 data
+    .m33_axis_tdata     (adc33_data         ), // output [15:0]m33_axis_tdata
+    .m33_axis_tready    (adc33_data_ready   ), // input m33_axis_tready
+    .m33_axis_tvalid    (adc33_data_valid   ), // output m33_axis_tvalid
+    // analog input signal, J12 on board
+    .vin3_23_v_p        (adc3_23_in_p       ), // input vin3_23_v_p
+    .vin3_23_v_n        (adc3_23_in_n       ), // input vin3_23_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 228 (dac0) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s0_axis_aclk       (sys_clk            ), // input s0_axis_aclk
+    .s0_axis_aresetn    (sys_rstn           ), // input s0_axis_aresetn
+
+    // channel 0 data
+    .s00_axis_tdata     (dac00_data         ), // input [31:0]s00_axis_tdata
+    .s00_axis_tready    (dac00_data_ready   ), // output s00_axis_tready
+    .s00_axis_tvalid    (dac00_data_valid   ), // input s00_axis_tvalid
+    // channel 1 data
+    // .s01_axis_tdata     (dac01_data         ), // input [31:0]s01_axis_tdata
+    // .s01_axis_tready    (dac01_data_ready   ), // output s01_axis_tready
+    // .s01_axis_tvalid    (dac01_data_valid   ), // input s01_axis_tvalid
+    // analog output signal, J14 on board
+    .vout00_v_p         (dac00_out_p        ), // output vout00_v_p
+    .vout00_v_n         (dac00_out_n        ), // output vout00_v_n
+
+    // channel 2 data
+    .s02_axis_tdata     (dac02_data         ), // input [31:0]s02_axis_tdata
+    .s02_axis_tready    (dac02_data_ready   ), // output s02_axis_tready
+    .s02_axis_tvalid    (dac02_data_valid   ), // input s02_axis_tvalid
+    // channel 3 data
+    // .s03_axis_tdata     (dac03_data         ), // input [31:0]s03_axis_tdata
+    // .s03_axis_tready    (dac03_data_ready   ), // output s03_axis_tready
+    // .s03_axis_tvalid    (dac03_data_valid   ), // input s03_axis_tvalid
+    // analog output signal, J16 on board
+    .vout02_v_p         (dac02_out_p        ), // output vout02_v_p
+    .vout02_v_n         (dac02_out_n        ), // output vout02_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 229 (dac1) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s1_axis_aclk       (sys_clk            ), // input s1_axis_aclk
+    .s1_axis_aresetn    (sys_rstn           ), // input s1_axis_aresetn
+
+    // channel 0 data
+    .s10_axis_tdata     (dac10_data         ), // input [31:0]s10_axis_tdata
+    .s10_axis_tready    (dac10_data_ready   ), // output s10_axis_tready
+    .s10_axis_tvalid    (dac10_data_valid   ), // input s10_axis_tvalid
+    // channel 1 data
+    // .s11_axis_tdata     (dac11_data         ), // input [31:0]s11_axis_tdata
+    // .s11_axis_tready    (dac11_data_ready   ), // output s11_axis_tready
+    // .s11_axis_tvalid    (dac11_data_valid   ), // input s11_axis_tvalid
+    // analog output signal, J17 on board
+    .vout10_v_p         (dac10_out_p        ), // output vout10_v_p
+    .vout10_v_n         (dac10_out_n        ), // output vout10_v_n
+
+    // channel 2 data
+    .s12_axis_tdata     (dac12_data         ), // input [31:0]s12_axis_tdata
+    .s12_axis_tready    (dac12_data_ready   ), // output s12_axis_tready
+    .s12_axis_tvalid    (dac12_data_valid   ), // input s12_axis_tvalid
+    // channel 3 data
+    // .s13_axis_tdata     (dac13_data         ), // input [31:0]s13_axis_tdata
+    // .s13_axis_tready    (dac13_data_ready   ), // output s13_axis_tready
+    // .s13_axis_tvalid    (dac13_data_valid   ), // input s13_axis_tvalid
+    // analog output signal, J18 on board
+    .vout12_v_p         (dac12_out_p        ), // output vout12_v_p
+    .vout12_v_n         (dac12_out_n        ), // output vout12_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 230 (dac2) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s2_axis_aclk       (sys_clk            ), // input s2_axis_aclk
+    .s2_axis_aresetn    (sys_rstn           ), // input s2_axis_aresetn
+
+    // channel 0 data
+    .s20_axis_tdata     (dac20_data         ), // input [31:0]s20_axis_tdata
+    .s20_axis_tready    (dac20_data_ready   ), // output s20_axis_tready
+    .s20_axis_tvalid    (dac20_data_valid   ), // input s20_axis_tvalid
+    // channel 1 data
+    // .s21_axis_tdata     (dac21_data         ), // input [31:0]s21_axis_tdata
+    // .s21_axis_tready    (dac21_data_ready   ), // output s21_axis_tready
+    // .s21_axis_tvalid    (dac21_data_valid   ), // input s21_axis_tvalid
+    // analog output signal, J19 on board
+    .vout20_v_p         (dac20_out_p        ), // output vout20_v_p
+    .vout20_v_n         (dac20_out_n        ), // output vout20_v_n
+
+    // channel 2 data
+    .s22_axis_tdata     (dac22_data         ), // input [31:0]s22_axis_tdata
+    .s22_axis_tready    (dac22_data_ready   ), // output s22_axis_tready
+    .s22_axis_tvalid    (dac22_data_valid   ), // input s22_axis_tvalid
+    // channel 3 data
+    // .s23_axis_tdata     (dac23_data         ), // input [31:0]s23_axis_tdata
+    // .s23_axis_tready    (dac23_data_ready   ), // output s23_axis_tready
+    // .s23_axis_tvalid    (dac23_data_valid   ), // input s23_axis_tvalid
+    // analog output signal, J20 on board
+    .vout22_v_p         (dac22_out_p        ), // output vout22_v_p
+    .vout22_v_n         (dac22_out_n        ), // output vout22_v_n
+
+    // *************************************************************************
+    // *********** RF-DAC Tile 231 (dac3) Digital & Analog Interface ***********
+    // *************************************************************************
+    // fabric clock (axi4-stream clock)
+    .s3_axis_aclk       (sys_clk            ), // input s3_axis_aclk
+    .s3_axis_aresetn    (sys_rstn           ), // input s3_axis_aresetn
+
+    // channel 0 data
+    .s30_axis_tdata     (dac30_data         ), // input [31:0]s30_axis_tdata
+    .s30_axis_tready    (dac30_data_ready   ), // output s30_axis_tready
+    .s30_axis_tvalid    (dac30_data_valid   ), // input s30_axis_tvalid
+    // channel 1 data
+    // .s31_axis_tdata     (dac31_data         ), // input [31:0]s31_axis_tdata
+    // .s31_axis_tready    (dac31_data_ready   ), // output s31_axis_tready
+    // .s31_axis_tvalid    (dac31_data_valid   ), // input s31_axis_tvalid
+    // analog output signal, J21 on board
+    .vout30_v_p         (dac30_out_p        ), // output vout30_v_p
+    .vout30_v_n         (dac30_out_n        ), // output vout30_v_n
+
+    // channel 2 data
+    .s32_axis_tdata     (dac32_data         ), // input [31:0]s32_axis_tdata
+    .s32_axis_tready    (dac32_data_ready   ), // output s32_axis_tready
+    .s32_axis_tvalid    (dac32_data_valid   ), // input s32_axis_tvalid
+    // channel 3 data
+    // .s33_axis_tdata     (dac33_data         ), // input [31:0]s33_axis_tdata
+    // .s33_axis_tready    (dac33_data_ready   ), // output s33_axis_tready
+    // .s33_axis_tvalid    (dac33_data_valid   ), // input s33_axis_tvalid
+    // analog output signal, J23 on board
+    .vout32_v_p         (dac32_out_p        ), // output vout32_v_p
+    .vout32_v_n         (dac32_out_n        )  // output vout32_v_n
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////// Tx Signal ///////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// tx signal mapping
+wire    [15:0]  tx_data_i, tx_data_q;
+
+assign dac00_data = {tx_data_q, tx_data_i};
+assign dac02_data = {tx_data_q, tx_data_i};
+assign dac10_data = {tx_data_q, tx_data_i};
+assign dac12_data = {tx_data_q, tx_data_i};
+assign dac20_data = {tx_data_q, tx_data_i};
+assign dac22_data = {tx_data_q, tx_data_i};
+assign dac30_data = {tx_data_q, tx_data_i};
+assign dac32_data = {tx_data_q, tx_data_i};
+
+// transimitter logic
+wire    [ 1:0]  waveform_sel;
+wire            sweep_on    ;
+wire    [31:0]  freq_set    ;
+wire    [ 1:0]  iq_sel      ;
+wire    [ 3:0]  bb_rshift   ;
+
+tx_qpsk #(
+    .DATA_WIDTH     (16),
+    .BIT_DATA       (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
+    .BIT_DATA_LEN   (1024),
+    .CLK_FREQ       (245_760_000)
+) u_tx_qpsk
+(
+    .clk            (sys_clk            ), // input           clk
+    .rst            (~sys_rstn          ), // input           rst
+    .tx_data_i      (tx_data_i          ), // output  [15:0]  tx_data_i
+    .tx_data_q      (tx_data_q          ), // output  [15:0]  tx_data_q
+    // debug ports
+    .waveform_sel   (waveform_sel[1:0]  ), // input   [ 1:0]  waveform_sel
+    .sweep_on       (sweep_on           ), // input           sweep_on
+    .freq_set       (freq_set           ), // input   [31:0]  freq_set
+    .iq_sel         (iq_sel             ), // input   [ 1:0]  iq_sel
+    .bb_rshift      (bb_rshift          )  // input   [ 3:0]  bb_rshift
+);
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////// Rx Signal ///////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// rx signal mapping
+wire    [15:0]  rx_ch1_i, rx_ch1_q;
+wire    [15:0]  rx_ch2_i, rx_ch2_q;
+wire    [15:0]  rx_ch3_i, rx_ch3_q;
+wire    [15:0]  rx_ch4_i, rx_ch4_q;
+wire    [15:0]  rx_ch5_i, rx_ch5_q;
+wire    [15:0]  rx_ch6_i, rx_ch6_q;
+wire    [15:0]  rx_ch7_i, rx_ch7_q;
+wire    [15:0]  rx_ch8_i, rx_ch8_q;
+
+assign rx_ch1_i = adc00_data;
+assign rx_ch1_q = adc01_data;
+assign rx_ch2_i = adc02_data;
+assign rx_ch2_q = adc03_data;
+assign rx_ch3_i = adc10_data;
+assign rx_ch3_q = adc11_data;
+assign rx_ch4_i = adc12_data;
+assign rx_ch4_q = adc13_data;
+assign rx_ch5_i = adc20_data;
+assign rx_ch5_q = adc21_data;
+assign rx_ch6_i = adc22_data;
+assign rx_ch6_q = adc23_data;
+assign rx_ch7_i = adc30_data;
+assign rx_ch7_q = adc31_data;
+assign rx_ch8_i = adc32_data;
+assign rx_ch8_q = adc33_data;
+
+// receiver logic
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////// ILAs and VIOs /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+ila_adc u_ila_adc
+(
+    .clk    (sys_clk            ), // input wire clk
+    .probe0 (rx_ch1_i           ), // input wire [15:0]  probe0
+    .probe1 (rx_ch1_q           ), // input wire [15:0]  probe1
+    .probe2 (rx_ch2_i           ), // input wire [15:0]  probe2
+    .probe3 (rx_ch2_q           ), // input wire [15:0]  probe3
+    .probe4 (rx_ch3_i           ), // input wire [15:0]  probe4
+    .probe5 (rx_ch3_q           ), // input wire [15:0]  probe5
+    .probe6 (rx_ch4_i           ), // input wire [15:0]  probe6
+    .probe7 (rx_ch4_q           ), // input wire [15:0]  probe7
+    .probe8 (rx_ch5_i           ), // input wire [15:0]  probe8
+    .probe9 (rx_ch5_q           ), // input wire [15:0]  probe9
+    .probe10(rx_ch6_i           ), // input wire [15:0]  probe10
+    .probe11(rx_ch6_q           ), // input wire [15:0]  probe11
+    .probe12(rx_ch7_i           ), // input wire [15:0]  probe12
+    .probe13(rx_ch7_q           ), // input wire [15:0]  probe13
+    .probe14(rx_ch8_i           ), // input wire [15:0]  probe14
+    .probe15(rx_ch8_q           )  // input wire [15:0]  probe15
+);
+
+ila_dac u_ila_dac
+(
+    .clk    (sys_clk            ), // input wire clk
+    .probe0 (tx_data_i          ), // input wire [15:0]  probe0
+    .probe1 (tx_data_q          )  // input wire [15:0]  probe1
+);
+
+vio_manual_ctrl u_vio_manual_ctrl
+(
+    .clk        (sys_clk            ), // input wire clk
+    .probe_out0 (waveform_sel[1:0]  ), // output wire [1 : 0] probe_out0
+    .probe_out1 (sweep_on           ), // output wire [0 : 0] probe_out1
+    .probe_out2 (freq_set[31:0]     ), // output wire [31 : 0] probe_out2
+    .probe_out3 (iq_sel[1:0]        ), // output wire [1 : 0] probe_out3
+    .probe_out4 (bb_rshift[3:0]     )  // output wire [3 : 0] probe_out4
+);
+
+endmodule

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/tx_qpsk.v

@@ -0,0 +1,539 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/03/23 20:17:56
+// Last Modified Date: 2023/03/10 15:41
+// Design Name:
+// Module Name: tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从
+//     乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。
+//   20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8
+//     倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计
+//     算得出。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_qpsk
+#(
+    parameter DATA_WIDTH = 12, // need to be <= 16
+    parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
+    parameter BIT_DATA_LEN = 128,
+    parameter SQUARE_INTERP = 8,
+    parameter CLK_FREQ = 245760000 // in Hertz
+)
+(
+    input           clk                 ,
+    input           rst                 ,
+    output [DATA_WIDTH-1:0] tx_data_i   ,
+    output [DATA_WIDTH-1:0] tx_data_q   ,
+    // debug ports
+    input   [ 1:0]  waveform_sel        ,
+    input           sweep_on            ,
+    input   [31:0]  freq_set            ,
+    input   [ 1:0]  iq_sel              ,
+    input   [ 3:0]  bb_rshift
+);
+
+localparam RCOS_INTERP = 64;
+localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP;
+localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ;
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////////// Data Counter /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// symbol & interpolation counter
+reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0]  cnt = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt <= 'b0;
+    end
+    else begin
+        cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1;
+    end
+end
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////// Root-Rasied Cosine Shaping Filter ///////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0;
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_addr_i <= 'b0;
+        hrc_data_addr_q <= 'b1;
+    end
+    else begin
+        hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0};
+        hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1};
+    end
+end
+
+// bit data
+reg hrc_data_i = 'b0;
+reg hrc_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hrc_data_i <= 'b0;
+        hrc_data_q <= 'b0;
+    end
+    else begin
+        hrc_data_i <= BIT_DATA[hrc_data_addr_i];
+        hrc_data_q <= BIT_DATA[hrc_data_addr_q];
+    end
+end
+
+// polarization
+wire    [ 7:0]  hrc_data_polar_i;
+wire    [ 7:0]  hrc_data_polar_q;
+
+assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1};
+assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1};
+
+// root raised cosine shaping-filter
+wire    [23:0]  hrc_wave_i;
+wire    [23:0]  hrc_wave_q;
+
+hrc_64_12_025 u_hrc_i (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_i   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_i         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+hrc_64_12_025 u_hrc_q (
+    .aclk               (clk                ), // input wire aclk
+    .s_axis_data_tvalid (~rst               ), // input wire s_axis_data_tvalid
+    .s_axis_data_tready (                   ), // output wire s_axis_data_tready
+    .s_axis_data_tdata  (hrc_data_polar_q   ), // input wire [7 : 0] s_axis_data_tdata
+    .m_axis_data_tvalid (                   ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata  (hrc_wave_q         )  // output wire [23 : 0] m_axis_data_tdata
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Square Shaping Filter /////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// address
+reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data_addr <= 'b0;
+    end
+    else
+        hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]};
+end
+
+// bit data
+reg hsq_data = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_data <= 'b0;
+    end
+    else begin
+        hsq_data <= BIT_DATA[hsq_data_addr];
+    end
+end
+
+// square shaping-filter
+reg     [17:0]  hsq_wave_i ='b0;
+reg     [17:0]  hsq_wave_q ='b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        hsq_wave_i <= 'b0;
+        hsq_wave_q <= 'b0;
+    end
+    else begin
+        hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001;
+        hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111;
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////// Two Tone Siganl ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// cosine wave with freq of 1 MHz
+wire signed [7:0] cos_1m;
+wire signed [7:0] sin_1m;
+
+dds_32b_8b u_dds_1m
+(
+    .aclk                 (clk                  ),  // input wire aclk
+    .s_axis_config_tvalid (1'b1                 ),  // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (FREQ_WORD_1M[31:0]   ),  // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                     ),  // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_1m,cos_1m}      )   // output wire [15 : 0] m_axis_data_tdata
+);
+
+// two-tone signal
+reg signed [16:0] two_tone_wave_i = 'b0;
+reg signed [16:0] two_tone_wave_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        two_tone_wave_i <= 'b0;
+        two_tone_wave_q <= 'b0;
+    end
+    else begin
+        two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0};
+        two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0};
+    end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////// Waveform Selection & Hopping Control /////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// baseband signal select
+reg [17:0] baseband_sel_i = 'b0;
+reg [17:0] baseband_sel_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_sel_i <= 'b0;
+        baseband_sel_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+            2'd1: begin
+                baseband_sel_i <= hsq_wave_i[17:0];
+                baseband_sel_q <= hsq_wave_q[17:0];
+            end
+            2'd2: begin
+                baseband_sel_i <= 18'b01_1111_1111_1111_1111;
+                baseband_sel_q <= 18'b0;
+            end
+            2'd3: begin
+                baseband_sel_i <= {two_tone_wave_i[16:0],1'b0};
+                baseband_sel_q <= {two_tone_wave_q[16:0],1'b0};
+            end
+            default: begin
+                baseband_sel_i <= {hrc_wave_i[16:0],1'b0};
+                baseband_sel_q <= {hrc_wave_q[16:0],1'b0};
+            end
+        endcase
+    end
+end
+
+// hopping control, 3750hop/s
+reg     [23:0]  sweep_rom_addr = 'b0;
+wire    [31:0]  freq_sweep;
+
+always @(posedge clk) begin
+    if (rst) begin
+        sweep_rom_addr <= 'b0;
+    end
+    else if (sweep_on) begin
+        sweep_rom_addr <= sweep_rom_addr + 24'b1;
+    end
+    else begin
+        sweep_rom_addr <= 'b0;
+    end
+end
+
+hop_rom u_sweep_rom
+(
+    .clka       (clk                    ), // input wire clka
+    .addra      (sweep_rom_addr[23:16]  ), // input wire [7 : 0] addra
+    .douta      (freq_sweep             )  // output wire [31 : 0] douta
+);
+
+// choose the actual frequency word
+reg     [31:0]  freq_word = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        freq_word <= 'b0;
+    end
+    else if (sweep_on) begin
+        // frequency sweep
+        freq_word <= freq_sweep;
+    end
+    else begin
+        // normal operation
+        freq_word <= freq_set;
+    end
+end
+
+// baseband frequency shift carrier generation
+wire    [ 7:0] cos_dds;
+wire    [ 7:0] sin_dds;
+reg     [ 7:0] cos = 'b0;
+reg     [ 7:0] sin = 'b0;
+
+dds_32b_8b u_dds_bb_shift (
+    .aclk                 (clk              ), // input wire aclk
+    .s_axis_config_tvalid (~rst             ), // input wire s_axis_config_tvalid
+    .s_axis_config_tdata  (freq_word        ), // input wire [31 : 0] s_axis_config_tdata
+    .m_axis_data_tvalid   (                 ), // output wire m_axis_data_tvalid
+    .m_axis_data_tdata    ({sin_dds,cos_dds})  // output wire [31 : 0] m_axis_data_tdata
+);
+
+always @(posedge clk) begin
+    if (rst) begin
+        cos <= 'b0;
+        sin <= 'b0;
+    end
+    else if (freq_word == 'b0) begin
+        // to make sure the carriers stay at the right position when freq = 0
+        cos <= 8'b0111_1111;
+        sin <= 8'b0111_1111;
+    end
+    else begin
+        cos <= cos_dds;
+        sin <= sin_dds;
+    end
+end
+
+// baseband frequency shift modulation
+wire    [47:0]  mod_cmpy_a;
+wire    [15:0]  mod_cmpy_b;
+wire    [63:0]  mod_cmpy_out;
+
+wire    [26:0]  baseband_mult_i;
+wire    [26:0]  baseband_mult_q;
+
+assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i};
+assign mod_cmpy_b = {-sin,cos};
+
+assign baseband_mult_i = mod_cmpy_out[58:32];
+assign baseband_mult_q = mod_cmpy_out[26: 0];
+
+cmpy_18x8 u_cmpy_18x8
+(
+    .aclk               (clk            ), // input wire aclk
+    .s_axis_a_tvalid    (1'b1           ), // input wire s_axis_a_tvalid
+    .s_axis_a_tdata     (mod_cmpy_a     ), // input wire [47 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid    (1'b1           ), // input wire s_axis_b_tvalid
+    .s_axis_b_tdata     (mod_cmpy_b     ), // input wire [15 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid (               ), // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata  (mod_cmpy_out   )  // output wire [63 : 0] m_axis_dout_tdata
+);
+
+// truncate to 16-bit
+reg signed  [15:0]  baseband_i = 'b0;
+reg signed  [15:0]  baseband_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_i <= 'b0;
+        baseband_q <= 'b0;
+    end
+    else begin
+        case (waveform_sel[1:0])
+            2'd0: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]});
+            end
+            2'd1: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]});
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]});
+            end
+            2'd2: begin
+                baseband_i <= baseband_mult_i[24:9];
+                baseband_q <= baseband_mult_q[24:9];
+            end
+            2'd3: begin
+                baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9];
+                baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9];
+            end
+            default: begin
+                // scale rasied-cosine-shaped bpsk signal by 1.125
+                baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]};
+                baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]};
+            end
+        endcase
+    end
+end
+
+// iq selection & baseband right shift
+reg signed [15:0] baseband_data_i = 'b0;
+reg signed [15:0] baseband_data_q = 'b0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        baseband_data_i <= 'b0;
+        baseband_data_q <= 'b0;
+    end
+    else begin
+        // inphase selection
+        if (iq_sel[1]) begin
+            baseband_data_i <= baseband_i >>> bb_rshift;
+        end
+        else begin
+            baseband_data_i <= 'b0;
+        end
+        // quadrature selection
+        if (iq_sel[0]) begin
+            baseband_data_q <= baseband_q >>> bb_rshift;
+        end
+        else begin
+            baseband_data_q <= 'b0;
+        end
+    end
+end
+
+// output data to ports
+assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH];
+assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH];
+
+endmodule
+
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2020/12/08 12:43:46
+// Design Name:
+// Module Name: tb_tx_qpsk
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// module tb_tx_qpsk;
+
+// reg             clk         = 1'b0  ;
+// reg             rst         = 1'b1  ;
+// reg             tx_on       = 1'b1  ;
+// reg     [31:0]  freq_set            ;
+// reg     [ 1:0]  waveform_sel = 2'b00;
+// reg     [ 1:0]  iq_sel      = 2'b11 ;
+// wire    [11:0]  tx_data_i           ;
+// wire    [11:0]  tx_data_q           ;
+// reg     [ 3:0]  bb_rshift   = 5'b0  ;
+
+// tx_qpsk u_tx_qpsk
+// (
+//     .clk            (clk            ),
+//     .rst            (rst            ),
+//     .tx_data_i      (tx_data_i      ),
+//     .tx_data_q      (tx_data_q      ),
+//     .waveform_sel   (waveform_sel   ),
+//     .sweep_on       (1'b0           ),
+//     // .freq_set       (32'd447392426  ),
+//     .freq_set       (32'd0          ),
+//     .iq_sel         (iq_sel         ),
+//     .bb_rshift      (bb_rshift      )
+// );
+
+// initial begin
+//     #102
+//     rst = 1'b0;
+//     // freq_set = 32'd873813333;
+//     // waveform_sel = 2'b00;
+//     // bb_rshift = 5'd0;
+//     // #5000
+//     // bb_rshift = 5'd1;
+//     // #5000
+//     // bb_rshift = 5'd2;
+//     // #5000
+//     // bb_rshift = 5'd3;
+//     // #5000
+//     // bb_rshift = 5'd4;
+//     // #5000
+//     // bb_rshift = 5'd5;
+//     // #5000
+//     // bb_rshift = 5'd6;
+//     // #5000
+//     // bb_rshift = 5'd7;
+//     // #5000
+//     // bb_rshift = 5'd8;
+//     // #5000
+//     // bb_rshift = 5'd9;
+//     // #5000
+//     // bb_rshift = 5'd14;
+//     // #5000
+//     // bb_rshift = 5'd15;
+//     // #5000
+//     // bb_rshift = 5'd16;
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b010;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // func_sel = 3'b100;
+//     // #7777
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b100;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // func_sel = 3'b010;
+//     // #7777
+//     // freq_set = 32'd0;
+//     // func_sel = 3'b010;
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b00;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b01;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b10;
+//     // #7777
+//     // freq_set = 32'd536870912;
+//     // iq_sel = 2'b11;
+// end
+
+// always #5 clk = ~clk;
+
+// // integer i;
+// // integer w_file;
+
+// // initial begin
+// //     w_file = $fopen("D:\\qpsk_josh.txt","w");
+// //     for (i = 0; i <= 35000; i = i + 1) begin
+// //         wait(clk);
+// //         #10;
+// //         $fdisplay(w_file,"%d    %d",$signed(tx_data_i),
+// //                 $signed(tx_data_q));
+// //         if (i == 35000) begin
+// //             $fclose(w_file);
+// //             $stop;
+// //         end
+// //     end
+// // end
+
+// endmodule

projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.xpr

@@ -0,0 +1,990 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="abd9f812433c49eb9e7ef4b1b5b01a41"/>
+    <Option Name="Part" Val="xczu47dr-ffve1156-2-i"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../../adi_library"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="15"/>
+    <Option Name="WTModelSimExportSim" Val="15"/>
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+    <Option Name="WTVcsExportSim" Val="15"/>
+    <Option Name="WTRivieraExportSim" Val="15"/>
+    <Option Name="WTActivehdlExportSim" Val="15"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
+          <Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_clk_wiz_0_0/system_bd_clk_wiz_0_0.xci">
+          <Proxy FileSetName="system_bd_clk_wiz_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_rst_ps8_0_96M_0/system_bd_rst_ps8_0_96M_0.xci">
+          <Proxy FileSetName="system_bd_rst_ps8_0_96M_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
+          <Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_usp_rf_data_converter_0_0/system_bd_usp_rf_data_converter_0_0.xci">
+          <Proxy FileSetName="system_bd_usp_rf_data_converter_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_util_ds_buf_0_0/system_bd_util_ds_buf_0_0.xci">
+          <Proxy FileSetName="system_bd_util_ds_buf_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_util_ds_buf_0_1/system_bd_util_ds_buf_0_1.xci">
+          <Proxy FileSetName="system_bd_util_ds_buf_0_1"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_util_ds_buf_1_0/system_bd_util_ds_buf_1_0.xci">
+          <Proxy FileSetName="system_bd_util_ds_buf_1_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xbar_0/system_bd_xbar_0.xci">
+          <Proxy FileSetName="system_bd_xbar_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xpm_cdc_gen_0_0/system_bd_xpm_cdc_gen_0_0.xci">
+          <Proxy FileSetName="system_bd_xpm_cdc_gen_0_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_xpm_cdc_gen_pl_sysref_0/system_bd_xpm_cdc_gen_pl_sysref_0.xci">
+          <Proxy FileSetName="system_bd_xpm_cdc_gen_pl_sysref_0"/>
+        </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_zynq_ultra_ps_e_0_1/system_bd_zynq_ultra_ps_e_0_1.xci">
+          <Proxy FileSetName="system_bd_zynq_ultra_ps_e_0_1"/>
+        </CompFileExtendedInfo>
+      </File>
+      <File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/tx_qpsk.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/system_top.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/sweep_freq.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_top"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/new/dj_47dr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="system_top"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedInSteps" Val="synth_1"/>
+          <Attr Name="AutoDcp" Val="1"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="cmpy_18x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/cmpy_18x8" RelGenDir="$PGENDIR/cmpy_18x8">
+      <File Path="$PSRCDIR/sources_1/ip/cmpy_18x8/cmpy_18x8.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="cmpy_18x8"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="dds_32b_8b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/dds_32b_8b" RelGenDir="$PGENDIR/dds_32b_8b">
+      <File Path="$PSRCDIR/sources_1/ip/dds_32b_8b/dds_32b_8b.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="dds_32b_8b"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="hop_rom" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hop_rom" RelGenDir="$PGENDIR/hop_rom">
+      <File Path="$PSRCDIR/sources_1/ip/hop_rom/hop_rom.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/hop_rom/hop_rom.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="hop_rom"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="hrc_64_12_025" Type="BlockSrcs" RelSrcDir="$PSRCDIR/hrc_64_12_025" RelGenDir="$PGENDIR/hrc_64_12_025">
+      <File Path="$PSRCDIR/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="hrc_64_12_025"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="ila_adc" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_adc" RelGenDir="$PGENDIR/ila_adc">
+      <File Path="$PSRCDIR/sources_1/ip/ila_adc/ila_adc.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/ila_adc/ila_adc.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ila_adc"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="ila_dac" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_dac" RelGenDir="$PGENDIR/ila_dac">
+      <File Path="$PSRCDIR/sources_1/ip/ila_dac/ila_dac.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/ila_dac/ila_dac.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="ila_dac"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="vio_manual_ctrl" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl" RelGenDir="$PGENDIR/vio_manual_ctrl">
+      <File Path="$PSRCDIR/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../dj_47dr_demo/dj_47dr_demo.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci"/>
+          <Attr Name="ImportTime" Val="1719371236"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="vio_manual_ctrl"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_spi_engine_execution_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_spi_engine_execution_0_0" RelGenDir="$PGENDIR/system_bd_spi_engine_execution_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_spi_engine_execution_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_usp_rf_data_converter_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_usp_rf_data_converter_0_0" RelGenDir="$PGENDIR/system_bd_usp_rf_data_converter_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_usp_rf_data_converter_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xbar_0" RelGenDir="$PGENDIR/system_bd_xbar_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_xbar_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_xpm_cdc_gen_pl_sysref_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xpm_cdc_gen_pl_sysref_0" RelGenDir="$PGENDIR/system_bd_xpm_cdc_gen_pl_sysref_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_xpm_cdc_gen_pl_sysref_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_xpm_cdc_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_xpm_cdc_gen_0_0" RelGenDir="$PGENDIR/system_bd_xpm_cdc_gen_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_xpm_cdc_gen_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_rst_ps8_0_96M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_rst_ps8_0_96M_0" RelGenDir="$PGENDIR/system_bd_rst_ps8_0_96M_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_rst_ps8_0_96M_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_clk_wiz_0_0" RelGenDir="$PGENDIR/system_bd_clk_wiz_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_clk_wiz_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_util_ds_buf_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_0_0" RelGenDir="$PGENDIR/system_bd_util_ds_buf_0_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_util_ds_buf_0_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_util_ds_buf_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_1_0" RelGenDir="$PGENDIR/system_bd_util_ds_buf_1_0">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_util_ds_buf_1_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_util_ds_buf_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_util_ds_buf_0_1" RelGenDir="$PGENDIR/system_bd_util_ds_buf_0_1">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_util_ds_buf_0_1"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="system_bd_zynq_ultra_ps_e_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_zynq_ultra_ps_e_0_1" RelGenDir="$PGENDIR/system_bd_zynq_ultra_ps_e_0_1">
+      <Config>
+        <Option Name="TopModule" Val="system_bd_zynq_ultra_ps_e_0_1"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu47dr-ffve1156-2-i" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="cmpy_18x8_synth_1" Type="Ft3:Synth" SrcSet="cmpy_18x8" Part="xczu47dr-ffve1156-2-i" ConstrsSet="cmpy_18x8" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_18x8_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="dds_32b_8b_synth_1" Type="Ft3:Synth" SrcSet="dds_32b_8b" Part="xczu47dr-ffve1156-2-i" ConstrsSet="dds_32b_8b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/dds_32b_8b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_synth_1" Type="Ft3:Synth" SrcSet="hop_rom" Part="xczu47dr-ffve1156-2-i" ConstrsSet="hop_rom" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hop_rom_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hrc_64_12_025_synth_1" Type="Ft3:Synth" SrcSet="hrc_64_12_025" Part="xczu47dr-ffve1156-2-i" ConstrsSet="hrc_64_12_025" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/hrc_64_12_025_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ila_adc_synth_1" Type="Ft3:Synth" SrcSet="ila_adc" Part="xczu47dr-ffve1156-2-i" ConstrsSet="ila_adc" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_adc_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_adc_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_adc_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ila_dac_synth_1" Type="Ft3:Synth" SrcSet="ila_dac" Part="xczu47dr-ffve1156-2-i" ConstrsSet="ila_dac" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_dac_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_dac_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_dac_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xczu47dr-ffve1156-2-i" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_spi_engine_execution_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
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+      </Strategy>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" ParallelReportGen="true">
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+      <RQSFiles/>
+    </Run>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+      </Strategy>
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+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+    </Run>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
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+    </Run>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+    </Run>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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+    </Run>
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+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+    </Run>
+    <Run Id="system_bd_zynq_ultra_ps_e_0_1_synth_1" Type="Ft3:Synth" SrcSet="system_bd_zynq_ultra_ps_e_0_1" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_zynq_ultra_ps_e_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_zynq_ultra_ps_e_0_1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_zynq_ultra_ps_e_0_1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_zynq_ultra_ps_e_0_1_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+    <Run Id="cmpy_18x8_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="cmpy_18x8" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_18x8_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_18x8_impl_1" ParallelReportGen="true">
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="dds_32b_8b_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="dds_32b_8b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="dds_32b_8b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/dds_32b_8b_impl_1" ParallelReportGen="true">
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="hop_rom_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="hop_rom" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hop_rom_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hop_rom_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+    <Run Id="hrc_64_12_025_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="hrc_64_12_025" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="hrc_64_12_025_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/hrc_64_12_025_impl_1" ParallelReportGen="true">
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ila_adc_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="ila_adc" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_adc_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_adc_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_adc_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="ila_dac_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="ila_dac" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_dac_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_dac_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_dac_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+    <Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_spi_engine_execution_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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+        <Step Id="opt_design"/>
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+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_usp_rf_data_converter_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_usp_rf_data_converter_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_usp_rf_data_converter_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_usp_rf_data_converter_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_usp_rf_data_converter_0_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_xpm_cdc_gen_pl_sysref_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_xpm_cdc_gen_pl_sysref_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xpm_cdc_gen_pl_sysref_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xpm_cdc_gen_pl_sysref_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xpm_cdc_gen_pl_sysref_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_xpm_cdc_gen_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_xpm_cdc_gen_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xpm_cdc_gen_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xpm_cdc_gen_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xpm_cdc_gen_0_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_rst_ps8_0_96M_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_rst_ps8_0_96M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_ps8_0_96M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps8_0_96M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps8_0_96M_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_clk_wiz_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_0_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_util_ds_buf_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_util_ds_buf_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_util_ds_buf_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_0_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="system_bd_util_ds_buf_1_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_util_ds_buf_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_util_ds_buf_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_1_0_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+    <Run Id="system_bd_util_ds_buf_0_1_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_util_ds_buf_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_util_ds_buf_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_util_ds_buf_0_1_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
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+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+    <Run Id="system_bd_zynq_ultra_ps_e_0_1_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_zynq_ultra_ps_e_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_zynq_ultra_ps_e_0_1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_zynq_ultra_ps_e_0_1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_zynq_ultra_ps_e_0_1_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
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+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
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+      <Dashboard Name="default_dashboard">
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+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/.cproject

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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/.gitignore

@@ -0,0 +1,2 @@
+/Debug/
+/Release/

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/.project

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>dj_47dr_basic</name>
+	<comment>Created by Vitis v2024.1</comment>
+	<projects>
+		<project>dj_47dr_platform</project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdx.sdk.core.SdkProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/_ide/hwspec.checksum

@@ -0,0 +1 @@
+2311224066

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/dj_47dr_basic.prj

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="ASCII"?>
+<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dj_47dr_basic" location="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic" platform="/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/dj_47dr_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dj_47dr_basic_system" sysConfig="dj_47dr_platform" runtime="cpp" cpu="standalone_psu_cortexa53_0" cpuInstance="psu_cortexa53_0" os="standalone" mssSignature="c6670d350bc5ad3b0c7e7d49c8d56f6d">
+  <configuration name="Debug" id="xilinx.gnu.arm.a53.exe.debug.1087926654">
+    <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
+    <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
+  </configuration>
+  <configuration name="Release" id="xilinx.gnu.arm.a53.exe.release.424068119" dirty="true">
+    <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
+  </configuration>
+  <template appTemplateName="empty_application"/>
+</sdkproject:SdkProject>

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/README.md

@@ -0,0 +1,30 @@
+# README.md
+
+> Vivado Project Name: dj_47dr_lmx
+>
+> Vitis Project Name: dj_47dr_basic
+>
+> Board: RFSOC_47DR_Z7045
+>
+> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmx2594(u67), lmx2594(u68)
+>
+> Date: 2024/07/05
+>
+> Archiver: Josh Gao
+
+1. 注意事项
+
+   本工程启用了动态 DDR 配置，依赖于 FSBL 启动，在启动时 FSBL 会使用 I2C 读取 DDR 的 SPD EEPROM 获得 DDR 参数，并初始化 DDR 控制器。
+
+   由于原理图与 Xilinx 开发板 I2C Mux Slave 连接不一致，FSBL 已将 I2C Mux 的 Slave 选择改为 `0x04`。若重新建立 PS 工程，注意修改 FSBL，否则可能无法正常启动。
+
+2. 实现的功能
+
+   - 配置了 LMK04828，使用 10 MHz 输入时钟和 122.88 MHz VCXO 完成配置，PLL2 锁定，输出时钟频率为 245.76 MHz。
+   - 配置了两片 LMK2594，RF 部分使用外部采样时钟，采样率为 4.9152 Gbps。
+   - 初始化了 RF Data Converter，自发自收测试 ch5 发 ch5 收正常，信号功率和 EVM 等未测量。
+   - 降低 SPI 速率后 LMX2594 回读正常。
+
+3. 存在的问题
+
+   - LMK04828 PLL1 锁定时间较长（约 1 分钟），单独配置 LMK04828 时同样存在该问题。

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/adc/ad9694/ad9694.c

@@ -0,0 +1,128 @@
+/***************************************************************************//**
+ * @file ad9694.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include "ad9694.h"
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief ad9694_read
+ *******************************************************************************/
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+	
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_write
+ *******************************************************************************/
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9694_init
+ *******************************************************************************/
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct ad9694_dev *dev;
+
+	dev = (struct ad9694_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by ad9694_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t ad9694_remove(struct ad9694_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/adc/ad9694/ad9694.h

@@ -0,0 +1,231 @@
+/***************************************************************************//**
+ * @file ad9694.h
+ * @brief Header file of AD9694 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef AD9694_H_
+#define AD9694_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A						0x0000
+#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B						0x0001
+#define AD9694_REG_CH_MAP_CHIP_CONF								0x0002
+#define AD9694_REG_PAIR_MAP_CHIP_TYPE							0x0003
+#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB							0x0004
+#define AD9694_REG_PAIR_MAP_CHIP_GRADE							0x0006
+#define AD9694_REG_PAIR_MAP_DEV_INDEX							0x0008
+#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX						0x0009
+#define AD9694_REG_PAIR_MAP_SCRATCH_PAD							0x000A
+#define AD9694_REG_PAIR_MAP_SPI_REVISION						0x000B
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB						0x000C
+#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB						0x000D
+#define AD9694_REG_CH_MAP_CHIP_PD_PIN							0x003F
+#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1						0x0040
+#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL						0x0108
+#define AD9694_REG_CH_MAP_CLK_DIV_PHASE							0x0109
+#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL					0x010A
+#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL						0x0110
+#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY					0x0111
+#define AD9694_REG_CH_MAP_CLK_FINE_DELAY						0x0112
+#define AD9694_REG_CLK_DETN_CTRL								0x011A
+#define AD9694_REG_PAIR_MAP_CLK_STAT							0x011B
+#define AD9694_REG_CLK_DCS_CTRL_1								0x011C
+#define AD9694_REG_CLK_DCS_CTRL_2								0x011E
+#define AD9694_REG_CLK_DCS_CTRL_3								0x011F
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1						0x0120
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2						0x0121
+#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4						0x0123
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1						0x0128
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2						0x0129
+#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3						0x012A
+#define AD9694_REG_PAIR_MAP_CHIP_SYNC							0x01FF
+#define AD9694_REG_PAIR_MAP_CHIP_MODE							0x0200
+#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO						0x0201
+#define AD9694_REG_CH_MAP_CUSTOM_OFFSET							0x0228
+#define AD9694_REG_CH_MAP_FD_CTRL								0x0245
+#define AD9694_REG_CH_MAP_FD_UT_LSB								0x0247
+#define AD9694_REG_CH_MAP_FD_UT_MSB								0x0248
+#define AD9694_REG_CH_MAP_FD_LT_LSB								0x0249
+#define AD9694_REG_CH_MAP_FD_LT_MSB								0x024A
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB						0x024B
+#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB						0x024C
+#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL					0x026F
+#define AD9694_REG_CH_MAP_SIG_MON_CTRL							0x0270
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0						0x0271
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1						0x0272
+#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2						0x0273
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL						0x0274
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_0						0x0275
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_1						0x0276
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_2						0x0277
+#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT				0x0278
+#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL			0x0279
+#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL				0x027A
+#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL						0x0300
+#define AD9694_REG_PAIR_MAP_DDC_0_CTRL							0x0310
+#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL						0x0311
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0					0x0314
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1					0x0315
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2					0x0316
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3					0x0317
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4					0x0318
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5					0x031A
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0				0x031D
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1				0x031E
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2				0x031F
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3				0x0320
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4				0x0321
+#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5				0x0322
+#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE					0x0327
+#define AD9694_REG_PAIR_MAP_DDC_1_CTRL							0x0330
+#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL						0x0331
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0					0x0334
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1					0x0335
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2					0x0336
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3					0x0337
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4					0x0338
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5					0x033A
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0				0x033D
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1				0x033E
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2				0x033F
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3				0x0340
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4				0x0341
+#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5				0x0342
+#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE					0x0347
+#define AD9694_REG_CH_MAP_TEST_MODE_CTRL						0x0550
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB					0x0551
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB					0x0552
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB					0x0553
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB					0x0554
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB					0x0555
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB					0x0556
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB					0x0557
+#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB					0x0558
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0					0x0559
+#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1					0x055A
+#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE					0x0561
+#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL						0x0564
+#define AD9694_REG_JESD204B_MAP_PLL_CTRL						0x056E
+#define AD9694_REG_JESD204B_MAP_PLL_STAT						0x056F
+#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF					0x0570
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1					0x0571
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2					0x0572
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3					0x0573
+#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4					0x0574
+#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET					0x0578
+#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF					0x0580
+#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF					0x0581
+#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF					0x0583
+#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF					0x0585
+#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF					0x058B
+#define AD9694_REG_JESD204B_MAP_JTX_F_CONF						0x058C
+#define AD9694_REG_JESD204B_MAP_JTX_K_CONF						0x058D
+#define AD9694_REG_JESD204B_MAP_JTX_M_CONF						0x058E
+#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF					0x058F
+#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF				0x0590
+#define AD9694_REG_JESD204B_MAP_JTX_S_CONF						0x0591
+#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF					0x0592
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF				0x05A0
+#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF				0x05A1
+#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD					0x05B0
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1				0x05B2
+#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2				0x05B3
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0					0x05C0
+#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1					0x05C1
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0					0x05C4
+#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1					0x05C6
+#define AD9694_REG_LARGE_DITHER_CTRL							0x0922
+#define AD9694_REG_PLL_CAL										0x1222
+#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST					0x1228
+#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL						0x1262
+#define AD9694_REG_DC_OFFSET_CAL_CTRL							0x0701
+#define AD9694_REG_DC_OFFSET_CAL_CTRL_2							0x073B
+#define AD9694_REG_PAIR_MAP_VREF_CTRL							0x18A6
+#define AD9694_REG_EXT_VCM_BUF_CTRL_1							0x18E0
+#define AD9694_REG_EXT_VCM_BUF_CTRL_2							0x18E1
+#define AD9694_REG_EXT_VCM_BUF_CTRL_3							0x18E2
+#define AD9694_REG_EXT_VCM_BUF_CTRL								0x18E3
+#define AD9694_REG_TEMP_DIODE_EXPORT							0x18E6
+#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL						0x1908
+#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE					0x1910
+#define AD9694_REG_CH_MAP_BUF_CTRL_1							0x1A4C
+#define AD9694_REG_CH_MAP_BUF_CTRL_2							0x1A4D
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct ad9694_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct ad9694_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct ad9694_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t ad9694_read(struct ad9694_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t ad9694_write(struct ad9694_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t ad9694_init(struct ad9694_dev **device,
+		     const struct ad9694_init_param *init_param);
+
+int32_t ad9694_remove(struct ad9694_dev *dev);
+
+#endif

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/gpio.c

@@ -0,0 +1,184 @@
+/***************************************************************************//**
+ *   @file   gpio.c
+ *   @brief  Implementation of the GPIO Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/gpio.h"
+#include "../../include/error.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->gpio_ops_get(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param)
+{
+	if (!param || (param->number == -1)) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_remove(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_direction_input(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_direction_output(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_get_direction(desc, direction);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_set_value(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_get_value(desc, value);
+	else
+		return SUCCESS;
+}

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/irq.c

@@ -0,0 +1,153 @@
+/***************************************************************************//**
+ *   @file   irq.c
+ *   @brief  Implementation of the IRQ Interface
+ *   @author Andrei Porumb ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/irq.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc)
+{
+	return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->unregister(desc, irq_id);
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_enable(desc);
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_disable(desc);
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig)
+{
+	if(desc->platform_ops->trigger_level_set)
+		return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
+	else
+		return ENOSYS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->enable(desc, irq_id);
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->disable(desc, irq_id);
+}

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/api/spi.c

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ *   @file   spi.c
+ *   @brief  Implementation of the SPI Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include "../../include/spi.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number)
+{
+	return desc->platform_ops->write_and_read(desc, data, bytes_number);
+}
+
+/**
+ * @brief Write and read data to/from SPI in 3 wire mode.
+ * @param desc - The SPI descriptor.
+ * @param write_data - The buffer with the transmitted data.
+ * @param read_data - The buffer with the received data.
+ * @param write_bytes_number - Number of bytes to write.
+ * @param read_bytes_number - Number of bytes to read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number)
+{
+	int ret;
+	if(desc->platform_ops->write_and_read_3wire != NULL){
+		return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
+			write_bytes_number, read_bytes_number);
+	}
+	else{
+		return FAILURE;
+	}
+}
+
+
+/**
+ * @brief  Iterate over head list and send all spi messages
+ * @param desc - The SPI descriptor.
+ * @param msgs - Array of messages.
+ * @param len - Number of messages in the array.
+ * @return SUCCESS in case of success, negativ error code otherwise.
+ */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
+{
+	int32_t  ret;
+	uint32_t i;
+
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (desc->platform_ops->transfer)
+		return desc->platform_ops->transfer(desc, msgs, len);
+
+	for (i = 0; i < len; i++) {
+		if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
+			return -EINVAL;
+		ret = spi_write_and_read(desc, msgs[i].rx_buff,
+					 msgs[i].bytes_number);
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
+
+	return SUCCESS;
+}

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c

@@ -0,0 +1,328 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.c
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+#include "../axi_dmac/axi_dmac.h"
+
+/***************************************************************************//**
+ * @brief dma_isr
+*******************************************************************************/
+void axi_dmac_default_isr(void *instance)
+{
+	struct axi_dmac *dmac = (struct axi_dmac *)instance;
+	uint32_t remaining_size, burst_size;
+	uint32_t reg_val;
+
+	/* Get interrupt sources and clear interrupts. */
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
+		remaining_size = dmac->big_transfer.size -
+				 dmac->big_transfer.size_done;
+		burst_size = (remaining_size <= dmac->transfer_max_size) ?
+			     remaining_size : dmac->transfer_max_size;
+
+		dmac->big_transfer.size_done += burst_size;
+		dmac->big_transfer.address += burst_size;
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return; // Other directions are not supported yet
+		}
+		/* The current transfer was started and a new one is queued. */
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       burst_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+	}
+	if (reg_val & AXI_DMAC_IRQ_EOT) {
+		dmac->big_transfer.transfer_done = true;
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+	}
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_read
+ *******************************************************************************/
+int32_t axi_dmac_read(struct axi_dmac *dmac,
+		      uint32_t reg_addr,
+		      uint32_t *reg_data)
+{
+	axi_io_read(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_write
+ *******************************************************************************/
+int32_t axi_dmac_write(struct axi_dmac *dmac,
+		       uint32_t reg_addr,
+		       uint32_t reg_data)
+{
+	axi_io_write(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer_nonblock
+ *******************************************************************************/
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size)
+{
+	uint32_t reg_val;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, &reg_val);
+	if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+	}
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	if (!(reg_val & 1)) {
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return FAILURE; // Other directions are not supported yet
+		}
+		if ((size - 1) > dmac->transfer_max_size) {
+			dmac->big_transfer.address = address;
+			dmac->big_transfer.size = size - 1;
+			dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       dmac->transfer_max_size);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		} else {
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       size - 1);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		}
+	} else {
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_is_transfer_ready
+ *******************************************************************************/
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
+{
+	*rdy = dmac->big_transfer.transfer_done;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer
+ *******************************************************************************/
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size)
+{
+	uint32_t transfer_id;
+	uint32_t reg_val;
+	uint32_t timeout = 0;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	switch (dmac->direction) {
+	case DMA_DEV_TO_MEM:
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+		break;
+	case DMA_MEM_TO_DEV:
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+		break;
+	default:
+		return FAILURE; // Other directions are not supported yet
+	}
+
+	if ((size - 1) > dmac->transfer_max_size) {
+		dmac->big_transfer.address = address;
+		dmac->big_transfer.size = size - 1;
+		dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       dmac->transfer_max_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+		while(!dmac->big_transfer.transfer_done) {
+			timeout++;
+			if (timeout == UINT32_MAX)
+				return FAILURE;
+		}
+
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+
+		return SUCCESS;
+	}
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
+	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+	if (dmac->flags & DMA_CYCLIC)
+		return SUCCESS;
+
+	/* Wait until the new transfer is queued. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	} while(reg_val == 1);
+
+	/* Wait until the current transfer is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+		if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+			break;
+	} while(!dmac->big_transfer.transfer_done);
+	if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	/* Wait until the transfer with the ID transfer_id is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, &reg_val);
+	} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_init
+ *******************************************************************************/
+int32_t axi_dmac_init(struct axi_dmac **dmac_core,
+		      const struct axi_dmac_init *init)
+{
+	struct axi_dmac *dmac;
+
+	dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
+	if (!dmac)
+		return FAILURE;
+
+	dmac->name = init->name;
+	dmac->base = init->base;
+	dmac->direction = init->direction;
+	dmac->flags = init->flags;
+	dmac->transfer_max_size = -1;
+	dmac->big_transfer.address = 0;
+	dmac->big_transfer.size = 0;
+	dmac->big_transfer.size_done = 0;
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
+	axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
+
+	*dmac_core = dmac;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_remove
+ *******************************************************************************/
+int32_t axi_dmac_remove(struct axi_dmac *dmac)
+{
+	if(!dmac)
+		return FAILURE;
+
+	free(dmac);
+
+	return SUCCESS;
+}

projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h

@@ -0,0 +1,124 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.h
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef AXI_DMAC_H_
+#define AXI_DMAC_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AXI_DMAC_REG_IRQ_MASK		0x80
+#define AXI_DMAC_REG_IRQ_PENDING	0x84
+#define AXI_DMAC_IRQ_SOT			BIT(0)
+#define AXI_DMAC_IRQ_EOT			BIT(1)
+
+#define AXI_DMAC_REG_CTRL			0x400
+#define AXI_DMAC_CTRL_ENABLE		BIT(0)
+#define AXI_DMAC_CTRL_PAUSE			BIT(1)
+
+#define AXI_DMAC_REG_TRANSFER_ID	0x404
+#define AXI_DMAC_REG_START_TRANSFER	0x408
+#define AXI_DMAC_REG_FLAGS			0x40c
+#define AXI_DMAC_REG_DEST_ADDRESS	0x410
+#define AXI_DMAC_REG_SRC_ADDRESS	0x414
+#define AXI_DMAC_REG_X_LENGTH		0x418
+#define AXI_DMAC_REG_Y_LENGTH		0x41c
+#define AXI_DMAC_REG_DEST_STRIDE	0x420
+#define AXI_DMAC_REG_SRC_STRIDE		0x424
+#define AXI_DMAC_REG_TRANSFER_DONE	0x428
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+enum dma_direction {
+	DMA_DEV_TO_MEM,
+	DMA_MEM_TO_DEV
+};
+
+enum dma_flags {
+	DMA_CYCLIC = 1,
+	DMA_LAST = 2
+};
+
+struct axi_dma_transfer {
+	uint32_t size;
+	uint32_t address;
+	uint32_t size_done;
+	volatile bool transfer_done;
+};
+
+struct axi_dmac {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+	uint32_t transfer_max_size;
+	volatile struct axi_dma_transfer big_transfer;
+};
+
+struct axi_dmac_init {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+void axi_dmac_default_isr(void *instance);
+int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
+		      uint32_t *reg_data);
+int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
+		       uint32_t reg_data);
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size);
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size);
+int32_t axi_dmac_init(struct axi_dmac **adc_core,
+		      const struct axi_dmac_init *init);
+int32_t axi_dmac_remove(struct axi_dmac *dmac);
+
+#endif