refactor(recveiver): replace old agc & frame-sync

hdl/ad9361_mgc_pin_ctrl.v

@@ -21,7 +21,7 @@ module ad9361_mgc_pin_ctrl (
     input       [11:0] rx_data_q,
     // this port is from zynq to ad9361
     output wire [ 3:0] ad9361_ctrl_in,
-    output reg         flag_mgc_done
+    output reg         flag_mgc_done // active high level signal
 
 );