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refactor(recviver): simulation pass for ila data

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ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
56 changed files with 5822 additions and 1186 deletions
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hdl/LDPC_TopManage_2.v
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`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/18 23:18:07
// Design Name:
// Module Name: LDPC_TopManage_2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LDPC_TopManage_2 #(
parameter WIDTH = 4'd8
) (
input clk, //工作时钟,100MHz
input Rst, //同步复位信号,高有效
input FrameSync_TM, //帧同步标志,高脉冲
input Nd_TM, //译码输入数据有效标志,高有效
input [WIDTH-1:0] Din_TM, //译码输入数据,软信息
//A
output FrameSync_A_TM, //帧同步标志,高脉冲
output Nd_A_TM, //译码输入数据有效标志,高有效
output [WIDTH-1:0] Din_A_TM, //译码输入数据,软信息
//B
output FrameSync_B_TM, //帧同步标志,高脉冲
output Nd_B_TM, //译码输入数据有效标志,高有效
output [WIDTH-1:0] Din_B_TM, //译码输入数据,软信息
// flag A
input LDPC_SyncOut_A_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
input Rdy_A_TM, //译码输出信号有效标志,高有效
input [ 0:0] LDPC_Dout_A_TM, //译码输出信号
input [ 8:0] good_frames_A_TM, //译码好帧计数
input [ 8:0] bad_frames_A_TM, //译码坏帧计数
input [ 8:0] total_frames_A_TM, //译码总帧数计数
//flag B
input LDPC_SyncOut_B_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
input Rdy_B_TM, //译码输出信号有效标志,高有效
input [ 0:0] LDPC_Dout_B_TM, //译码输出信号
input [ 8:0] good_frames_B_TM, //译码好帧计数
input [ 8:0] bad_frames_B_TM, //译码坏帧计数
input [ 8:0] total_frames_B_TM, //译码总帧数计数
//result
output LDPC_SyncOut_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
output Rdy_TM, //译码输出信号有效标志,高有效
output [ 0:0] LDPC_Dout_TM, //译码输出信号
output [ 8:0] good_frames_TM, //译码好帧计数
output [ 8:0] bad_frames_TM, //译码坏帧计数
output [ 8:0] total_frames_TM //译码总帧数计数
);
reg FrameSync_TM_reg0, FrameSync_TM_reg1;
reg Nd_TM_reg0, Nd_TM_reg1;
reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;
//******输入过程控制
always @(posedge clk) begin //接收数据缓存过程
FrameSync_TM_reg0 <= FrameSync_TM;
FrameSync_TM_reg1 <= FrameSync_TM_reg0;
Nd_TM_reg0 <= Nd_TM;
Nd_TM_reg1 <= Nd_TM_reg0;
Din_TM_reg0 <= Din_TM;
Din_TM_reg1 <= Din_TM_reg0;
end
reg [0:0] flag_switch_in = 1'b1;
always @(posedge clk) begin //输入乒乓控制过程
if (Rst) begin
flag_switch_in <= 1'd1;
end
else begin
if (FrameSync_TM) begin
flag_switch_in <= ~flag_switch_in;
end
else flag_switch_in <= flag_switch_in;
end
end
assign FrameSync_A_TM = (flag_switch_in == 1'b0) ? FrameSync_TM_reg1 : 1'b0;
assign Nd_A_TM = (flag_switch_in == 1'b0) ? Nd_TM_reg1 : 1'b0;
assign Din_A_TM = (flag_switch_in == 1'b0) ? Din_TM_reg1 : 8'd0;
assign FrameSync_B_TM = (flag_switch_in == 1'b1) ? FrameSync_TM_reg1 : 1'b0;
assign Nd_B_TM = (flag_switch_in == 1'b1) ? Nd_TM_reg1 : 1'b0;
assign Din_B_TM = (flag_switch_in == 1'b1) ? Din_TM_reg1 : 8'd0;
reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;
reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;
reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;
reg [8:0] good_frames_A_TM_reg0, good_frames_A_TM_reg1;
reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;
reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;
reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;
reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;
reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;
reg [8:0] good_frames_B_TM_reg0, good_frames_B_TM_reg1;
reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;
reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;
//******输入过程控制
always @(posedge clk) begin //输出数据缓存过程
if (Rst) begin
LDPC_SyncOut_A_TM_reg0 <= 1'b0;
LDPC_SyncOut_A_TM_reg1 <= 1'b0;
Rdy_A_TM_reg0 <= 1'b0;
Rdy_A_TM_reg1 <= 1'b0;
LDPC_Dout_A_TM_reg0 <= 1'b0;
LDPC_Dout_A_TM_reg1 <= 1'b0;
good_frames_A_TM_reg0 <= 9'd0;
good_frames_A_TM_reg1 <= 9'd0;
bad_frames_A_TM_reg0 <= 9'd0;
bad_frames_A_TM_reg1 <= 9'd0;
total_frames_A_TM_reg0 <= 9'd0;
total_frames_A_TM_reg1 <= 9'd0;
LDPC_SyncOut_B_TM_reg0 <= 1'b0;
LDPC_SyncOut_B_TM_reg1 <= 1'b0;
Rdy_B_TM_reg0 <= 1'b0;
Rdy_B_TM_reg1 <= 1'b0;
LDPC_Dout_B_TM_reg0 <= 1'b0;
LDPC_Dout_B_TM_reg1 <= 1'b0;
good_frames_B_TM_reg0 <= 9'd0;
good_frames_B_TM_reg1 <= 9'd0;
bad_frames_B_TM_reg0 <= 9'd0;
bad_frames_B_TM_reg1 <= 9'd0;
total_frames_B_TM_reg0 <= 9'd0;
total_frames_B_TM_reg1 <= 9'd0;
end
else begin
LDPC_SyncOut_A_TM_reg0 <= LDPC_SyncOut_A_TM;
LDPC_SyncOut_A_TM_reg1 <= LDPC_SyncOut_A_TM_reg0;
Rdy_A_TM_reg0 <= Rdy_A_TM;
Rdy_A_TM_reg1 <= Rdy_A_TM_reg0;
LDPC_Dout_A_TM_reg0 <= LDPC_Dout_A_TM;
LDPC_Dout_A_TM_reg1 <= LDPC_Dout_A_TM_reg0;
good_frames_A_TM_reg0 <= good_frames_A_TM;
good_frames_A_TM_reg1 <= good_frames_A_TM_reg0;
bad_frames_A_TM_reg0 <= bad_frames_A_TM;
bad_frames_A_TM_reg1 <= bad_frames_A_TM_reg0;
total_frames_A_TM_reg0 <= total_frames_A_TM;
total_frames_A_TM_reg1 <= total_frames_A_TM_reg0;
LDPC_SyncOut_B_TM_reg0 <= LDPC_SyncOut_B_TM;
LDPC_SyncOut_B_TM_reg1 <= LDPC_SyncOut_B_TM_reg0;
Rdy_B_TM_reg0 <= Rdy_B_TM;
Rdy_B_TM_reg1 <= Rdy_B_TM_reg0;
LDPC_Dout_B_TM_reg0 <= LDPC_Dout_B_TM;
LDPC_Dout_B_TM_reg1 <= LDPC_Dout_B_TM_reg0;
good_frames_B_TM_reg0 <= good_frames_B_TM;
good_frames_B_TM_reg1 <= good_frames_B_TM_reg0;
bad_frames_B_TM_reg0 <= bad_frames_B_TM;
bad_frames_B_TM_reg1 <= bad_frames_B_TM_reg0;
total_frames_B_TM_reg0 <= total_frames_B_TM;
total_frames_B_TM_reg1 <= total_frames_B_TM_reg0;
end
end
reg [0:0] flag_switch_out = 1'b1;
always @(posedge clk) begin //输出乒乓控制过程
if (Rst) begin
flag_switch_out <= 1'd1;
end
else begin
if (LDPC_SyncOut_A_TM || LDPC_SyncOut_B_TM) flag_switch_out <= ~flag_switch_out;
else flag_switch_out <= flag_switch_out;
end
end
assign LDPC_SyncOut_TM = (flag_switch_out == 1'b0) ? LDPC_SyncOut_A_TM_reg1 : LDPC_SyncOut_B_TM_reg1;
assign Rdy_TM = (flag_switch_out == 1'b0) ? Rdy_A_TM_reg1 : Rdy_B_TM_reg1;
assign LDPC_Dout_TM = (flag_switch_out == 1'b0) ? LDPC_Dout_A_TM_reg1 : LDPC_Dout_B_TM_reg1;
assign good_frames_TM = good_frames_B_TM_reg1 + good_frames_A_TM_reg1;
assign bad_frames_TM = bad_frames_B_TM_reg1 + bad_frames_A_TM_reg1;
assign total_frames_TM = total_frames_B_TM_reg1 + total_frames_A_TM_reg1;
endmodule