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refactor(recviver): simulation pass for ila data

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ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
56 changed files with 5822 additions and 1186 deletions
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hdl/OUT_PRO.v
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`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/18 23:18:07
// Design Name:
// Module Name: OUT_PRO
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module OUT_PRO
#(
parameter OUT_ONLY_INFORMATION = 1'd0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
)
(
input clk,
input rst_OUT,
input start_OUT,
input [0:0] DR_dout_01,
input [0:0] DR_dout_02,
input [0:0] DR_dout_03,
input [0:0] DR_dout_04,
output reg [8:0] DR_addr_rd_01=9'd511,
output reg [8:0] DR_addr_rd_02=9'd511,
output reg [8:0] DR_addr_rd_03=9'd511,
output reg [8:0] DR_addr_rd_04=9'd511,
output ldpc_syncout_OUT,
output rdy_OUT,
output reg [0:0] ldpc_dout_OUT=1'd0
);
reg [11:0] cnt_OUT=12'd0;
reg flag_OUT=1'd0;
always @ (posedge clk) begin//产生该模块的计数基准
if(rst_OUT) begin
cnt_OUT <= 12'd0;
flag_OUT <= 1'b0;
end else begin
if(start_OUT) begin
flag_OUT <= 1'b1;
cnt_OUT <= 12'd0;
end else begin
if(flag_OUT) begin
if(cnt_OUT<12'd2080)begin
flag_OUT <= flag_OUT;
cnt_OUT <= cnt_OUT + 12'd1;
end else begin
cnt_OUT <= cnt_OUT;
flag_OUT <= 1'b0;
end
end else begin
cnt_OUT <= cnt_OUT;
end
end
end
end
// 控制DR的读地址
always @ (posedge clk) begin
if (rst_OUT) begin
DR_addr_rd_01 <= 9'd511;
DR_addr_rd_02 <= 9'd511;
DR_addr_rd_03 <= 9'd511;
DR_addr_rd_04 <= 9'd511;
end else begin
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
else begin
DR_addr_rd_01 <= 9'd511;
DR_addr_rd_02 <= 9'd511;
end
end else begin // 输出整个码字
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
else if (cnt_OUT >= 12'd1025 && cnt_OUT <= 12'd1536)
DR_addr_rd_03 <= DR_addr_rd_03 + 9'd1;
else if (cnt_OUT >= 12'd1537 && cnt_OUT <= 12'd2048)
DR_addr_rd_04 <= DR_addr_rd_04 + 9'd1;
else begin
DR_addr_rd_01 <= 9'd511;
DR_addr_rd_02 <= 9'd511;
DR_addr_rd_03 <= 9'd511;
DR_addr_rd_04 <= 9'd511;
end
end
end
end
parameter DELAY_OUT = 4'd6;
// 控制DR的输出数据到译码器的输出
always @ (posedge clk) begin
if (rst_OUT) begin
ldpc_dout_OUT <= 1'd0;
end else begin
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_01;
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_02;
else
ldpc_dout_OUT <= 1'd0;
end else begin // 输出整个码字
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_01;
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_02;
else if (cnt_OUT >= 12'd1025 + DELAY_OUT && cnt_OUT <= 12'd1536 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_03;
else if (cnt_OUT >= 12'd1537 + DELAY_OUT && cnt_OUT <= 12'd2048 + DELAY_OUT)
ldpc_dout_OUT <= DR_dout_04;
else
ldpc_dout_OUT <= 1'd0;
end
end
end
// 产生状态指示标志
assign ldpc_syncout_OUT = (cnt_OUT == 12'd1 + DELAY_OUT) ? 1'd1 : 1'd0;
assign rdy_OUT = (OUT_ONLY_INFORMATION == 1'd0) ?
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd2048 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0) :
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd1024 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0);
endmodule