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refactor(recviver): simulation pass for ila data

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ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
56 changed files with 5822 additions and 1186 deletions
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hdl/RecvTop.v
+178 -253
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@@ -1,4 +1,4 @@
`timescale 1ns / 1ps
`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
@@ -19,104 +19,103 @@
//
//////////////////////////////////////////////////////////////////////////////////
module RecvTop (
input clk,
input clk2,
input clk_60M_mac,
input clk_4x,
input rst,
input rst2,
input [11:0] dini,
input [11:0] dinq,
output [3:0] ad9361_ctrl_in,
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
//debug
//trigger
output rst_TimeSync,
output rst_freq,
output DAGC_rdy,
output framesync, //帧同步峰
output framesync_delay, //帧同步峰，与频率补偿输出对应
output framesync_tsync, //帧同步标志，与TSync输出对应
output IntpARdy, //TSync输出nd
output nd_SC_FDE_dout, //SC_FDE输出nd
output framerdy, //一帧译码结果存储完毕标志
output reg flag_bercount = 1'd0,
output reg flag_badframe = 1'd0,
output reg flag_ber = 1'd0,
//各模块输出，星座图
output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出
output [11:0] dc_removal_dout_q,
output [ 9:0] matchfilterout_i, //MF输出
output [ 9:0] matchfilterout_q,
output [ 9:0] DAGC_out_i, //DAGC输出
output [ 9:0] DAGC_out_q,
output [ 9:0] freqdataout_i, //频率补偿输出
output [ 9:0] freqdataout_q,
output [ 9:0] IntpOuti, //TSync输出
output [ 9:0] IntpOutq,
output [ 9:0] SC_FDE_douti, //SC_FDE输出
output [ 9:0] SC_FDE_doutq,
//MGC_adaptation
output [24:0] mean_temp,
output [12:0] acc_mean,
output [ 4:0] state_mgc,
output mgc1_rdy,
output flag_state_mgc,
output [ 2:0] state_rst,
output flag_overflow,
output flag_small,
//DC
output [11:0] dc_value_i,
output [11:0] dc_value_q,
output flag_dc,
//DAGC
output flag_agch,
output flag_agcl,
output flag_agc_power,
output [12:0] agc_ref,
output [12:0] agc_check,
//power test
output flag_powerabsh,
output flag_powerabsl,
output flag_abs_power,
output [10:0] abs_ref,
output [10:0] abs_check,
//TSync
output [ 3:0] flag_clk_4bit, //位同步选取通道结果
//SC_FDE,溢出标志
output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
output reg flagoverflow = 1'd0, //总溢出标志
output Pilot_rdy_hide1_d1,
input clk,
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
// phy wave
input [11:0] dini,
input [11:0] dinq,
// mgc control
output [ 3:0] ad9361_ctrl_in,
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
// stop signal
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
// mac frame header
output [63:0] recvNetData,
output recvNetDataNd,
input debug_loss
output recvNetDataNd
);
reg [7:0] cnt_mgc_delay;
wire mgc_start;
wire flag_mgc_done; // level flag
wire flag_mgc_done_4x; // level flag
wire rst_TimeSync;
wire rst_freq;
wire DAGC_rdy;
wire framesync; //帧同步峰
wire framesync_delay; //帧同步峰，与频率补偿输出对应
wire framesync_tsync; //帧同步标志，与TSync输出对应
wire IntpARdy; //TSync输出nd
wire nd_SC_FDE_dout; //SC_FDE输出nd
wire framerdy; //一帧译码结果存储完毕标志
reg flag_bercount = 1'd0;
reg flag_badframe = 1'd0;
reg flag_ber = 1'd0;
wire [11:0] dc_removal_dout_i; //MGC_adaptation、去直流输出
wire [11:0] dc_removal_dout_q;
wire [ 9:0] matchfilterout_i; //MF输出
wire [ 9:0] matchfilterout_q;
wire [ 9:0] DAGC_out_i; //DAGC输出
wire [ 9:0] DAGC_out_q;
wire [ 9:0] freqdataout_i; //频率补偿输出
wire [ 9:0] freqdataout_q;
wire [ 9:0] IntpOuti; //TSync输出
wire [ 9:0] IntpOutq;
wire [ 9:0] SC_FDE_douti; //SC_FDE输出
wire [ 9:0] SC_FDE_doutq;
wire [24:0] mean_temp;
wire [12:0] acc_mean;
wire [ 4:0] state_mgc;
wire mgc1_rdy;
wire flag_state_mgc;
wire [ 2:0] state_rst;
wire flag_overflow;
wire flag_small;
wire [11:0] dc_value_i;
wire [11:0] dc_value_q;
wire flag_dc;
wire flag_agch;
wire flag_agcl;
wire flag_agc_power;
wire [12:0] agc_ref;
wire [12:0] agc_check;
wire flag_powerabsh;
wire flag_powerabsl;
wire flag_abs_power;
wire [10:0] abs_ref;
wire [10:0] abs_check;
wire [ 3:0] flag_clk_4bit; //位同步选取通道结果
wire flagoverflow_fftpilot_26to14; //第1个fft结果截位，即导频fft结果的截位，26截到14
wire flagoverflow_ChnZF_26to18; //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
wire flagoverflow_comdiv_34to20i; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
wire flagoverflow_comdiv_34to20q; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
wire flagoverflow_ifftzero_29to17i; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
wire flagoverflow_ifftzero_29to17q; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
wire flagoverflow_MMSEdiv_divisor_31to28; //第2个除法器，即MMSE除法的分母截位，31截到28
wire flagoverflow_divmmse_34to11; //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
wire flagoverflow_ifftindata_28to20i; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
wire flagoverflow_ifftindata_28to20q; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
wire flagoverflow_fftdata_26to16i; //数据段ow的fft输出截位，26截到16
wire flagoverflow_fftdata_26to16q; //数据段ow的fft输出截位，26截到16
wire flagoverflow_FDE_dataout_29to10i; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
wire flagoverflow_FDE_dataout_29to10q; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
reg flagoverflow = 1'd0; //总溢出标志
wire Pilot_rdy_hide1_d1;
reg [ 7:0] cnt_mgc_delay;
wire mgc_start;
wire flag_mgc_done; // level flag
wire flag_mgc_done_4x; // level flag
// startup delay
always @(posedge clk) begin
if (rst) begin
cnt_mgc_delay <= 0;
@@ -131,6 +130,7 @@ module RecvTop (
assign mgc_start = (cnt_mgc_delay == 8'hFE);
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk),
.rst (rst),
@@ -141,6 +141,8 @@ module RecvTop (
.flag_mgc_done (flag_mgc_done)
);
reg MF_rdy; // flag_mgc_done_d1
wire MF_rst; // flag_mgc_done_pulse_d2
always @(posedge clk) begin
@@ -197,24 +199,25 @@ module RecvTop (
end
wire mf_fir_s_tready_i;
wire mf_fir_s_tready_q;
// Match filter
fir_match_interp4 u_fir_match_filter_interp4_i (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
);
fir_match_interp4 u_fir_match_filter_interp4_q (
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
.aclk (clk), // input wire aclk
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
.s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
);
// CDC into clk_4x
@@ -252,24 +255,31 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
localparam CNT_CHU_SEQ_SYNC_MAX = 8;//! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
wire frame_sync_pulse; // in domain clk
reg flag_frame_sync; // active high level
// calc the magnitude
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
//* calc the magnitude
MagnitudeEstimator #(
.VEC_WIDTH(21)
) u_MagnitudeEstimator (
.clk (clk_4x),
.rst (rst),
.vec_valid(dmf_tvalid_interp4_i),
.I (dmf_tdata_interp4_i),
.Q (dmf_tdata_interp4_q),
.I (dmf_tdata_interp4_i[20:0]),
.Q (dmf_tdata_interp4_q[20:0]),
.mag (mag),
.mag_valid(mag_valid)
);
// frame sync threashold judgement
//* frame sync threashold judgement
PAPR #(
.MAG_WIDTH (22),
.WINDOW_DEPTH(1023)
@@ -279,41 +289,47 @@ module RecvTop (
.vec_mag (mag),
.mag_valid (mag_valid),
.frame_sync (frame_sync_4x),
.frame_sync_pulse()
.frame_sync_pulse() // under clk_4x
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
end
else begin
cnt_chu_seq_sync <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
flag_frame_sync <= 0;
end
else if (frame_sync_pulse) begin
else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
flag_frame_sync <= 1;
end
else begin
flag_frame_sync <= flag_frame_sync;
end
end
// wire [9:0] DAGC_out_i;
// wire [9:0] DAGC_out_q;
wire [9:0] FrameSync_douti;
wire [9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
//帧同步模块
assign FrameSync_dini = DAGC_out_i;
assign FrameSync_dinq = DAGC_out_q;
// wire framesync;
wire [ 9:0] FrameSync_douti;
wire [ 9:0] FrameSync_doutq;
wire dagc_rdy;
wire mgc_rdy;
wire rst_dagc;
// * lost the connection with other nodes
reg [20:0] cnt_lost;
reg framelost;
reg [20:0] cnt_lost;
reg framelost;
always @(posedge clk) begin
if (Pilot_rdy_hide1_d1) begin
if (rst_frame_sync) begin
cnt_lost <= 21'd0;
framelost <= 1'b0;
end
@@ -353,13 +369,7 @@ module RecvTop (
);
//载波频偏补偿
// wire [9:0] freqdataout_i;
// wire [9:0] freqdataout_q;
// wire framesync_delay;
wire data_save; //debug用，暂不需使用
// wire rst_freq;
// CFO estimation
freqestm freqestm (
.clk (clk),
.rst (mgc_start),
@@ -376,18 +386,17 @@ module RecvTop (
//位同步
wire [1:0] cnt_tsync;
// wire framesync_tsync; //帧同步标志
TimeSync_top TimeSync_top (
.clk (clk),
.rst (Pilot_rdy_hide1_d1),
.rst (rst_frame_sync),
.dini (freqdataout_i),
.dinq (freqdataout_q),
.rdy (IntpARdy),
.douti (IntpOuti),
.doutq (IntpOutq),
.vio_tsync_inter16(vio_tsync_inter16),
.framesync (framesync_delay), //帧同步标志
.framesync_tsync (framesync_tsync), //帧同步标志
.framesync (framesync_delay), //帧同步标志
.framesync_tsync (framesync_tsync), //帧同步标志
//debug
.cnt_tsync (cnt_tsync),
.flag_clk_4bit (flag_clk_4bit)
@@ -398,15 +407,13 @@ module RecvTop (
// SC-FDE
SC_FDE_TOP SC_FDE_TOP_djy (
.clk(clk),
.rst(Pilot_rdy_hide1_d1),
.EQUenable_vio(EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.clk (clk),
.rst (rst_frame_sync),
// param
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.nd (IntpARdy),
.dini (IntpOuti),
.dinq (IntpOutq),
@@ -414,20 +421,20 @@ module RecvTop (
.SC_FDE_douti (SC_FDE_douti),
.SC_FDE_doutq (SC_FDE_doutq),
// debug,溢出标志
.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14),
.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18),
.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i),
.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q),
.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i),
.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q),
.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28),
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11),
.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i),
.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q),
.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i),
.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q),
.flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i),
.flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q)
.flagoverflow_fftpilot_26to14 (),
.flagoverflow_ChnZF_26to18 (),
.flagoverflow_comdiv_34to20i (),
.flagoverflow_comdiv_34to20q (),
.flagoverflow_ifftzero_29to17i (),
.flagoverflow_ifftzero_29to17q (),
.flagoverflow_MMSEdiv_divisor_31to28(),
.flagoverflow_divmmse_34to11 (),
.flagoverflow_ifftindata_28to20i (),
.flagoverflow_ifftindata_28to20q (),
.flagoverflow_fftdata_26to16i (),
.flagoverflow_fftdata_26to16q (),
.flagoverflow_FDE_dataout_29to10i (),
.flagoverflow_FDE_dataout_29to10q ()
);
@@ -436,7 +443,7 @@ module RecvTop (
wire [9:0] phase_adjust_doutq;
phase_adjust phase_adjust (
.clk (clk),
.rst (Pilot_rdy_hide1_d1),
.rst (rst_frame_sync),
.din_i (SC_FDE_douti),
.din_q (SC_FDE_doutq),
.nd (nd_SC_FDE_dout),
@@ -452,8 +459,8 @@ module RecvTop (
IQmerge IQmerge (
.clk (clk),
.clk2 (clk2),
.rst (rst2 || Pilot_rdy_hide1_d1),
.clk2 (clk_2x),
.rst (rst2 || rst_frame_sync),
.nd (phase_adjust_rdy),
.framesync (framesync_tsync),
.dini (phase_adjust_douti),
@@ -469,9 +476,10 @@ module RecvTop (
wire [8:0] good_frames;
wire [8:0] bad_frames;
wire [8:0] total_frames;
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
.clk (clk2),
.Rst (rst2 || Pilot_rdy_hide1_d1),
.clk (clk_2x),
.Rst (rst2 || rst_frame_sync),
.FrameSync (ldpcsyncin),
.Nd (IQmergerdy),
.Din (IQmergedout),
@@ -487,89 +495,6 @@ module RecvTop (
wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位
wire [ 1:0] state_ram;
wire berstart_1d;
wire bercompare;
wire [16:0] bercount;
wire [16:0] bercount_max;
wire [16:0] ROMaddra_d2;
wire RAMdout_d1;
wire validnd_new_new;
wire [63:0] stop_temp_new;
wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
wire [16:0] addr_stop_0;
wire [ 2:0] cnt_8;
wire state_8;
wire rdy_scramble;
wire dout_scramble;
wire [16:0] RAMaddra; //比较误码率
wire [16:0] ROMaddra; //比较误码率
wire nd_ber;
FrameMerge FrameMerge (
.clk (clk2),
.rst (Pilot_rdy_hide1_d1),
.rst2(rst2),
.sync(LDPC_SyncOut),
.nd (LDPC_Rdy),
.din (LDPC_Dout),
.vio_stopbit(vio_stopbit),
.frameIDnd(Pilot_rdy_hide1_d1),
.clk2 (clk_60M_mac),
.framerdy (framerdy),
.recv_addr_new_0 (recv_addr_new_0),
.recv_addr_new_1 (recv_addr_new_1),
.recv_addr_new_2 (recv_addr_new_2),
.recv_addr_new_3 (recv_addr_new_3),
.recv_data_new_0 (recv_data_new_0),
.recv_data_new_1 (recv_data_new_1),
.recv_data_new_2 (recv_data_new_2),
.recv_data_new_3 (recv_data_new_3),
.RAMaddra_write_0(RAMaddra_write_0),
.RAMaddra_write_1(RAMaddra_write_1),
.RAMaddra_write_2(RAMaddra_write_2),
.RAMaddra_write_3(RAMaddra_write_3),
.RAMaddra_new_0 (RAMaddra_new_0),
.RAMaddra_new_1 (RAMaddra_new_1),
.RAMaddra_new_2 (RAMaddra_new_2),
.RAMaddra_new_3 (RAMaddra_new_3),
.flag_notbyte(flag_notbyte),
.state_ram (state_ram),
.flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕
.addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
//debug
.berstart_1d (berstart_1d),
.bercompare (bercompare),
.bercount (bercount),
.bercount_max(bercount_max),
.ROMaddra_d2 (ROMaddra_d2),
.RAMdout_d1 (RAMdout_d1),
.validnd_new_new(validnd_new_new),
.stop_temp_new(stop_temp_new),
.flag_stop_0(flag_stop_0),
.addr_stop_0(addr_stop_0),
.cnt_8 (cnt_8),
.state_8 (state_8),
.rdy_scramble (rdy_scramble),
.dout_scramble(dout_scramble),
.RAMaddra (RAMaddra),
.ROMaddra (ROMaddra),
.nd_ber (nd_ber),
.recvNetData (recvNetData),
.recvNetDataNd(recvNetDataNd)
);
// ***** cdc *****
xpm_cdc_single #(
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
@@ -586,8 +511,8 @@ module RecvTop (
xpm_cdc_pulse #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) xpm_cdc_frame_sync_pulse_inst (