refactor(recviver): simulation pass for ila data

2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
56 changed files with 5822 additions and 1186 deletions
@@ -0,0 +1,78 @@
+`timescale 1ns / 1ns
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2019/11/18 23:18:07
+// Design Name: 
+// Module Name: VNU_1din
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module VNU_1din(
+    input clk,
+    input [7:0] din01_CN_CU,   //校验节点信息输入
+    input [7:0] din02_CHNL_CU, //信道信息输入
+    
+    output reg [7:0] dout01_CU=8'd0,//校验节点更新输出    
+    output reg [0:0] dout02_result_CU=1'd0//判决结果输出 
+    );//输出相对输入延时8个周期(8)
+
+    reg [8:0] sum=9'd0;
+    
+    reg [0:0] result_reg0=1'd0;
+    reg [0:0] result_reg1=1'd0; 
+    reg [0:0] result_reg2=1'd0;
+    reg [0:0] result_reg3=1'd0;
+    reg [0:0] result_reg4=1'd0;
+    
+    reg [8:0] din01_CN_CU_9bit=9'd0;
+    reg [8:0] din02_CHNL_CU_9bit=9'd0;
+    
+    reg [7:0] din02_CHNL_CU_reg0=8'd0;
+    reg [7:0] din02_CHNL_CU_reg1=8'd0;
+    reg [7:0] din02_CHNL_CU_reg2=8'd0;
+    reg [7:0] din02_CHNL_CU_reg3=8'd0;
+    reg [7:0] din02_CHNL_CU_reg4=8'd0;
+    reg [7:0] din02_CHNL_CU_reg5=8'd0;
+    reg [7:0] din02_CHNL_CU_reg6=8'd0;
+
+    always @ (posedge clk) begin//先把输入转换为9bit
+        din01_CN_CU_9bit        <= {din01_CN_CU[7],din01_CN_CU[7:0]};
+        din02_CHNL_CU_9bit      <= {din02_CHNL_CU[7],din02_CHNL_CU[7:0]};
+    end
+       
+    always @ (posedge clk) begin//结果更新过程
+        sum                    <= din01_CN_CU_9bit + din02_CHNL_CU_9bit; 
+        result_reg0              <= {sum[8]};
+        
+        result_reg1              <= result_reg0;
+        result_reg2              <= result_reg1;
+        result_reg3              <= result_reg2;
+        result_reg4              <= result_reg3;
+        dout02_result_CU         <= result_reg4;
+    end
+    
+    always @ (posedge clk) begin
+        din02_CHNL_CU_reg0     <= din02_CHNL_CU;
+        din02_CHNL_CU_reg1     <= din02_CHNL_CU_reg0;
+        din02_CHNL_CU_reg2     <= din02_CHNL_CU_reg1;
+        din02_CHNL_CU_reg3     <= din02_CHNL_CU_reg2;
+        din02_CHNL_CU_reg4     <= din02_CHNL_CU_reg3;
+        din02_CHNL_CU_reg5     <= din02_CHNL_CU_reg4;
+        din02_CHNL_CU_reg6     <= din02_CHNL_CU_reg5;
+        dout01_CU              <= din02_CHNL_CU_reg6;  
+    end
+endmodule
+