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refactor(recviver): simulation pass for ila data

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ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
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hdl/VNU_3din.v
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`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/18 23:18:07
// Design Name:
// Module Name: VNU_3din
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VNU_3din(
input clk,
input [7:0] din01_CN_CU, //校验节点信息输入
input [7:0] din02_CN_CU, //校验节点信息输入
input [7:0] din03_CN_CU, //校验节点信息输入
input [7:0] din04_CHNL_CU, //信道信息输入
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
output reg [0:0] dout04_result_CU=1'd0//判决结果输出
);//输出相对输入延时8个周期(8)
reg [9:0] din01_CN_CU_10bit=10'd0;
reg [9:0] din02_CN_CU_10bit=10'd0;
reg [9:0] din03_CN_CU_10bit=10'd0;
reg [9:0] din01_CN_CU_10bit_reg0=10'd0;
reg [9:0] din02_CN_CU_10bit_reg0=10'd0;
reg [9:0] din03_CN_CU_10bit_reg0=10'd0;
reg [9:0] din01_CN_CU_10bit_reg1=10'd0;
reg [9:0] din02_CN_CU_10bit_reg1=10'd0;
reg [9:0] din03_CN_CU_10bit_reg1=10'd0;
reg [9:0] din04_CHNL_CU_10bit=10'd0;
reg [9:0] sum1=10'd0;
reg [9:0] sum2=10'd0;
reg [9:0] sum=10'd0;
reg [9:0] minus1=10'd0;
reg [9:0] minus2=10'd0;
reg [9:0] minus3=10'd0;
reg [9:0] minus1_reg0=10'd0;
reg [9:0] minus2_reg0=10'd0;
reg [9:0] minus3_reg0=10'd0;
reg [9:0] minus1_reg1=10'd0;
reg [9:0] minus2_reg1=10'd0;
reg [9:0] minus3_reg1=10'd0;
reg [9:0] minus1_reg2=10'd0;
reg [9:0] minus2_reg2=10'd0;
reg [9:0] minus3_reg2=10'd0;
reg [9:0] minus1_abs=10'd0;
reg [9:0] minus2_abs=10'd0;
reg [9:0] minus3_abs=10'd0;
reg [0:0] result_reg0=1'd0;
reg [0:0] result_reg1=1'd0;
reg [0:0] result_reg2=1'd0;
reg [0:0] result_reg3=1'd0;
always @ (posedge clk) begin//先把输入转换为10bit
din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
din03_CN_CU_10bit <= {{2{din03_CN_CU[7]}},din03_CN_CU[7:0]};
din04_CHNL_CU_10bit <= {{2{din04_CHNL_CU[7]}},din04_CHNL_CU[7:0]};
end
always @ (posedge clk) begin//流水延时过程
din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
din03_CN_CU_10bit_reg0 <= din03_CN_CU_10bit;
din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
din03_CN_CU_10bit_reg1 <= din03_CN_CU_10bit_reg0;
minus1_reg0 <= minus1;
minus2_reg0 <= minus2;
minus3_reg0 <= minus3;
minus1_reg1 <= minus1_reg0;
minus2_reg1 <= minus2_reg0;
minus3_reg1 <= minus3_reg0;
minus1_reg2 <= minus1_reg1;
minus2_reg2 <= minus2_reg1;
minus3_reg2 <= minus3_reg1;
end
always @ (posedge clk) begin//结果更新过程
sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
sum2 <= din03_CN_CU_10bit + din04_CHNL_CU_10bit;
sum <= sum1 + sum2;
result_reg0 <= {sum[9]};
result_reg1 <= result_reg0;
result_reg2 <= result_reg1;
result_reg3 <= result_reg2;
dout04_result_CU <= result_reg3;
minus1 <= sum - din01_CN_CU_10bit_reg1;
minus2 <= sum - din02_CN_CU_10bit_reg1;
minus3 <= sum - din03_CN_CU_10bit_reg1;
if(minus1_reg1[9])//限幅前求绝对值操作
minus1_abs <= ~minus1_reg1 + 10'd1;
else
minus1_abs <= minus1_reg1;
if(minus1_reg2[9]) begin//限幅操作
if(minus1_abs>10'd127)
dout01_CU <= -8'd127;
else
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
// dout01_CU <= minus1_reg2;
end else begin
if(minus1_abs>10'd127)
dout01_CU <= 8'd127;
else
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
// dout01_CU <= minus1_reg2;
end
if(minus2_reg1[9])//限幅前求绝对值操作
minus2_abs <= ~minus2_reg1 + 10'd1;
else
minus2_abs <= minus2_reg1;
if(minus2_reg2[9]) begin//限幅操作
if(minus2_abs>10'd127)
dout02_CU <= -8'd127;
else
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
// dout02_CU <= minus2_reg2;
end else begin
if(minus2_abs>10'd127)
dout02_CU <= 8'd127;
else
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
// dout02_CU <= minus2_reg2;
end
if(minus3_reg1[9])//限幅前求绝对值操作
minus3_abs <= ~minus3_reg1 + 10'd1;
else
minus3_abs <= minus3_reg1;
if(minus3_reg2[9]) begin//限幅操作
if(minus3_abs>10'd127)
dout03_CU <= -8'd127;
else
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
// dout03_CU <= minus3_reg2;
end else begin
if(minus3_abs>10'd127)
dout03_CU <= 8'd127;
else
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
// dout03_CU <= minus3_reg2;
end
end
endmodule