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refactor(recviver): simulation pass for ila data

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ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
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hdl/VNU_6din.v
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`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/11/18 23:18:07
// Design Name:
// Module Name: VNU_6din
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module VNU_6din(
input clk,
input [7:0] din01_CN_CU, //校验节点信息输入
input [7:0] din02_CN_CU, //校验节点信息输入
input [7:0] din03_CN_CU, //校验节点信息输入
input [7:0] din04_CN_CU, //校验节点信息输入
input [7:0] din05_CN_CU, //校验节点信息输入
input [7:0] din06_CN_CU, //校验节点信息输入
input [7:0] din07_CHNL_CU, //信道信息输入
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
output reg [7:0] dout04_CU=8'd0,//校验节点更新输出
output reg [7:0] dout05_CU=8'd0,//校验节点更新输出
output reg [7:0] dout06_CU=8'd0,//校验节点更新输出
output reg [0:0] dout07_result_CU=1'd0//判决结果输出
);//输出相对输入延时8个周期
reg [10:0] din01_CN_CU_11bit=11'd0;
reg [10:0] din02_CN_CU_11bit=11'd0;
reg [10:0] din03_CN_CU_11bit=11'd0;
reg [10:0] din04_CN_CU_11bit=11'd0;
reg [10:0] din05_CN_CU_11bit=11'd0;
reg [10:0] din06_CN_CU_11bit=11'd0;
reg [10:0] din01_CN_CU_11bit_reg0=11'd0;
reg [10:0] din02_CN_CU_11bit_reg0=11'd0;
reg [10:0] din03_CN_CU_11bit_reg0=11'd0;
reg [10:0] din04_CN_CU_11bit_reg0=11'd0;
reg [10:0] din05_CN_CU_11bit_reg0=11'd0;
reg [10:0] din06_CN_CU_11bit_reg0=11'd0;
reg [10:0] din01_CN_CU_11bit_reg1=11'd0;
reg [10:0] din02_CN_CU_11bit_reg1=11'd0;
reg [10:0] din03_CN_CU_11bit_reg1=11'd0;
reg [10:0] din04_CN_CU_11bit_reg1=11'd0;
reg [10:0] din05_CN_CU_11bit_reg1=11'd0;
reg [10:0] din06_CN_CU_11bit_reg1=11'd0;
reg [10:0] din01_CN_CU_11bit_reg2=11'd0;
reg [10:0] din02_CN_CU_11bit_reg2=11'd0;
reg [10:0] din03_CN_CU_11bit_reg2=11'd0;
reg [10:0] din04_CN_CU_11bit_reg2=11'd0;
reg [10:0] din05_CN_CU_11bit_reg2=11'd0;
reg [10:0] din06_CN_CU_11bit_reg2=11'd0;
reg [10:0] din07_CHNL_CU_11bit=11'd0;
reg [10:0] din07_CHNL_CU_11bit_reg0=11'd0;
reg [10:0] sum1=11'd0;
reg [10:0] sum2=11'd0;
reg [10:0] sum3=11'd0;
reg [10:0] sum4=11'd0;
reg [10:0] sum5=11'd0;
reg [10:0] sum=11'd0;
reg [10:0] minus1=11'd0;
reg [10:0] minus2=11'd0;
reg [10:0] minus3=11'd0;
reg [10:0] minus4=11'd0;
reg [10:0] minus5=11'd0;
reg [10:0] minus6=11'd0;
reg [10:0] minus1_reg0=11'd0;
reg [10:0] minus2_reg0=11'd0;
reg [10:0] minus3_reg0=11'd0;
reg [10:0] minus4_reg0=11'd0;
reg [10:0] minus5_reg0=11'd0;
reg [10:0] minus6_reg0=11'd0;
reg [10:0] minus1_reg1=11'd0;
reg [10:0] minus2_reg1=11'd0;
reg [10:0] minus3_reg1=11'd0;
reg [10:0] minus4_reg1=11'd0;
reg [10:0] minus5_reg1=11'd0;
reg [10:0] minus6_reg1=11'd0;
reg [10:0] minus1_abs=11'd0;
reg [10:0] minus2_abs=11'd0;
reg [10:0] minus3_abs=11'd0;
reg [10:0] minus4_abs=11'd0;
reg [10:0] minus5_abs=11'd0;
reg [10:0] minus6_abs=11'd0;
reg [0:0] result_reg0=1'd0;
reg [0:0] result_reg1=1'd0;
reg [0:0] result_reg2=1'd0;
always @ (posedge clk) begin//先把输入转换为11bit
din01_CN_CU_11bit <= {{3{din01_CN_CU[7]}},din01_CN_CU[7:0]};
din02_CN_CU_11bit <= {{3{din02_CN_CU[7]}},din02_CN_CU[7:0]};
din03_CN_CU_11bit <= {{3{din03_CN_CU[7]}},din03_CN_CU[7:0]};
din04_CN_CU_11bit <= {{3{din04_CN_CU[7]}},din04_CN_CU[7:0]};
din05_CN_CU_11bit <= {{3{din05_CN_CU[7]}},din05_CN_CU[7:0]};
din06_CN_CU_11bit <= {{3{din06_CN_CU[7]}},din06_CN_CU[7:0]};
din07_CHNL_CU_11bit <= {{3{din07_CHNL_CU[7]}},din07_CHNL_CU[7:0]};
end
always @ (posedge clk) begin//流水延时过程
din01_CN_CU_11bit_reg0 <= din01_CN_CU_11bit;
din02_CN_CU_11bit_reg0 <= din02_CN_CU_11bit;
din03_CN_CU_11bit_reg0 <= din03_CN_CU_11bit;
din04_CN_CU_11bit_reg0 <= din04_CN_CU_11bit;
din05_CN_CU_11bit_reg0 <= din05_CN_CU_11bit;
din06_CN_CU_11bit_reg0 <= din06_CN_CU_11bit;
din07_CHNL_CU_11bit_reg0 <= din07_CHNL_CU_11bit;
din01_CN_CU_11bit_reg1 <= din01_CN_CU_11bit_reg0;
din02_CN_CU_11bit_reg1 <= din02_CN_CU_11bit_reg0;
din03_CN_CU_11bit_reg1 <= din03_CN_CU_11bit_reg0;
din04_CN_CU_11bit_reg1 <= din04_CN_CU_11bit_reg0;
din05_CN_CU_11bit_reg1 <= din05_CN_CU_11bit_reg0;
din06_CN_CU_11bit_reg1 <= din06_CN_CU_11bit_reg0;
din01_CN_CU_11bit_reg2 <= din01_CN_CU_11bit_reg1;
din02_CN_CU_11bit_reg2 <= din02_CN_CU_11bit_reg1;
din03_CN_CU_11bit_reg2 <= din03_CN_CU_11bit_reg1;
din04_CN_CU_11bit_reg2 <= din04_CN_CU_11bit_reg1;
din05_CN_CU_11bit_reg2 <= din05_CN_CU_11bit_reg1;
din06_CN_CU_11bit_reg2 <= din06_CN_CU_11bit_reg1;
minus1_reg0 <= minus1;
minus2_reg0 <= minus2;
minus3_reg0 <= minus3;
minus4_reg0 <= minus4;
minus5_reg0 <= minus5;
minus6_reg0 <= minus6;
minus1_reg1 <= minus1_reg0;
minus2_reg1 <= minus2_reg0;
minus3_reg1 <= minus3_reg0;
minus4_reg1 <= minus4_reg0;
minus5_reg1 <= minus5_reg0;
minus6_reg1 <= minus6_reg0;
end
always @ (posedge clk) begin//结果更新过程
sum1 <= din01_CN_CU_11bit + din02_CN_CU_11bit;
sum2 <= din03_CN_CU_11bit + din04_CN_CU_11bit;
sum3 <= din05_CN_CU_11bit + din06_CN_CU_11bit;
sum4 <= sum1 + sum2;
sum5 <= sum3 + din07_CHNL_CU_11bit_reg0;
sum <= sum4 + sum5;
result_reg0 <= {sum[10]};
result_reg1 <= result_reg0;
result_reg2 <= result_reg1;
dout07_result_CU <= result_reg2;
minus1 <= sum - din01_CN_CU_11bit_reg2;
minus2 <= sum - din02_CN_CU_11bit_reg2;
minus3 <= sum - din03_CN_CU_11bit_reg2;
minus4 <= sum - din04_CN_CU_11bit_reg2;
minus5 <= sum - din05_CN_CU_11bit_reg2;
minus6 <= sum - din06_CN_CU_11bit_reg2;
if(minus1_reg0[10])//限幅前求绝对值操作
minus1_abs <= ~minus1_reg0 + 11'd1;
else
minus1_abs <= minus1_reg0;
if(minus1_reg1[10]) begin//限幅操作
if(minus1_abs>11'd127)
dout01_CU <= -8'd127;
else
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
// dout01_CU <= minus1_reg1;
end else begin
if(minus1_abs>11'd127)
dout01_CU <= 8'd127;
else
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
// dout01_CU <= minus1_reg1;
end
if(minus2_reg0[10])//限幅前求绝对值操作
minus2_abs <= ~minus2_reg0 + 11'd1;
else
minus2_abs <= minus2_reg0;
if(minus2_reg1[10]) begin//限幅操作
if(minus2_abs>11'd127)
dout02_CU <= -8'd127;
else
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
// dout02_CU <= minus2_reg1;
end else begin
if(minus2_abs>11'd127)
dout02_CU <= 8'd127;
else
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
// dout02_CU <= minus2_reg1;
end
if(minus3_reg0[10])//限幅前求绝对值操作
minus3_abs <= ~minus3_reg0 + 11'd1;
else
minus3_abs <= minus3_reg0;
if(minus3_reg1[10]) begin//限幅操作
if(minus3_abs>11'd127)
dout03_CU <= -8'd127;
else
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
// dout03_CU <= minus3_reg1;
end else begin
if(minus3_abs>11'd127)
dout03_CU <= 8'd127;
else
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
// dout03_CU <= minus3_reg1;
end
if(minus4_reg0[10])//限幅前求绝对值操作
minus4_abs <= ~minus4_reg0 + 11'd1;
else
minus4_abs <= minus4_reg0;
if(minus4_reg1[10]) begin//限幅操作
if(minus4_abs>11'd127)
dout04_CU <= -8'd127;
else
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
// dout04_CU <= minus4_reg1;
end else begin
if(minus4_abs>11'd127)
dout04_CU <= 8'd127;
else
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
// dout04_CU <= minus4_reg1;
end
if(minus5_reg0[10])//限幅前求绝对值操作
minus5_abs <= ~minus5_reg0 + 11'd1;
else
minus5_abs <= minus5_reg0;
if(minus5_reg1[10]) begin//限幅操作
if(minus5_abs>11'd127)
dout05_CU <= -8'd127;
else
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
// dout05_CU <= minus5_reg1;
end else begin
if(minus5_abs>11'd127)
dout05_CU <= 8'd127;
else
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
// dout05_CU <= minus5_reg1;
end
if(minus6_reg0[10])//限幅前求绝对值操作
minus6_abs <= ~minus6_reg0 + 11'd1;
else
minus6_abs <= minus6_reg0;
if(minus6_reg1[10]) begin//限幅操作
if(minus6_abs>11'd127)
dout06_CU <= -8'd127;
else
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
// dout06_CU <= minus6_reg1;
end else begin
if(minus6_abs>11'd127)
dout06_CU <= 8'd127;
else
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
// dout06_CU <= minus6_reg1;
end
end
endmodule