refactor(recviver): simulation pass for ila data

hdl/abs_min_4din.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ns
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    21:36:07 01/20/2018 
+// Design Name: 
+// Module Name:    abs_min_4din 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module abs_min_4din #(
+    parameter WIDTH = 4'd8
+) (
+    input                  clk,
+    input      [WIDTH-1:0] din01,            //din01<din02
+    input      [WIDTH-1:0] din02,
+    input      [WIDTH-1:0] din03,            //din03<din04
+    input      [WIDTH-1:0] din04,
+    output reg [WIDTH-1:0] dout_min = 8'd0,
+    output reg [WIDTH-1:0] dout_sec = 8'd0
+);  //输出相对输入延时1个周期
+
+    always @(posedge clk) begin
+        if (din02 <= din03) begin
+            dout_min <= din01;
+            dout_sec <= din02;
+        end
+        else begin
+            if (din01 <= din03) begin
+                dout_min <= din01;
+                dout_sec <= din03;
+            end
+            else begin
+                dout_min <= din03;
+                dout_sec <= (din01 < din04) ? din01 : din04;
+            end
+        end
+    end
+
+endmodule
+