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refactor(recviver): simulation pass for ila data

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This commit is contained in:
ZoroGH
2024-07-24 21:32:28 +08:00
parent 09fe5b3f8d
commit 0bedb6c2ef
56 changed files with 5822 additions and 1186 deletions
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hdl/ad9361_mgc_pin_ctrl.v
+22 -13
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@@ -21,7 +21,7 @@ module ad9361_mgc_pin_ctrl (
input [11:0] rx_data_q,
// this port is from zynq to ad9361
output wire [ 3:0] ad9361_ctrl_in,
output reg flag_mgc_done // active high level signal
output reg flag_mgc_done = 0 // active high level signal
);
@@ -117,15 +117,24 @@ module ad9361_mgc_pin_ctrl (
if (cnt_pulse_width == 0) begin
ns = S_DONE;
end
else begin
ns = S_IDLE;
end
end
S_DEC: begin
if (cnt_pulse_width == 0) begin
ns = S_DONE;
end
else begin
ns = S_IDLE;
end
end
S_DONE: begin
ns = S_IDLE;
end
default: begin
ns = S_IDLE;
end
endcase
end
@@ -151,18 +160,18 @@ module ad9361_mgc_pin_ctrl (
// .probe_out0(start) // output wire [0 : 0] probe_out0
// );
ila_ad9361_mgc u_ila_ad9361_mgc (
.clk (clk), // input wire clk
.probe0(start_posedge), // input wire [0:0] probe0
.probe1(rx_data_i), // input wire [11:0] probe1
.probe2(u_power_measure.cs), // input wire [2:0] probe2
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
.probe5(flag_too_high), // input wire [0:0] probe5
.probe6(flag_too_low), // input wire [0:0] probe6
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
);
// ila_ad9361_mgc u_ila_ad9361_mgc (
// .clk (clk), // input wire clk
// .probe0(start_posedge), // input wire [0:0] probe0
// .probe1(rx_data_i), // input wire [11:0] probe1
// .probe2(u_power_measure.cs), // input wire [2:0] probe2
// .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
// .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
// .probe5(flag_too_high), // input wire [0:0] probe5
// .probe6(flag_too_low), // input wire [0:0] probe6
// .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
// .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
// );
endmodule