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fix(top): reverse iq in recv

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ZoroGH
2024-08-02 20:51:37 +08:00
parent 92583b785c
commit 145e8c0930
11 changed files with 1918 additions and 569 deletions
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hdl/PAPR.v
+2 -19
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@@ -27,7 +27,7 @@ module PAPR #(
parameter WINDOW_DEPTH = 1023
// parameter GATE = 8
) (
input clk,
input clk,
input rst,
input [MAG_WIDTH-1:0] vec_mag,
input mag_valid,
@@ -64,11 +64,6 @@ module PAPR #(
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 5:0] cnt;
// shift_1024 shift_1024 (
// .D (vec_mag), // input wire [21 : 0] D
// .CLK(clk), // input wire CLK
// .Q (vec_mag_1024) // output wire [21 : 0] Q
// );
shift_reg #(
.DATA_WIDTH(MAG_WIDTH),
@@ -144,22 +139,10 @@ module PAPR #(
end
// ******** Wire & Reg ********
// ******** Assingment ********
// ******** Logic Block ********
// ******** Inst ********
// ******** Debug ********
// NOTE: comment
ila_frame_sync u_ila_frame_sync (
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(mag_valid), // input wire [0:0] probe1
.probe1(data_avg), // input wire [21:0] probe0
.probe2(frame_sync) // input wire [0:0] probe2
);
hdl/RecvTop.v
+52 -38
View File
@@ -20,24 +20,25 @@
//////////////////////////////////////////////////////////////////////////////////
module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
input rst2, // TODO： delete the signal
// phy wave
input [11:0] dini,
input [11:0] dinq,
// mgc control
output [ 3:0] ad9361_ctrl_in,
output wire frame_sync_pulse, // in domain clk
output wire flag_mgc_done_pulse, // active high pulse signal
output wire frame_sync_pulse, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
// stop signal
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
// mac frame header
output [63:0] recvNetData,
output recvNetDataNd
@@ -47,7 +48,7 @@ module RecvTop (
wire rst_freq;
wire DAGC_rdy;
wire framesync; //帧同步峰
wire framesync_delay; //帧同步峰，与频率补偿输出对应
wire flag_cfo_done; //帧同步峰，与频率补偿输出对应
wire framesync_tsync; //帧同步标志，与TSync输出对应
wire IntpARdy; //TSync输出nd
wire nd_SC_FDE_dout; //SC_FDE输出nd
@@ -133,13 +134,14 @@ module RecvTop (
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in(ad9361_ctrl_in),
.flag_mgc_done (flag_mgc_done)
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.flag_mgc_done (flag_mgc_done)
);
@@ -256,6 +258,7 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
wire [7:0] cnt_chu_seq_sync_max_vio;
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
@@ -266,7 +269,7 @@ module RecvTop (
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -298,7 +301,7 @@ module RecvTop (
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
end
else begin
@@ -310,7 +313,7 @@ module RecvTop (
if (rst) begin
flag_frame_sync <= 0;
end
else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin
flag_frame_sync <= 1;
end
else begin
@@ -380,7 +383,7 @@ module RecvTop (
.datain_q (DAGC_out_q),
.dataout_i (freqdataout_i),
.dataout_q (freqdataout_q),
.framesync_delay(framesync_delay),
.framesync_delay(flag_cfo_done),
.data_save (data_save),
.rst_freq (rst_freq)
);
@@ -396,7 +399,7 @@ module RecvTop (
.douti (IntpOuti),
.doutq (IntpOutq),
.vio_tsync_inter16(vio_tsync_inter16),
.framesync (framesync_delay), //帧同步标志
.framesync (flag_cfo_done), //帧同步标志
.framesync_tsync (framesync_tsync), //帧同步标志
//debug
.cnt_tsync (cnt_tsync),
@@ -536,24 +539,35 @@ module RecvTop (
// ***** debug *****
vio_recv_top u_vio_recv_top (
.clk (clk),
.probe_out0(cnt_chu_seq_sync_max_vio)
);
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (flag_mgc_done), // width: 1
.probe1 (flag_frame_sync), // width: 1
.probe2 (mf_data_interp4_q), // width: 32
.probe3 (mf_data_interp4_i), // width: 32
.probe4 (freqestm.freq_out), // width: 14
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (nd_SC_FDE_dout), // width: 1
.probe8 (SC_FDE_douti), // width: 10
.probe9 (SC_FDE_doutq), // width: 10
.probe10(LDPC_SyncOut), // width: 1
.probe11(LDPC_Rdy), // width: 1
.probe12(LDPC_Dout), // width: 1
.probe13(bad_frames), // width: 9
.probe14(total_frames), // width: 9
.probe15(mgc_start) // width: 1
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
);
hdl/ad9361_mgc_pin_ctrl.v
+9 -7
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@@ -21,7 +21,8 @@ module ad9361_mgc_pin_ctrl (
input [11:0] rx_data_q,
// this port is from zynq to ad9361
output wire [ 3:0] ad9361_ctrl_in,
output reg flag_mgc_done = 0 // active high level signal
output wire flag_mgc_done_pulse, // active high pulse signal
output reg flag_mgc_done = 0 // active high level signal
);
@@ -54,14 +55,15 @@ module ad9361_mgc_pin_ctrl (
reg [2:0] ns;
// ******** Assingment ********
assign ad9361_ctrl_in[0] = inc_pulse;
assign ad9361_ctrl_in[1] = dec_pulse;
assign ad9361_ctrl_in[0] = inc_pulse;
assign ad9361_ctrl_in[1] = dec_pulse;
assign flag_adjust = flag_too_high | flag_too_low;
assign inc_pulse = (cs == S_INC);
assign dec_pulse = (cs == S_DEC);
assign flag_adjust = flag_too_high | flag_too_low;
assign inc_pulse = (cs == S_INC);
assign dec_pulse = (cs == S_DEC);
assign start_posedge = start & ~start_d1;
assign start_posedge = start & ~start_d1;
assign flag_mgc_done_pulse = power_measure_done_pulse;
// ******** Logic Block ********
hdl/net_city.v
+23 -25
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@@ -75,7 +75,7 @@ module net_city (
always @(posedge clk) begin
if (rst) begin
rx_rst <= 1;
rx_rst <= 0;
end
else if (tx_start) begin
rx_rst <= 1;
@@ -211,31 +211,29 @@ module net_city (
end
8'd50: begin
if (recv_net_data_nd) begin
if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
// if (recv_net_data_nd) begin
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;
// is_net <= 1'b0;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
recv_id <= recv_net_data[63:56];
recv_video_id01 <= recv_net_data[55:48];
recv_video_id02 <= recv_net_data[47:40];
recv_video_id03 <= recv_net_data[39:32];
recv_connect_node <= recv_net_data[31:24];
end
else begin
state_net <= 8'd200;
is_net <= 1'b0;
cnt_trans_slot <= cnt_inter_slot + 32'd1;
end
end
else begin
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= cnt_inter_slot + 32'd1;
end
// cnt_trans_slot <= cnt_inter_slot + 32'd1;
// end
// end
// else begin
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// end
end
8'd51: begin
state_net <= 8'd200;
hdl/power_measure.v
+1 -1
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@@ -30,7 +30,7 @@ module power_measure (
);
localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
localparam CNT_MEASURING_MAX = 512; // * 观察64个周期
localparam CNT_MEASURING_MAX = 256; // * 观察64个周期
localparam CNT_ADJUST_TIMES_MAX = 25;
localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
// ******** Wire & Reg ********
hdl/system_top.v
+86 -69
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@@ -89,6 +89,7 @@ module system_top (
wire tx_data_src_tvalid;
// tx signal
wire tx_test_flag;
wire flag_mgc_done_pulse;
// baseband signal
wire [11:0] ad9361_rx_data_i;
@@ -98,6 +99,13 @@ module system_top (
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
wire [ 2:0] speed_mode;
// mux
wire bb_tx_iq_reverse;
wire bb_rx_iq_reverse;
wire [11:0] bb_tx_i;
wire [11:0] bb_tx_q;
wire [11:0] bb_rx_i;
wire [11:0] bb_rx_q;
// phy control signal
wire phy_rst_vio;
@@ -126,15 +134,20 @@ module system_top (
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ad9361 control
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i;
assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// ******** Logic Block ********
// ******** Inst ********
@@ -196,7 +209,7 @@ module system_top (
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (intr_2ps),
.pl2ps_intr3 (pl2ps_intr3),
.pl2ps_intr3 (flag_mgc_done_pulse),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
@@ -211,44 +224,47 @@ module system_top (
);
// tdma #(
// .SLOT_LEN (750000), // 50MHz--> 15ms
// .TIC_TO_PS_LEN (700000),
// .TIC_FRAME_SYNC(42344)
// ) u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (0),
// .flag_frame_sync(frame_sync_pulse),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
net_city u_net_city (
.clk (clk_1x),
.rst_initial (rst_sys),
.rst_manual (rst_manual),
.tx_start (tx_start),
.trans_net_data (),
.flag_video_send (),
.recv_id (),
.frame_sync (frame_sync_pulse),
.recv_net_data_nd(1),
.recv_net_data (0),
.frame_sync_time (42344),
.id_num (node_id),
.max_slot_num (max_slot_num),
.video_id01 (0),
.video_id02 (0),
.video_id03 (0),
.is_net (),
.flag_to_uc (),
.intr_ps (intr_2ps),
.rx_rst (rx_rst),
.tx_done (tx_done)
tdma #(
.SLOT_LEN (750000), // 50MHz--> 15ms
.TIC_TO_PS_LEN (700000),
.TIC_FRAME_SYNC(42344)
// .SLOT_LEN (625001), // 50MHz--> 15ms
// .TIC_TO_PS_LEN (575000),
// .TIC_FRAME_SYNC(42344)
) u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start
@@ -278,30 +294,31 @@ module system_top (
.tx_data_src_tready(enc_fifo_rd_en),
.tx_data_src_tvalid(~enc_fifo_empty),
.hopping_freq (),
.ad9361_tx_data_i (ad9361_tx_data_i),
.ad9361_tx_data_q (ad9361_tx_data_q),
.ad9361_tx_data_i (bb_tx_i),
.ad9361_tx_data_q (bb_tx_q),
.test (tx_test_flag | phy_tx_test_flag_vio),
.hop_wait (100)
);
RecvTop u_RecvTop (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (ad9361_rx_data_i),
.dinq (ad9361_rx_data_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16(1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
);
@@ -361,7 +378,7 @@ module system_top (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
// .probe2(u_RecvTop.flag_mgc_done)
// );
// ila_ad9361_tx u_ila_ad9361_tx (
@@ -381,13 +398,13 @@ module system_top (
intr_2ps_vio_d1 <= intr_2ps_vio;
end
vio_phy_control u_vio_phy_control (
.clk (clk_1x), // input wire clk
.probe_out0(rst_manual), // output wire [0 : 0]
.probe_out1(node_id), // output wire [7 : 0]
.probe_out2(max_slot_num), // output wire [7 : 0]
.probe_out3(intr_2ps_vio), // output wire [0 : 0]
.probe_out4(tx_start_vio) // output wire [0 : 0]
.clk (clk_1x), // input wire clk
.probe_out0(flag_is_master), // output wire [0 : 0]
.probe_out1(bb_tx_iq_reverse), // output wire [0 : 0]
.probe_out2(bb_rx_iq_reverse) // output wire [0 : 0]
);
hdl/tdma.v
+50 -22
View File
@@ -14,29 +14,36 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter SLOT_LEN = 1250000,
parameter TIC_TO_PS_LEN = 1200000,
parameter TIC_FRAME_SYNC = 42272
parameter SLOT_LEN = 750000,
parameter TIC_TO_PS_LEN = 700000,
parameter TIC_FRAME_SYNC = 42344
) (
input clk,
input rst,
input flag_is_master, // TODO: refactor it to parameters
input flag_frame_sync,
output intr_2ps,
(* KEEP = "TRUE" *) output tx_start,
(* KEEP = "TRUE" *) output rx_rst
input clk,
input rst,
input flag_is_master, // TODO: refactor it to parameters
input flag_frame_sync,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg [23:0] cnt;
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1);
// ******** Logic Block ********
reg [23:0] cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
@@ -48,7 +55,7 @@ module tdma #(
end
else begin
// master
if (cnt < SLOT_LEN) begin
if (cnt < SLOT_LEN - 1) begin
cnt <= cnt + 1;
end
else begin
@@ -57,26 +64,47 @@ module tdma #(
end
end
end
assign tx_start = flag_is_tx_slot & (cnt == 16'd10);
assign rx_rst = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10));
assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
always @(posedge clk) begin
if (rst) begin
flag_is_tx_slot <= 0;
if (flag_is_master) begin
rx_rst <= 1;
end
else if (!flag_is_master && flag_frame_sync) begin
flag_is_tx_slot <= 0;
end
else if (cnt == 16'd1) begin
flag_is_tx_slot <= ~flag_is_tx_slot;
else begin
rx_rst <= flag_is_master | (cnt <= 16'd4);
end
end
// always @(posedge clk) begin
// if (rst) begin
// flag_is_tx_slot <= 0;
// end
// else if (!flag_is_master && flag_frame_sync) begin
// flag_is_tx_slot <= 0;
// end
// else if (cnt == 16'd1) begin
// flag_is_tx_slot <= ~flag_is_tx_slot;
// end
// end
// ******** Inst ********
// ******** Debug ********
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1
);
endmodule