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fix(top): reverse iq in recv

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ZoroGH
2024-08-02 20:51:37 +08:00
parent 92583b785c
commit 145e8c0930
11 changed files with 1918 additions and 569 deletions
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hdl/RecvTop.v
+52 -38
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@@ -20,24 +20,25 @@
//////////////////////////////////////////////////////////////////////////////////
module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
input rst2, // TODO： delete the signal
// phy wave
input [11:0] dini,
input [11:0] dinq,
// mgc control
output [ 3:0] ad9361_ctrl_in,
output wire frame_sync_pulse, // in domain clk
output wire flag_mgc_done_pulse, // active high pulse signal
output wire frame_sync_pulse, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
// stop signal
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
// mac frame header
output [63:0] recvNetData,
output recvNetDataNd
@@ -47,7 +48,7 @@ module RecvTop (
wire rst_freq;
wire DAGC_rdy;
wire framesync; //帧同步峰
wire framesync_delay; //帧同步峰，与频率补偿输出对应
wire flag_cfo_done; //帧同步峰，与频率补偿输出对应
wire framesync_tsync; //帧同步标志，与TSync输出对应
wire IntpARdy; //TSync输出nd
wire nd_SC_FDE_dout; //SC_FDE输出nd
@@ -133,13 +134,14 @@ module RecvTop (
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in(ad9361_ctrl_in),
.flag_mgc_done (flag_mgc_done)
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.flag_mgc_done (flag_mgc_done)
);
@@ -256,6 +258,7 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
wire [7:0] cnt_chu_seq_sync_max_vio;
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
@@ -266,7 +269,7 @@ module RecvTop (
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
//* calc the magnitude
MagnitudeEstimator #(
@@ -298,7 +301,7 @@ module RecvTop (
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
end
else begin
@@ -310,7 +313,7 @@ module RecvTop (
if (rst) begin
flag_frame_sync <= 0;
end
else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin
flag_frame_sync <= 1;
end
else begin
@@ -380,7 +383,7 @@ module RecvTop (
.datain_q (DAGC_out_q),
.dataout_i (freqdataout_i),
.dataout_q (freqdataout_q),
.framesync_delay(framesync_delay),
.framesync_delay(flag_cfo_done),
.data_save (data_save),
.rst_freq (rst_freq)
);
@@ -396,7 +399,7 @@ module RecvTop (
.douti (IntpOuti),
.doutq (IntpOutq),
.vio_tsync_inter16(vio_tsync_inter16),
.framesync (framesync_delay), //帧同步标志
.framesync (flag_cfo_done), //帧同步标志
.framesync_tsync (framesync_tsync), //帧同步标志
//debug
.cnt_tsync (cnt_tsync),
@@ -536,24 +539,35 @@ module RecvTop (
// ***** debug *****
vio_recv_top u_vio_recv_top (
.clk (clk),
.probe_out0(cnt_chu_seq_sync_max_vio)
);
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (flag_mgc_done), // width: 1
.probe1 (flag_frame_sync), // width: 1
.probe2 (mf_data_interp4_q), // width: 32
.probe3 (mf_data_interp4_i), // width: 32
.probe4 (freqestm.freq_out), // width: 14
.probe5 (freqdataout_i), // width: 10
.probe6 (freqdataout_q), // width: 10
.probe7 (nd_SC_FDE_dout), // width: 1
.probe8 (SC_FDE_douti), // width: 10
.probe9 (SC_FDE_doutq), // width: 10
.probe10(LDPC_SyncOut), // width: 1
.probe11(LDPC_Rdy), // width: 1
.probe12(LDPC_Dout), // width: 1
.probe13(bad_frames), // width: 9
.probe14(total_frames), // width: 9
.probe15(mgc_start) // width: 1
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (mf_data_interp4_i[29-:12]), // width: 12
.probe3 (mf_data_interp4_q[29-:12]), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
);