fix(top): reverse iq in recv

hdl/ad9361_mgc_pin_ctrl.v

@@ -21,7 +21,8 @@ module ad9361_mgc_pin_ctrl (
     input       [11:0] rx_data_q,
     // this port is from zynq to ad9361
     output wire [ 3:0] ad9361_ctrl_in,
-    output reg         flag_mgc_done = 0  // active high level signal
+    output wire        flag_mgc_done_pulse,  // active high pulse signal
+    output reg         flag_mgc_done = 0     // active high level signal
 
 );
 
@@ -54,14 +55,15 @@ module ad9361_mgc_pin_ctrl (
     reg [2:0] ns;
 
     // ******** Assingment  ********
-    assign ad9361_ctrl_in[0] = inc_pulse;
-    assign ad9361_ctrl_in[1] = dec_pulse;
+    assign ad9361_ctrl_in[0]   = inc_pulse;
+    assign ad9361_ctrl_in[1]   = dec_pulse;
 
-    assign flag_adjust       = flag_too_high | flag_too_low;
-    assign inc_pulse         = (cs == S_INC);
-    assign dec_pulse         = (cs == S_DEC);
+    assign flag_adjust         = flag_too_high | flag_too_low;
+    assign inc_pulse           = (cs == S_INC);
+    assign dec_pulse           = (cs == S_DEC);
 
-    assign start_posedge     = start & ~start_d1;
+    assign start_posedge       = start & ~start_d1;
+    assign flag_mgc_done_pulse = power_measure_done_pulse;
 
     // ******** Logic Block ********