fix(top): reverse iq in recv
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+23
-25
@@ -75,7 +75,7 @@ module net_city (
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always @(posedge clk) begin
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if (rst) begin
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rx_rst <= 1;
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rx_rst <= 0;
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end
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else if (tx_start) begin
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rx_rst <= 1;
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@@ -211,31 +211,29 @@ module net_city (
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end
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8'd50: begin
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if (recv_net_data_nd) begin
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if (recv_net_data[23:00] == 24'h7e5a33) begin
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state_net <= 8'd51;
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is_net <= 1'b1;
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// if (recv_net_data_nd) begin
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// if (recv_net_data[23:00] == 24'h7e5a33) begin
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state_net <= 8'd51;
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is_net <= 1'b1;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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cnt_inter_slot <= cnt_inter_slot + 32'd1;
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recv_id <= recv_net_data[63:56];
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recv_video_id01 <= recv_net_data[55:48];
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recv_video_id02 <= recv_net_data[47:40];
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recv_video_id03 <= recv_net_data[39:32];
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recv_connect_node <= recv_net_data[31:24];
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// end
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// else begin
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// state_net <= 8'd200;
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// is_net <= 1'b0;
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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cnt_inter_slot <= cnt_inter_slot + 32'd1;
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recv_id <= recv_net_data[63:56];
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recv_video_id01 <= recv_net_data[55:48];
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recv_video_id02 <= recv_net_data[47:40];
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recv_video_id03 <= recv_net_data[39:32];
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recv_connect_node <= recv_net_data[31:24];
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end
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else begin
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state_net <= 8'd200;
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is_net <= 1'b0;
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cnt_trans_slot <= cnt_inter_slot + 32'd1;
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end
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end
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else begin
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cnt_trans_slot <= cnt_trans_slot + 32'd1;
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cnt_inter_slot <= cnt_inter_slot + 32'd1;
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end
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// cnt_trans_slot <= cnt_inter_slot + 32'd1;
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// end
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// end
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// else begin
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// cnt_trans_slot <= cnt_trans_slot + 32'd1;
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// cnt_inter_slot <= cnt_inter_slot + 32'd1;
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// end
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end
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8'd51: begin
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state_net <= 8'd200;
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