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fix(top): reverse iq in recv

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ZoroGH
2024-08-02 20:51:37 +08:00
parent 92583b785c
commit 145e8c0930
11 changed files with 1918 additions and 569 deletions
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hdl/system_top.v
+86 -69
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@@ -89,6 +89,7 @@ module system_top (
wire tx_data_src_tvalid;
// tx signal
wire tx_test_flag;
wire flag_mgc_done_pulse;
// baseband signal
wire [11:0] ad9361_rx_data_i;
@@ -98,6 +99,13 @@ module system_top (
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
wire [ 2:0] speed_mode;
// mux
wire bb_tx_iq_reverse;
wire bb_rx_iq_reverse;
wire [11:0] bb_tx_i;
wire [11:0] bb_tx_q;
wire [11:0] bb_rx_i;
wire [11:0] bb_rx_q;
// phy control signal
wire phy_rst_vio;
@@ -126,15 +134,20 @@ module system_top (
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ad9361 control
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_tx_data_i = bb_tx_iq_reverse ? bb_tx_q : bb_tx_i;
assign ad9361_tx_data_q = bb_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = bb_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = bb_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// ******** Logic Block ********
// ******** Inst ********
@@ -196,7 +209,7 @@ module system_top (
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (intr_2ps),
.pl2ps_intr3 (pl2ps_intr3),
.pl2ps_intr3 (flag_mgc_done_pulse),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
@@ -211,44 +224,47 @@ module system_top (
);
// tdma #(
// .SLOT_LEN (750000), // 50MHz--> 15ms
// .TIC_TO_PS_LEN (700000),
// .TIC_FRAME_SYNC(42344)
// ) u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (0),
// .flag_frame_sync(frame_sync_pulse),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start),
// .rx_rst (rx_rst)
// );
net_city u_net_city (
.clk (clk_1x),
.rst_initial (rst_sys),
.rst_manual (rst_manual),
.tx_start (tx_start),
.trans_net_data (),
.flag_video_send (),
.recv_id (),
.frame_sync (frame_sync_pulse),
.recv_net_data_nd(1),
.recv_net_data (0),
.frame_sync_time (42344),
.id_num (node_id),
.max_slot_num (max_slot_num),
.video_id01 (0),
.video_id02 (0),
.video_id03 (0),
.is_net (),
.flag_to_uc (),
.intr_ps (intr_2ps),
.rx_rst (rx_rst),
.tx_done (tx_done)
tdma #(
.SLOT_LEN (750000), // 50MHz--> 15ms
.TIC_TO_PS_LEN (700000),
.TIC_FRAME_SYNC(42344)
// .SLOT_LEN (625001), // 50MHz--> 15ms
// .TIC_TO_PS_LEN (575000),
// .TIC_FRAME_SYNC(42344)
) u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_is_master (flag_is_master),
.flag_frame_sync(frame_sync_pulse),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// net_city u_net_city (
// .clk (clk_1x),
// .rst_initial (rst_sys),
// .rst_manual (rst_manual),
// .tx_start (tx_start),
// .trans_net_data (),
// .flag_video_send (),
// .recv_id (),
// .frame_sync (frame_sync_pulse),
// .recv_net_data_nd(1'b1),
// .recv_net_data (64'd0),
// .frame_sync_time (42344),
// .id_num (node_id),
// .max_slot_num (max_slot_num),
// .video_id01 (0),
// .video_id02 (0),
// .video_id03 (0),
// .is_net (),
// .flag_to_uc (),
// .intr_ps (intr_2ps),
// .rx_rst (rx_rst),
// .tx_done (tx_done)
// );
// ---- PHY layer logic start
@@ -278,30 +294,31 @@ module system_top (
.tx_data_src_tready(enc_fifo_rd_en),
.tx_data_src_tvalid(~enc_fifo_empty),
.hopping_freq (),
.ad9361_tx_data_i (ad9361_tx_data_i),
.ad9361_tx_data_q (ad9361_tx_data_q),
.ad9361_tx_data_i (bb_tx_i),
.ad9361_tx_data_q (bb_tx_q),
.test (tx_test_flag | phy_tx_test_flag_vio),
.hop_wait (100)
);
RecvTop u_RecvTop (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (ad9361_rx_data_i),
.dinq (ad9361_rx_data_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16(1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd)
);
@@ -361,7 +378,7 @@ module system_top (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
// .probe2(u_RecvTop.flag_mgc_done)
// );
// ila_ad9361_tx u_ila_ad9361_tx (
@@ -381,13 +398,13 @@ module system_top (
intr_2ps_vio_d1 <= intr_2ps_vio;
end
vio_phy_control u_vio_phy_control (
.clk (clk_1x), // input wire clk
.probe_out0(rst_manual), // output wire [0 : 0]
.probe_out1(node_id), // output wire [7 : 0]
.probe_out2(max_slot_num), // output wire [7 : 0]
.probe_out3(intr_2ps_vio), // output wire [0 : 0]
.probe_out4(tx_start_vio) // output wire [0 : 0]
.clk (clk_1x), // input wire clk
.probe_out0(flag_is_master), // output wire [0 : 0]
.probe_out1(bb_tx_iq_reverse), // output wire [0 : 0]
.probe_out2(bb_rx_iq_reverse) // output wire [0 : 0]
);