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fix(top): reverse iq in recv

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ZoroGH
2024-08-02 20:51:37 +08:00
parent 92583b785c
commit 145e8c0930
11 changed files with 1918 additions and 569 deletions
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hdl/tdma.v
+50 -22
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@@ -14,29 +14,36 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter SLOT_LEN = 1250000,
parameter TIC_TO_PS_LEN = 1200000,
parameter TIC_FRAME_SYNC = 42272
parameter SLOT_LEN = 750000,
parameter TIC_TO_PS_LEN = 700000,
parameter TIC_FRAME_SYNC = 42344
) (
input clk,
input rst,
input flag_is_master, // TODO: refactor it to parameters
input flag_frame_sync,
output intr_2ps,
(* KEEP = "TRUE" *) output tx_start,
(* KEEP = "TRUE" *) output rx_rst
input clk,
input rst,
input flag_is_master, // TODO: refactor it to parameters
input flag_frame_sync,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg [23:0] cnt;
// ******** Assingment ********
assign tx_start = flag_is_master & (cnt == 16'd10);
assign intr_2ps = flag_is_master & (cnt == TIC_TO_PS_LEN - 1);
// ******** Logic Block ********
reg [23:0] cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
@@ -48,7 +55,7 @@ module tdma #(
end
else begin
// master
if (cnt < SLOT_LEN) begin
if (cnt < SLOT_LEN - 1) begin
cnt <= cnt + 1;
end
else begin
@@ -57,26 +64,47 @@ module tdma #(
end
end
end
assign tx_start = flag_is_tx_slot & (cnt == 16'd10);
assign rx_rst = flag_is_tx_slot | (~flag_is_tx_slot & (cnt <= 16'd10));
assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
always @(posedge clk) begin
if (rst) begin
flag_is_tx_slot <= 0;
if (flag_is_master) begin
rx_rst <= 1;
end
else if (!flag_is_master && flag_frame_sync) begin
flag_is_tx_slot <= 0;
end
else if (cnt == 16'd1) begin
flag_is_tx_slot <= ~flag_is_tx_slot;
else begin
rx_rst <= flag_is_master | (cnt <= 16'd4);
end
end
// always @(posedge clk) begin
// if (rst) begin
// flag_is_tx_slot <= 0;
// end
// else if (!flag_is_master && flag_frame_sync) begin
// flag_is_tx_slot <= 0;
// end
// else if (cnt == 16'd1) begin
// flag_is_tx_slot <= ~flag_is_tx_slot;
// end
// end
// ******** Inst ********
// ******** Debug ********
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(flag_is_master), // width: 1
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync) // width: 1
);
endmodule