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fix(top): reverse iq in recv

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ZoroGH
2024-08-02 20:51:37 +08:00
parent 92583b785c
commit 145e8c0930
11 changed files with 1918 additions and 569 deletions
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sim/tb_tdma.v
+10 -45
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@@ -22,60 +22,25 @@
module tb_tdma ();
reg clk = 1;
reg clk_tx = 1;
reg rst = 1;
always #1 clk <= ~clk;
initial begin
#1000 rst <= 1'b0;
#10 rst <= 1'b0;
end
wire flag_frame_sync_m;
reg flag_frame_sync_s = 0;
wire intr_2ps_m;
wire intr_2ps_s;
wire tic_hop_m;
wire tic_hop_s;
wire tx_start_m;
wire tx_start_s;
assign flag_frame_sync_m = 1'b0;
tdma #(
.SLOT_LEN (1250000),
.TIC_TO_PS_LEN (1200000),
.TIC_FRAME_SYNC(42272)
) u_tdma_master (
.SLOT_LEN (625000), // 50MHz--> 15ms
.TIC_TO_PS_LEN (575000),
.TIC_FRAME_SYNC(42344)
) u_tdma (
.clk (clk),
.rst (rst),
.flag_is_master (1'b1),
.flag_frame_sync(flag_frame_sync_m),
.intr_2ps (intr_2ps_m),
// .tic_hop (tic_hop_m),
.tx_start (tx_start_m)
.flag_is_master (1),
.flag_frame_sync(0),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
tdma #(
.SLOT_LEN (20000),
.TIC_TO_PS_LEN (18000),
.TIC_FRAME_SYNC(2000)
) u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_is_master (1'b0),
.flag_frame_sync(flag_frame_sync_s),
.intr_2ps (intr_2ps_s),
// .tic_hop (tic_hop_s),
.tx_start (tx_start_s)
);
initial begin
#12000 flag_frame_sync_s <= 1'b1;
#3 flag_frame_sync_s <= 1'b0;
end
endmodule