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tdma module tx_start signal is set high wrongly when slot number = 1 and id !=1
tdma module tx_start signal is set high wrongly when slot number = 1 and id !=1
update ps logic, intr2ps signal will be trigger at the end of the slot while the next slot is the send slot
ZoroGH
released perf(sys): delete some ila, optimize timing at ZoroGH/MM7020
2024-10-14 13:28:24 +08:00
tdma module tx_start signal is set high wrongly when slot number = 1 and id !=1