 josh
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a8ea62ab3d
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add zc706_cx9261a_demo vitis project, hop function needs further development
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2024-10-25 15:17:18 +08:00 |
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josh
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9103a45487
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add zc706_cx9261a_demo vivado project
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2024-10-25 15:15:51 +08:00 |
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josh
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10d102245f
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test ad9361_mapping with vcs, update broken file
xc7k410tffg900-2_ad9361_mapping
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2024-10-16 17:58:14 +08:00 |
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josh
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a9c307dab3
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update ad9361 mapping
cmos mode works fine, but the timing of lvds mode needs more test
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2024-10-11 19:22:14 +08:00 |
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josh
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c4b23c89ed
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update dj_47dr_demo, including lmx constraints and axi spi engine miso line number
dj_47dr_20240711
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2024-07-05 15:00:07 +08:00 |
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josh
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bbc5e544a1
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update dj_47dr_lmx vitis project
decrease spi speed to garantee valid readback, disable lmx2594 ramp config, update some comments
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2024-07-05 11:39:44 +08:00 |
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josh
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5f6348942f
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update dj_47dr_lmx vivado project
change axi spi engine miso line number to 1, miso is now selected based on cs
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2024-07-05 11:35:10 +08:00 |
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josh
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81467ace82
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add dj_47dr_lmx vitis project
refer to readme for details
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2024-07-04 20:32:14 +08:00 |
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josh
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8f5171133e
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add dj_47dr_lmx vivado project
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2024-07-04 20:25:32 +08:00 |
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josh
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5a9cb91186
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update dj_47dr_ibert vivado project, will not affect vitis project
update some paths to current ones
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2024-07-02 16:10:06 +08:00 |
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josh
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86ccfd5cc6
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git add dr_47dr_ibert vitis project, with basic rfdc function
boot image is created, and start-up test is passed
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2024-07-02 14:15:33 +08:00 |
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josh
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c2e411b8fb
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add dj_47dr vivado ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
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2024-07-02 14:14:35 +08:00 |
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josh
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9ac4c532f3
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add dj_47dr_z7045 vitis fsbl project
boot image is created, and start-up test is passed
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2024-07-02 14:13:03 +08:00 |
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josh
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3aac7f01b6
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add dj_47dr_z7045 ibert project
ibert line rate 9.6 Gbps, refclk 150 MHz
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2024-07-02 14:10:41 +08:00 |
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josh
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47a1b38997
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update dj_47dr ps project, add tcp performance server project
refer to readme.md for details
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2024-07-01 19:27:23 +08:00 |
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josh
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0dcb823314
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add ax7020 pl project, including mpsoc bd core only
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2024-07-01 19:26:17 +08:00 |
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josh
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66f574fef7
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update dj_47dr pl, add ttc to mpsoc bd core
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2024-07-01 19:14:06 +08:00 |
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josh
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6a4af4fb55
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add rfsoc_eval vitis project, refer to readme for details
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2024-07-01 14:31:21 +08:00 |
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josh
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fad0306d82
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add rfsoc_eval pl project
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2024-06-29 00:11:59 +08:00 |
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josh
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cec690b984
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add dj_47dr vitis projects, refer to readme within each project for details
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2024-06-28 23:06:09 +08:00 |
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josh
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0eead518df
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add dj_47dr pl project, set .dcp as large file type
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2024-06-28 22:24:04 +08:00 |
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josh
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3b6d109c4c
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update gitignore, add .bin file as large lfs
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2024-06-28 22:08:24 +08:00 |
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josh
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dbc7dddc19
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upgrade ad9361_mapping to vivado 2024.1
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2024-06-21 10:10:46 +08:00 |
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josh
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24cc6b9ee9
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update adi_library to vivado 2024.1
compile adi_library with latest hdl commit and vivado 2024.1
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2024-06-06 11:22:50 +08:00 |
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josh
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3c6c573f6a
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add var_cal module for xc7k410tffg900-2
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2024-01-30 10:35:26 +08:00 |
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josh
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a1680685ed
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add tx_qpsk module for xc7k410tffg900-2
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2024-01-30 10:35:16 +08:00 |
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josh
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9eea2b693a
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add multi_ch_cal module for xc7k410tffg900-2
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2024-01-30 10:35:04 +08:00 |
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josh
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5defedcc88
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add ad9361_mapping module for xc7k410tffg900-2
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2024-01-30 10:34:36 +08:00 |
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josh
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118ade226e
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add modules
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2024-01-24 21:56:47 +08:00 |
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josh
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8c68cb519e
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add xilinx spi examlpe with ax7020
refer to projects/ax7020/ax7020_spi_loopback/README.md for detailed information
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2024-01-24 20:14:55 +08:00 |
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josh
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7d18b23b4f
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update gitignore for projects
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2024-01-24 20:12:56 +08:00 |
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josh
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2ac35fe4e6
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add readme
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2024-01-24 11:23:15 +08:00 |
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josh
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315a673005
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initial commit, add dds_par module
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2024-01-15 09:36:08 +08:00 |
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