refactor(recviver): simulation pass for ila data

sim/tb_Receiver.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 

sim/tb_led.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 

sim/tb_recv_top.v

@@ -0,0 +1,76 @@
+`timescale 1ns / 1ns
+module tb_recv_top ();
+
+    reg clk = 0;
+    reg clk_2x = 0;
+    reg clk_4x = 0;
+    reg rst = 1;
+
+    always #(4) clk = ~clk;
+    always #(2) clk_2x = ~clk_2x;
+    always #(1) clk_4x = ~clk_4x;
+
+    initial begin
+        #20 rst <= 0;
+    end
+
+    reg signed [11:0] ad9361_rx_data_i;
+    reg signed [11:0] ad9361_rx_data_q;
+    reg        [ 9:0] k1;
+    reg        [ 9:0] k2;
+    reg        [11:0] mem_i            [0:637049];
+    reg        [11:0] mem_q            [0:637049];
+
+    initial begin
+        $readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_i2_new2.txt", mem_i);
+        $readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_q2_new2.txt", mem_q);
+        $display("Read mem done ");
+    end
+
+    // reg [31:0] idx = 46500 - 8000;
+    reg [31:0] idx = 0;
+
+    always @(posedge clk) begin
+        idx <= idx + 1;
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            ad9361_rx_data_i <= 0;
+            ad9361_rx_data_q <= 0;
+            k1               <= 0;
+            k2               <= 0;
+        end
+        else begin
+            ad9361_rx_data_i <= $signed(k1);
+            ad9361_rx_data_q <= $signed(k2);
+            k1               <= mem_i[idx];
+            k2               <= mem_q[idx];
+        end
+    end
+
+
+
+
+    RecvTop u_RecvTop (
+        .clk              (clk),
+        .clk_2x           (clk_2x),
+        .clk_4x           (clk_4x),
+        .rst              (rst),
+        .rst2             (rst),
+        .dini             (ad9361_rx_data_i),
+        .dinq             (ad9361_rx_data_q),
+        .ad9361_ctrl_in   (),
+        .vio_tsync_inter16(1),
+        .EQUenable_vio    (1),
+        .Zerozone_vio     (8'd29),
+        .vio_stopbit      (7'd60),
+        .flag_stop        (flag_stop),
+        .addr_stop        (addr_stop),
+        .recvNetData      (recvNetData),
+        .recvNetDataNd    (recvNetDataNd)
+    );
+
+
+
+endmodule

sim/tb_tdma.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 //////////////////////////////////////////////////////////////////////////////////
 // Company: 
 // Engineer: 

sim/tb_width_convert.v

@@ -1,4 +1,4 @@
-`timescale 1ns / 1ps
+`timescale 1ns / 1ns
 module tb_width_convert ();