refactor(recviver): simulation pass for ila data
This commit is contained in:
@@ -2,3 +2,4 @@ adi_library
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c/**
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ip
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.tags
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sim/sim_data
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@@ -1,4 +1,4 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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+1
-1
@@ -1,4 +1,4 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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@@ -0,0 +1,145 @@
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: CCSDS_LDPC_DEC_K1024_R12
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CCSDS_LDPC_DEC_K1024_R12 #(
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parameter WIDTH = 4'd8,
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parameter MAX_ITER_NUM = 6'd14,
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parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
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) (
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input clk, //工作时钟,100MHz
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input Rst, //同步复位信号,高有效
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input FrameSync, //帧同步标志,高脉冲
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input Nd, //译码输入数据有效标志,高有效
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input [WIDTH-1:0] Din, //译码输入数据,软信息,数据速率约为12.5Mbps
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output reg LDPC_SyncOut = 1'b0, //LDPC模块帧同步输出信号,高脉冲,指示帧起点
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output reg Rdy = 1'b0, //译码输出信号有效标志,高有效
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output reg [0:0] LDPC_Dout = 1'b0, //译码输出信号
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output reg [8:0] good_frames = 9'd0, //译码好帧计数
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output reg [8:0] bad_frames = 9'd0, //译码坏帧计数
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output reg [8:0] total_frames = 9'd0 //译码总帧计数
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);
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reg rst_MS = 1'd0;
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reg framesync_MS = 1'd0;
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reg nd_MS = 1'd0;
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reg [WIDTH-1:0] din_MS = 8'd0;
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reg oe_MS = 1'd0;
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wire deal_end_MS;
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wire [WIDTH-1:0] dout01_MS;
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wire [WIDTH-1:0] dout02_MS;
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wire [WIDTH-1:0] dout03_MS;
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wire [WIDTH-1:0] dout04_MS;
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always @(posedge clk) begin
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rst_MS <= Rst;
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framesync_MS <= FrameSync;
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nd_MS <= Nd;
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din_MS <= Din;
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end
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//******输入数据的缓存模块
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Message_Store #(
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.WIDTH(WIDTH)
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) MS (
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.clk (clk),
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.rst_MS (rst_MS),
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.framesync_MS(framesync_MS),
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.nd_MS (nd_MS),
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.din_MS (din_MS),
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.oe_MS (oe_MS),
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.deal_end_MS (deal_end_MS),
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.syncout_MS (syncout_MS),
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.rdy_MS (rdy_MS),
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.dout01_MS (dout01_MS),
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.dout02_MS (dout02_MS),
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.dout03_MS (dout03_MS),
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.dout04_MS (dout04_MS)
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);
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reg rst = 1'd0;
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reg start = 1'd0;
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reg framesync = 1'd0;
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reg nd = 1'd0;
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reg [WIDTH-1:0] din01 = 8'd0;
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reg [WIDTH-1:0] din02 = 8'd0;
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reg [WIDTH-1:0] din03 = 8'd0;
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reg [WIDTH-1:0] din04 = 8'd0;
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wire ask_din;
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wire [ 8:0] gd_frames;
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wire [ 8:0] bd_frames;
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wire [ 8:0] tl_frames;
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wire ldpc_syncout;
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wire rdy;
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wire [ 0:0] ldpc_dout;
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always @(posedge clk) begin
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rst <= Rst;
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start <= deal_end_MS;
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framesync <= syncout_MS;
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nd <= rdy_MS;
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din01 <= dout01_MS;
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din02 <= dout02_MS;
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din03 <= dout03_MS;
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din04 <= dout04_MS;
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oe_MS <= ask_din;
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end
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// TOP层译码器输出
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always @(posedge clk) begin
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LDPC_SyncOut <= ldpc_syncout;
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Rdy <= rdy;
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LDPC_Dout <= ldpc_dout;
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good_frames <= gd_frames;
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bad_frames <= bd_frames;
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total_frames <= tl_frames;
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end
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LDPC_DEC_PRO //译码器的吞吐量=(信息比特数/(一次迭代所需的时钟数*迭代次数))*FPGA工作主频
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#(
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.MAX_ITER_NUM(MAX_ITER_NUM),
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.WIDTH(WIDTH),
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.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
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) LDPC_DEC (
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.clk (clk),
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.rst (rst),
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.start (start),
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.framesync (framesync),
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.nd (nd),
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.din01 (din01),
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.din02 (din02),
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.din03 (din03),
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.din04 (din04),
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.ask_din (ask_din),
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.gd_frames (gd_frames),
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.bd_frames (bd_frames),
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.tl_frames (tl_frames),
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.ldpc_syncout(ldpc_syncout),
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.rdy (rdy),
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.ldpc_dout (ldpc_dout)
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);
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endmodule
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@@ -1,4 +1,4 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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@@ -1,4 +1,4 @@
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`timescale 1ns / 1ps
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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+386
@@ -0,0 +1,386 @@
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`timescale 1ns / 1ns
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2019/11/18 23:18:07
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// Design Name:
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// Module Name: CK_PRO
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module CK_PRO
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#(
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parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,
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parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,
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parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,
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parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,
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parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec_08_01=31,Index_p2_row_01_dec_07_01=39,
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parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec_05_01=23,Index_p2_row_02_dec_08_01=16,
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parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec_06_01=54,Index_p2_row_03_dec_05_01=0,
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parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec_07_01=9, Index_p2_row_04_dec_06_01=83,
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parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec_11_01=97, Index_p3_row_01_dec_10_01=0, Index_p3_row_01_dec_12_01=34,
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parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec_12_01=64, Index_p3_row_02_dec_11_01=6, Index_p3_row_02_dec_09_01=98,
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parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec_09_01=78, Index_p3_row_03_dec_12_01=35, Index_p3_row_03_dec_10_01=26,
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parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec_10_01=81, Index_p3_row_04_dec_09_01=99, Index_p3_row_04_dec_11_01=59
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)
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(
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input clk,
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input rst_OUTCK,
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input start_OUTCK,
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input nd_OUTCK,
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input [0:0] DR_din_01,
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input [0:0] DR_din_02,
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input [0:0] DR_din_03,
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input [0:0] DR_din_04,
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input [0:0] DR_din_05,
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output reg [8:0] gd_frames=9'd0,//译码好帧计数
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output reg [8:0] bd_frames=9'd0,//译码坏帧计数
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output reg [8:0] tl_frames=9'd0 //译码总帧数计数
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);
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reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;
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reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;
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reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;
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reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;
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reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;
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reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;
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reg [10:0] cnt_CK=11'd0;
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reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_end_d5=1'd0,dec_proc=1'd0;
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// 产生本模块的计数器
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always @ (posedge clk) begin
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if (rst_OUTCK) begin
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dec_proc <= 1'd0;
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cnt_CK <= 11'd0;
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end else begin
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if (start_OUTCK) begin
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dec_proc <= 1'd1;
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cnt_CK <= 11'd0;
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end else begin
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if (dec_proc) begin
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if (cnt_CK < 11'd560) begin
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cnt_CK <= cnt_CK + 11'd1;
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dec_proc <= dec_proc;
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end else begin
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cnt_CK <= cnt_CK;
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dec_proc <= 1'd0;
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end
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end else begin
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cnt_CK <= cnt_CK;
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end
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end
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end
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end
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parameter DELAY_DIN = 11'd0;
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always @ (posedge clk) begin
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if (rst_OUTCK || start_OUTCK) begin
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dec_01 <= 128'd0; dec_01_d1 <= 128'd0;
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dec_02 <= 128'd0; dec_02_d1 <= 128'd0;
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dec_03 <= 128'd0; dec_03_d1 <= 128'd0;
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dec_04 <= 128'd0; dec_04_d1 <= 128'd0;
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dec_05 <= 128'd0; dec_05_d1 <= 128'd0;
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dec_06 <= 128'd0; dec_06_d1 <= 128'd0;
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dec_07 <= 128'd0; dec_07_d1 <= 128'd0;
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dec_08 <= 128'd0; dec_08_d1 <= 128'd0;
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dec_09 <= 128'd0; dec_09_d1 <= 128'd0;
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dec_10 <= 128'd0; dec_10_d1 <= 128'd0;
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dec_11 <= 128'd0; dec_11_d1 <= 128'd0;
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dec_12 <= 128'd0; dec_12_d1 <= 128'd0;
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deal_end <= 1'd0;
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end else begin
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// 本来3行5列的H矩阵转置后变成5行3列
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// 第1列（4*128=512）个校验子求解过程
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if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
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dec_01[Index_p1_row_01_dec_01_01] <= DR_din_03 ^ DR_din_05;
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dec_02[Index_p1_row_01_dec_02_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
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dec_01[Index_p1_row_01_dec_01_01] <= 1'd0;
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dec_02[Index_p1_row_02_dec_02_01] <= DR_din_03 ^ DR_din_05;
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dec_03[Index_p1_row_02_dec_03_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
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dec_03[Index_p1_row_03_dec_03_01] <= DR_din_03 ^ DR_din_05;
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dec_04[Index_p1_row_03_dec_04_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
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dec_04[Index_p1_row_04_dec_04_01] <= DR_din_03 ^ DR_din_05;
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dec_01[Index_p1_row_04_dec_01_01] <= DR_din_05;
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end else begin
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dec_01 <= dec_01;
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dec_02 <= dec_02;
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dec_03 <= dec_03;
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dec_04 <= dec_04;
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end
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if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
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end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
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end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
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end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
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end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
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dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]};
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dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]};
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dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]};
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dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]};
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end else begin
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dec_01_d1 <= dec_01_d1;
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dec_02_d1 <= dec_02_d1;
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dec_03_d1 <= dec_03_d1;
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dec_04_d1 <= dec_04_d1;
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deal_end <= 1'd0;
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end
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// 第2列（4*128=512）个校验子求解过程
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if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
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dec_05[Index_p2_row_01_dec_05_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_05[Index_p2_row_01_dec_05_02] <= DR_din_05;
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dec_08[Index_p2_row_01_dec_08_01] <= DR_din_05;
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dec_07[Index_p2_row_01_dec_07_01] <= DR_din_05;
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end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
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dec_06[Index_p2_row_02_dec_06_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_06[Index_p2_row_02_dec_06_02] <= DR_din_05;
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dec_05[Index_p2_row_02_dec_05_01] <= DR_din_05;
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dec_05[Index_p2_row_01_dec_05_01] <= 1'd0;
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dec_05[Index_p2_row_01_dec_05_02] <= 1'd0;
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dec_08[Index_p2_row_02_dec_08_01] <= DR_din_05;
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dec_08[Index_p2_row_01_dec_08_01] <= 1'd0;
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dec_07[Index_p2_row_01_dec_07_01] <= 1'd0; //xhx
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end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
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dec_07[Index_p2_row_03_dec_07_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
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dec_07[Index_p2_row_03_dec_07_02] <= DR_din_05;
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dec_06[Index_p2_row_03_dec_06_01] <= DR_din_05;
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dec_06[Index_p2_row_02_dec_06_01] <= 1'd0;
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dec_06[Index_p2_row_02_dec_06_02] <= 1'd0;
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||||
dec_05[Index_p2_row_03_dec_05_01] <= DR_din_05;
|
||||
dec_05[Index_p2_row_02_dec_05_01] <= 1'd0;
|
||||
dec_08[Index_p2_row_02_dec_08_01] <= 1'd0; //xhx
|
||||
end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
|
||||
dec_08[Index_p2_row_04_dec_08_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
|
||||
dec_08[Index_p2_row_04_dec_08_02] <= DR_din_05;
|
||||
dec_07[Index_p2_row_04_dec_07_01] <= DR_din_05;
|
||||
dec_07[Index_p2_row_03_dec_07_01] <= 1'd0;
|
||||
dec_07[Index_p2_row_03_dec_07_02] <= 1'd0;
|
||||
dec_06[Index_p2_row_04_dec_06_01] <= DR_din_05;
|
||||
dec_06[Index_p2_row_03_dec_06_01] <= 1'd0;
|
||||
dec_05[Index_p2_row_03_dec_05_01] <= 1'd0; //xhx
|
||||
end else begin
|
||||
dec_05 <= dec_05;
|
||||
dec_06 <= dec_06;
|
||||
dec_07 <= dec_07;
|
||||
dec_08 <= dec_08;
|
||||
end
|
||||
|
||||
if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]};
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]};
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]};
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]};
|
||||
end else begin
|
||||
dec_05_d1 <= dec_05_d1;
|
||||
dec_06_d1 <= dec_06_d1;
|
||||
dec_07_d1 <= dec_07_d1;
|
||||
dec_08_d1 <= dec_08_d1;
|
||||
end
|
||||
|
||||
|
||||
// 第3列（4*128=512）个校验子求解过程
|
||||
if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
|
||||
dec_09[Index_p3_row_01_dec_09_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_09[Index_p3_row_01_dec_09_02] <= DR_din_04;
|
||||
dec_11[Index_p3_row_01_dec_11_01] <= DR_din_02;
|
||||
dec_10[Index_p3_row_01_dec_10_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_01_dec_12_01] <= DR_din_04;
|
||||
end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
|
||||
dec_10[Index_p3_row_02_dec_10_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_10[Index_p3_row_02_dec_10_02] <= DR_din_04;
|
||||
dec_12[Index_p3_row_02_dec_12_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_01_dec_12_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_02_dec_11_01] <= DR_din_02;
|
||||
dec_11[Index_p3_row_01_dec_11_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_02_dec_09_01] <= DR_din_04;
|
||||
dec_09[Index_p3_row_01_dec_09_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_01_dec_09_02] <= 1'd0;
|
||||
end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
|
||||
dec_11[Index_p3_row_03_dec_11_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_11[Index_p3_row_03_dec_11_02] <= DR_din_04;
|
||||
dec_11[Index_p3_row_02_dec_11_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_03_dec_09_01] <= DR_din_02;
|
||||
dec_09[Index_p3_row_02_dec_09_01] <= 1'd0;
|
||||
dec_12[Index_p3_row_03_dec_12_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_02_dec_12_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_03_dec_10_01] <= DR_din_04;
|
||||
dec_10[Index_p3_row_02_dec_10_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_02_dec_10_02] <= 1'd0;
|
||||
end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
|
||||
dec_12[Index_p3_row_04_dec_12_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_12[Index_p3_row_04_dec_12_02] <= DR_din_04;
|
||||
dec_12[Index_p3_row_03_dec_12_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_04_dec_10_01] <= DR_din_02;
|
||||
dec_10[Index_p3_row_03_dec_10_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_04_dec_09_01] <= DR_din_02;
|
||||
dec_09[Index_p3_row_03_dec_09_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_04_dec_11_01] <= DR_din_04;
|
||||
dec_11[Index_p3_row_03_dec_11_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_03_dec_11_02] <= 1'd0;
|
||||
end else begin
|
||||
dec_09 <= dec_09;
|
||||
dec_10 <= dec_10;
|
||||
dec_11 <= dec_11;
|
||||
dec_12 <= dec_12;
|
||||
end
|
||||
|
||||
if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]};
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]};
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]};
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]};
|
||||
end else begin
|
||||
dec_09_d1 <= dec_09_d1;
|
||||
dec_10_d1 <= dec_10_d1;
|
||||
dec_11_d1 <= dec_11_d1;
|
||||
dec_12_d1 <= dec_12_d1;
|
||||
end
|
||||
|
||||
// 产生标志位
|
||||
if (cnt_CK == 11'd514 + DELAY_DIN)
|
||||
deal_end <= 1'd1;
|
||||
else
|
||||
deal_end <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
//2019.02.28添加：打一拍，尝试避免时序问题
|
||||
reg deal_end_d6 = 1'd0;
|
||||
reg flag_judge1 = 1'd0;
|
||||
reg flag_judge2 = 1'd0;
|
||||
reg flag_judge3 = 1'd0;
|
||||
always@(posedge clk) begin
|
||||
if(rst_OUTCK) begin
|
||||
flag_judge1 <= 1'd0;
|
||||
flag_judge2 <= 1'd0;
|
||||
flag_judge3 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(deal_end_d5) begin
|
||||
if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 ) flag_judge1 <= 1'd0;
|
||||
else flag_judge1 <= 1'd1;
|
||||
if(dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 ) flag_judge2 <= 1'd0;
|
||||
else flag_judge2 <= 1'd1;
|
||||
if(dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) flag_judge3 <= 1'd0;
|
||||
else flag_judge3 <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
flag_judge1 <= flag_judge1;
|
||||
flag_judge2 <= flag_judge2;
|
||||
flag_judge3 <= flag_judge3;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(rst_OUTCK) begin
|
||||
gd_frames <= 9'd0;
|
||||
bd_frames <= 9'd0;
|
||||
tl_frames <= 9'd0;
|
||||
deal_end_d1 <= 1'd0;
|
||||
deal_end_d2 <= 1'd0;
|
||||
deal_end_d3 <= 1'd0;
|
||||
deal_end_d4 <= 1'd0;
|
||||
deal_end_d5 <= 1'd0;
|
||||
deal_end_d6 <= 1'd0; //2019.02.28添加
|
||||
end else begin
|
||||
deal_end_d1 <= deal_end;
|
||||
deal_end_d2 <= deal_end_d1;
|
||||
deal_end_d3 <= deal_end_d2;
|
||||
deal_end_d4 <= deal_end_d3;
|
||||
deal_end_d5 <= deal_end_d4;
|
||||
deal_end_d6 <= deal_end_d5; //2019.02.28添加
|
||||
if(deal_end_d6) begin
|
||||
if(flag_judge1 == 1'd0 && flag_judge2 == 1'd0 && flag_judge3 == 1'd0 ) begin
|
||||
// if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 &&
|
||||
// dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 &&
|
||||
// dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) begin
|
||||
gd_frames <= gd_frames + 9'd1;
|
||||
bd_frames <= bd_frames;
|
||||
tl_frames <= tl_frames + 9'd1;
|
||||
end else begin
|
||||
gd_frames <= gd_frames;
|
||||
bd_frames <= bd_frames + 9'd1;
|
||||
tl_frames <= tl_frames + 9'd1;
|
||||
end
|
||||
end else begin
|
||||
gd_frames <= gd_frames;
|
||||
bd_frames <= bd_frames;
|
||||
tl_frames <= tl_frames;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CNU_3din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CNU_3din
|
||||
#(parameter WIDTH = 4'd8)(
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din02_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din03_VN_RU, //变量节点信息输入
|
||||
|
||||
output reg [WIDTH-1:0] dout01_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout02_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout03_RU=8'd0 //更新输出
|
||||
);//输出相对输入延时9个clk
|
||||
|
||||
reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0;
|
||||
reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0;
|
||||
reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//求输入数据的绝对值过程
|
||||
if(din01_VN_RU[WIDTH-1]) abs01 <= ~din01_VN_RU + 8'd1;else abs01 <= din01_VN_RU;
|
||||
if(din02_VN_RU[WIDTH-1]) abs02 <= ~din02_VN_RU + 8'd1;else abs02 <= din02_VN_RU;
|
||||
if(din03_VN_RU[WIDTH-1]) abs03 <= ~din03_VN_RU + 8'd1;else abs03 <= din03_VN_RU;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
abs01_reg0 <= abs01; abs01_reg1 <= abs01_reg0;
|
||||
abs02_reg0 <= abs02; abs02_reg1 <= abs02_reg0;
|
||||
abs03_reg0 <= abs03; abs03_reg1 <= abs03_reg0;
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] min_level_1_01=8'd0,min_level_1_02=8'd0;
|
||||
reg [WIDTH-1:0] min_level_2_01=8'd0,min_level_2_02=8'd0;
|
||||
always @ (posedge clk) begin//第1级分类，两两一组将最小及次小值分开
|
||||
min_level_1_01 <= (abs01 < abs02) ? abs01:abs02;
|
||||
min_level_1_02 <= (abs01 < abs02) ? abs02:abs01;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
min_level_2_01 <= (abs03_reg0<min_level_1_01) ? abs03_reg0:min_level_1_01;
|
||||
min_level_2_02 <= (abs03_reg0<min_level_1_01) ? min_level_1_01:((abs03_reg0<min_level_1_02)? abs03_reg0 : min_level_1_02);
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] abs01_update=8'd0,abs02_update=8'd0,abs03_update=8'd0;
|
||||
always @ (posedge clk) begin//各绝对值的最小值及次小值更新
|
||||
abs01_update <= (abs01_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
abs02_update <= (abs02_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
abs03_update <= (abs03_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] dout_abs_NF01,dout_abs_NF02,dout_abs_NF03;
|
||||
//*****对更新后的非负数修正，系数为0.8125
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(dout_abs_NF01));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(dout_abs_NF02));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(dout_abs_NF03));
|
||||
|
||||
|
||||
reg [2:0] sgn=3'd0,sgn_reg0=3'd0;
|
||||
always @ (posedge clk) begin//求输入数据的符号位及其流水延时过程
|
||||
sgn[2:0] <= {din01_VN_RU[WIDTH-1],din02_VN_RU[WIDTH-1],din03_VN_RU[WIDTH-1]};
|
||||
sgn_reg0 <= sgn;
|
||||
end
|
||||
|
||||
reg xor_level_1_01=1'd0;
|
||||
always @ (posedge clk) begin//求所有符号位异或和的过程
|
||||
xor_level_1_01 <= sgn[0] ^ sgn[1] ^ sgn[2];
|
||||
end
|
||||
|
||||
reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn_update_reg3=3'd0;
|
||||
always @ (posedge clk) begin //更新所有符号位及结果流水延时过程
|
||||
sgn_update[2:0] <= sgn_reg0^{3{xor_level_1_01}};
|
||||
sgn_update_reg0 <= sgn_update;
|
||||
sgn_update_reg1 <= sgn_update_reg0;
|
||||
sgn_update_reg2 <= sgn_update_reg1;
|
||||
sgn_update_reg3 <= sgn_update_reg2;
|
||||
end
|
||||
reg [WIDTH-1:0] dout01_RU_temp=8'd0,dout02_RU_temp=8'd0,dout03_RU_temp=8'd0;
|
||||
always @ (posedge clk) begin //计算最终更新结果的过程（符号位+绝对值）
|
||||
dout01_RU_temp <= (sgn_update_reg3[2]) ? {sgn_update_reg3[2],~dout_abs_NF01[WIDTH-2:0]+8'd1} : {sgn_update_reg3[2],dout_abs_NF01[WIDTH-2:0]};
|
||||
dout02_RU_temp <= (sgn_update_reg3[1]) ? {sgn_update_reg3[1],~dout_abs_NF02[WIDTH-2:0]+8'd1} : {sgn_update_reg3[1],dout_abs_NF02[WIDTH-2:0]};
|
||||
dout03_RU_temp <= (sgn_update_reg3[0]) ? {sgn_update_reg3[0],~dout_abs_NF03[WIDTH-2:0]+8'd1} : {sgn_update_reg3[0],dout_abs_NF03[WIDTH-2:0]};
|
||||
|
||||
dout01_RU <= dout01_RU_temp;
|
||||
dout02_RU <= dout02_RU_temp;
|
||||
dout03_RU <= dout03_RU_temp;
|
||||
end
|
||||
endmodule
|
||||
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CNU_6din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
module CNU_6din
|
||||
#(parameter WIDTH = 4'd8)
|
||||
(//输入数据个数为10的行更新模块，包括符号更新
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din02_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din03_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din04_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din05_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din06_VN_RU, //变量节点信息输入
|
||||
|
||||
output reg [WIDTH-1:0] dout01_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout02_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout03_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout04_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout05_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout06_RU=8'd0 //更新输出
|
||||
); //输出相对输入延时9个clk
|
||||
reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'd0;
|
||||
reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'd0;
|
||||
reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'd0;
|
||||
reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'd0;
|
||||
reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'd0;
|
||||
reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'd0;
|
||||
|
||||
wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;
|
||||
|
||||
always @ (posedge clk) begin//求输入数据的绝对值过程
|
||||
if(din01_VN_RU[WIDTH-1]) abs01 <= ~din01_VN_RU + 8'd1;else abs01 <= din01_VN_RU;
|
||||
if(din02_VN_RU[WIDTH-1]) abs02 <= ~din02_VN_RU + 8'd1;else abs02 <= din02_VN_RU;
|
||||
if(din03_VN_RU[WIDTH-1]) abs03 <= ~din03_VN_RU + 8'd1;else abs03 <= din03_VN_RU;
|
||||
if(din04_VN_RU[WIDTH-1]) abs04 <= ~din04_VN_RU + 8'd1;else abs04 <= din04_VN_RU;
|
||||
if(din05_VN_RU[WIDTH-1]) abs05 <= ~din05_VN_RU + 8'd1;else abs05 <= din05_VN_RU;
|
||||
if(din06_VN_RU[WIDTH-1]) abs06 <= ~din06_VN_RU + 8'd1;else abs06 <= din06_VN_RU;
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk) begin//对绝对值流水延时
|
||||
abs01_reg0 <= abs01; abs01_reg1 <= abs01_reg0; abs01_reg2 <= abs01_reg1;
|
||||
abs02_reg0 <= abs02; abs02_reg1 <= abs02_reg0; abs02_reg2 <= abs02_reg1;
|
||||
abs03_reg0 <= abs03; abs03_reg1 <= abs03_reg0; abs03_reg2 <= abs03_reg1;
|
||||
abs04_reg0 <= abs04; abs04_reg1 <= abs04_reg0; abs04_reg2 <= abs04_reg1;
|
||||
abs05_reg0 <= abs05; abs05_reg1 <= abs05_reg0; abs05_reg2 <= abs05_reg1;
|
||||
abs06_reg0 <= abs06; abs06_reg1 <= abs06_reg0; abs06_reg2 <= abs06_reg1;
|
||||
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] min_level_1_05_reg0=8'd0,min_level_1_06_reg0=8'd0;
|
||||
always @ (posedge clk) begin
|
||||
min_level_1_05_reg0 <= min_level_1_05;
|
||||
min_level_1_06_reg0 <= min_level_1_06;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//第1级分类，两两一组将最小及次小值分开
|
||||
min_level_1_01 <= (abs01<abs02) ? abs01 : abs02; min_level_1_02 <= (abs01<abs02) ? abs02 : abs01;
|
||||
min_level_1_03 <= (abs03<abs04) ? abs03 : abs04; min_level_1_04 <= (abs03<abs04) ? abs04 : abs03;
|
||||
min_level_1_05 <= (abs05<abs06) ? abs05 : abs06; min_level_1_06 <= (abs05<abs06) ? abs06 : abs05;
|
||||
end
|
||||
abs_min_4din #(.WIDTH(WIDTH))inst_4din_level_1_01 (.clk(clk),.din01(min_level_1_01),.din02(min_level_1_02),.din03(min_level_1_03),.din04(min_level_1_04),.dout_min(min_level_2_01),.dout_sec(min_level_2_02));
|
||||
abs_min_4din #(.WIDTH(WIDTH))inst_4din_level_2_01 (.clk(clk),.din01(min_level_1_05_reg0),.din02(min_level_1_06_reg0),.din03(min_level_2_01),.din04(min_level_2_02),.dout_min(min_level_3_01),.dout_sec(min_level_3_02));
|
||||
|
||||
reg [WIDTH-1:0] abs01_update=8'd0;
|
||||
reg [WIDTH-1:0] abs02_update=8'd0;
|
||||
reg [WIDTH-1:0] abs03_update=8'd0;
|
||||
reg [WIDTH-1:0] abs04_update=8'd0;
|
||||
reg [WIDTH-1:0] abs05_update=8'd0;
|
||||
reg [WIDTH-1:0] abs06_update=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//各绝对值的最小值及次小值更新
|
||||
abs01_update <= (abs01_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs02_update <= (abs02_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs03_update <= (abs03_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs04_update <= (abs04_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs05_update <= (abs05_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs06_update <= (abs06_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] dout_abs_NF01;
|
||||
wire [WIDTH-1:0] dout_abs_NF02;
|
||||
wire [WIDTH-1:0] dout_abs_NF03;
|
||||
wire [WIDTH-1:0] dout_abs_NF04;
|
||||
wire [WIDTH-1:0] dout_abs_NF05;
|
||||
wire [WIDTH-1:0] dout_abs_NF06;
|
||||
|
||||
//*****对更新后的非负数修正，系数为0.8125
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(dout_abs_NF01));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(dout_abs_NF02));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(dout_abs_NF03));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF04 (.clk(clk),.din_NF(abs04_update),.dout_NF(dout_abs_NF04));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF05 (.clk(clk),.din_NF(abs05_update),.dout_NF(dout_abs_NF05));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF06 (.clk(clk),.din_NF(abs06_update),.dout_NF(dout_abs_NF06));
|
||||
|
||||
reg [5:0] sgn=6'd0,sgn_reg0=6'd0,sgn_reg1=6'd0;
|
||||
always @ (posedge clk) begin//求输入数据的符号位及其流水延时过程
|
||||
sgn[5:0] <= {din01_VN_RU[WIDTH-1],din02_VN_RU[WIDTH-1],din03_VN_RU[WIDTH-1],din04_VN_RU[WIDTH-1],din05_VN_RU[WIDTH-1],din06_VN_RU[WIDTH-1]};
|
||||
sgn_reg0 <= sgn;
|
||||
sgn_reg1 <= sgn_reg0;
|
||||
end
|
||||
|
||||
reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,xor_level_2_01=1'd0;
|
||||
always @ (posedge clk) begin//求所有符号位异或和的过程
|
||||
xor_level_1_01 <= sgn[0] ^ sgn[1] ^ sgn[2];
|
||||
xor_level_1_02 <= sgn[3] ^ sgn[4] ^ sgn[5];
|
||||
xor_level_2_01 <= xor_level_1_01 ^ xor_level_1_02;
|
||||
end
|
||||
|
||||
reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn_update_reg3=6'd0;
|
||||
always @ (posedge clk) begin //更新所有符号位及结果流水延时过程
|
||||
sgn_update[5:0] <= sgn_reg1^{6{xor_level_2_01}};
|
||||
sgn_update_reg0 <= sgn_update;
|
||||
sgn_update_reg1 <= sgn_update_reg0;
|
||||
sgn_update_reg2 <= sgn_update_reg1;
|
||||
sgn_update_reg3 <= sgn_update_reg2;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin //计算最终更新结果的过程（符号位+绝对值）
|
||||
dout01_RU <= (sgn_update_reg3[5]) ? {sgn_update_reg3[5],~dout_abs_NF01[WIDTH-2:0]+8'd1} : {sgn_update_reg3[5],dout_abs_NF01[WIDTH-2:0]};
|
||||
dout02_RU <= (sgn_update_reg3[4]) ? {sgn_update_reg3[4],~dout_abs_NF02[WIDTH-2:0]+8'd1} : {sgn_update_reg3[4],dout_abs_NF02[WIDTH-2:0]};
|
||||
dout03_RU <= (sgn_update_reg3[3]) ? {sgn_update_reg3[3],~dout_abs_NF03[WIDTH-2:0]+8'd1} : {sgn_update_reg3[3],dout_abs_NF03[WIDTH-2:0]};
|
||||
dout04_RU <= (sgn_update_reg3[2]) ? {sgn_update_reg3[2],~dout_abs_NF04[WIDTH-2:0]+8'd1} : {sgn_update_reg3[2],dout_abs_NF04[WIDTH-2:0]};
|
||||
dout05_RU <= (sgn_update_reg3[1]) ? {sgn_update_reg3[1],~dout_abs_NF05[WIDTH-2:0]+8'd1} : {sgn_update_reg3[1],dout_abs_NF05[WIDTH-2:0]};
|
||||
dout06_RU <= (sgn_update_reg3[0]) ? {sgn_update_reg3[0],~dout_abs_NF06[WIDTH-2:0]+8'd1} : {sgn_update_reg3[0],dout_abs_NF06[WIDTH-2:0]};
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+426
@@ -0,0 +1,426 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CN_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CN_PRO
|
||||
#(
|
||||
parameter WIDTH = 4'd8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_CN,
|
||||
input start_CN, //模块启动信号，高脉冲
|
||||
|
||||
//VN数据输出，H阵第１行
|
||||
input [WIDTH-1:0] VN1_dout_01_00,
|
||||
input [WIDTH-1:0] VN1_dout_02_00, //后面的00代表H阵原模图的IM
|
||||
input [WIDTH-1:0] VN1_dout_02_01, //后面的01代表H阵原模图的II1
|
||||
//VN数据输出，H阵第２行
|
||||
input [WIDTH-1:0] VN2_dout_01_00,
|
||||
input [WIDTH-1:0] VN2_dout_02_00,
|
||||
input [WIDTH-1:0] VN2_dout_03_00,
|
||||
input [WIDTH-1:0] VN2_dout_04_02, //后面的02代表H阵原模图的II2
|
||||
input [WIDTH-1:0] VN2_dout_04_03, //后面的03代表H阵原模图的II3
|
||||
input [WIDTH-1:0] VN2_dout_04_04, //后面的04代表H阵原模图的II4
|
||||
//VN数据输出，H阵第３行
|
||||
input [WIDTH-1:0] VN3_dout_01_00,
|
||||
input [WIDTH-1:0] VN3_dout_02_05, //后面的05代表H阵原模图的II5
|
||||
input [WIDTH-1:0] VN3_dout_02_06, //后面的06代表H阵原模图的II6
|
||||
input [WIDTH-1:0] VN3_dout_03_07, //后面的07代表H阵原模图的II7
|
||||
input [WIDTH-1:0] VN3_dout_03_08, //后面的08代表H阵原模图的II8
|
||||
input [WIDTH-1:0] VN3_dout_04_00,
|
||||
|
||||
//VN读地址，H阵第１行
|
||||
output reg [8:0] VN1_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] VN1_addr_rd_02_00=10'd1023,
|
||||
output reg [9:0] VN1_addr_rd_02_01=10'd511,
|
||||
//VN读地址，H阵第２行
|
||||
output reg [8:0] VN2_addr_rd_01_00=9'd511,
|
||||
output reg [8:0] VN2_addr_rd_02_00=9'd511,
|
||||
output reg [8:0] VN2_addr_rd_03_00=9'd511,
|
||||
output reg [9:0] VN2_addr_rd_04_02=10'd1023,
|
||||
output reg [9:0] VN2_addr_rd_04_03=10'd511,
|
||||
output reg [8:0] VN2_addr_rd_04_04=9'd511,
|
||||
//VN读地址，H阵第３行
|
||||
output reg [8:0] VN3_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] VN3_addr_rd_02_05=10'd1023,
|
||||
output reg [9:0] VN3_addr_rd_02_06=10'd511,
|
||||
output reg [9:0] VN3_addr_rd_03_07=10'd1023,
|
||||
output reg [9:0] VN3_addr_rd_03_08=10'd511,
|
||||
output reg [8:0] VN3_addr_rd_04_00=9'd511,
|
||||
|
||||
//CN写使能
|
||||
output reg [0:0] CN_wea=1'd0,
|
||||
|
||||
//CN写地址，H阵第１行
|
||||
output reg [8:0] CN1_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] CN1_addr_wr_02_00=10'd1023,
|
||||
output reg [9:0] CN1_addr_wr_02_01=10'd511,
|
||||
|
||||
//CN写地址，H阵第２行
|
||||
output reg [8:0] CN2_addr_wr_01_00=9'd511,
|
||||
output reg [8:0] CN2_addr_wr_02_00=9'd511,
|
||||
output reg [8:0] CN2_addr_wr_03_00=9'd511,
|
||||
output reg [9:0] CN2_addr_wr_04_02=10'd1023,
|
||||
output reg [9:0] CN2_addr_wr_04_03=10'd511,
|
||||
output reg [8:0] CN2_addr_wr_04_04=9'd511,
|
||||
|
||||
//CN写地址，H阵第３行
|
||||
output reg [8:0] CN3_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] CN3_addr_wr_02_05=10'd1023,
|
||||
output reg [9:0] CN3_addr_wr_02_06=10'd511,
|
||||
output reg [9:0] CN3_addr_wr_03_07=10'd1023,
|
||||
output reg [9:0] CN3_addr_wr_03_08=10'd511,
|
||||
output reg [8:0] CN3_addr_wr_04_00=9'd511,
|
||||
|
||||
|
||||
//CN写数据，H阵第１行
|
||||
output reg [WIDTH-1:0] CN1_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN1_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN1_din_02_01=8'd0,
|
||||
|
||||
//CN写数据，H阵第２行
|
||||
output reg [WIDTH-1:0] CN2_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_03_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_02=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_03=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_04=8'd0,
|
||||
|
||||
//CN写数据，H阵第３行
|
||||
output reg [WIDTH-1:0] CN3_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_02_05=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_02_06=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_03_07=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_03_08=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_04_00=8'd0,
|
||||
|
||||
output end_CN //模块结束标志，高脉冲
|
||||
);
|
||||
|
||||
reg [10:0] cnt_CN=11'd0;
|
||||
reg flag_CN=1'd0;
|
||||
// 产生该模块的计数基准
|
||||
always @ (posedge clk) begin
|
||||
if(rst_CN) begin
|
||||
cnt_CN <= 11'd0;
|
||||
flag_CN <= 1'b0;
|
||||
end else begin
|
||||
if(start_CN) begin
|
||||
flag_CN <= 1'b1;
|
||||
cnt_CN <= 11'd0;
|
||||
end else begin
|
||||
if(flag_CN) begin
|
||||
if(cnt_CN<11'd560)begin
|
||||
flag_CN <= flag_CN;
|
||||
cnt_CN <= cnt_CN + 11'd1;
|
||||
end else begin
|
||||
cnt_CN <= cnt_CN;
|
||||
flag_CN<= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_CN <= cnt_CN;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 对VN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
VN1_addr_rd_01_00 <= 9'd511;
|
||||
VN1_addr_rd_02_00 <= 10'd1023;
|
||||
VN2_addr_rd_01_00 <= 9'd511;
|
||||
VN2_addr_rd_02_00 <= 9'd511;
|
||||
VN2_addr_rd_03_00 <= 9'd511;
|
||||
VN3_addr_rd_01_00 <= 9'd511;
|
||||
VN3_addr_rd_04_00 <= 9'd511;
|
||||
|
||||
VN1_addr_rd_02_01 <= 10'd511;
|
||||
VN2_addr_rd_04_02 <= 10'd1023;
|
||||
VN2_addr_rd_04_03 <= 10'd511;
|
||||
VN2_addr_rd_04_04 <= 9'd511;
|
||||
VN3_addr_rd_02_05 <= 10'd1023;
|
||||
VN3_addr_rd_02_06 <= 10'd511;
|
||||
VN3_addr_rd_03_07 <= 10'd1023;
|
||||
VN3_addr_rd_03_08 <= 10'd511;
|
||||
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 && cnt_CN <= 11'd512) begin
|
||||
VN1_addr_rd_01_00 <= VN1_addr_rd_01_00 + 9'd1;
|
||||
VN1_addr_rd_02_00 <= VN1_addr_rd_02_00 + 9'd1;
|
||||
VN2_addr_rd_01_00 <= VN2_addr_rd_01_00 + 9'd1;
|
||||
VN2_addr_rd_02_00 <= VN2_addr_rd_02_00 + 9'd1;
|
||||
VN2_addr_rd_03_00 <= VN2_addr_rd_03_00 + 9'd1;
|
||||
VN3_addr_rd_01_00 <= VN3_addr_rd_01_00 + 9'd1;
|
||||
VN3_addr_rd_04_00 <= VN3_addr_rd_04_00 + 9'd1;
|
||||
VN1_addr_rd_02_01 <= VN1_addr_rd_02_01 + 10'd1;
|
||||
VN2_addr_rd_04_02 <= VN2_addr_rd_04_02 + 10'd1;
|
||||
VN2_addr_rd_04_03 <= VN2_addr_rd_04_03 + 10'd1;
|
||||
VN2_addr_rd_04_04 <= VN2_addr_rd_04_04 + 9'd1;
|
||||
VN3_addr_rd_02_05 <= VN3_addr_rd_02_05 + 10'd1;
|
||||
VN3_addr_rd_02_06 <= VN3_addr_rd_02_06 + 10'd1;
|
||||
VN3_addr_rd_03_07 <= VN3_addr_rd_03_07 + 10'd1;
|
||||
VN3_addr_rd_03_08 <= VN3_addr_rd_03_08 + 10'd1;
|
||||
end else begin
|
||||
VN1_addr_rd_01_00 <= 9'd511;
|
||||
VN1_addr_rd_02_00 <= 10'd1023;
|
||||
VN2_addr_rd_01_00 <= 9'd511;
|
||||
VN2_addr_rd_02_00 <= 9'd511;
|
||||
VN2_addr_rd_03_00 <= 9'd511;
|
||||
VN3_addr_rd_01_00 <= 9'd511;
|
||||
VN3_addr_rd_04_00 <= 9'd511;
|
||||
VN1_addr_rd_02_01 <= 10'd511;
|
||||
VN2_addr_rd_04_02 <= 10'd1023;
|
||||
VN2_addr_rd_04_03 <= 10'd511;
|
||||
VN2_addr_rd_04_04 <= 9'd511;
|
||||
VN3_addr_rd_02_05 <= 10'd1023;
|
||||
VN3_addr_rd_02_06 <= 10'd511;
|
||||
VN3_addr_rd_03_07 <= 10'd1023;
|
||||
VN3_addr_rd_03_08 <= 10'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] din01_VN_RU01;
|
||||
wire [WIDTH-1:0] din02_VN_RU01;
|
||||
wire [WIDTH-1:0] din03_VN_RU01;
|
||||
wire [WIDTH-1:0] dout01_RU01 ;
|
||||
wire [WIDTH-1:0] dout02_RU01 ;
|
||||
wire [WIDTH-1:0] dout03_RU01 ;
|
||||
wire [WIDTH-1:0] din01_VN_RU02;
|
||||
wire [WIDTH-1:0] din02_VN_RU02;
|
||||
wire [WIDTH-1:0] din03_VN_RU02;
|
||||
wire [WIDTH-1:0] din04_VN_RU02;
|
||||
wire [WIDTH-1:0] din05_VN_RU02;
|
||||
wire [WIDTH-1:0] din06_VN_RU02;
|
||||
wire [WIDTH-1:0] dout01_RU02 ;
|
||||
wire [WIDTH-1:0] dout02_RU02 ;
|
||||
wire [WIDTH-1:0] dout03_RU02 ;
|
||||
wire [WIDTH-1:0] dout04_RU02 ;
|
||||
wire [WIDTH-1:0] dout05_RU02 ;
|
||||
wire [WIDTH-1:0] dout06_RU02 ;
|
||||
wire [WIDTH-1:0] din01_VN_RU03;
|
||||
wire [WIDTH-1:0] din02_VN_RU03;
|
||||
wire [WIDTH-1:0] din03_VN_RU03;
|
||||
wire [WIDTH-1:0] din04_VN_RU03;
|
||||
wire [WIDTH-1:0] din05_VN_RU03;
|
||||
wire [WIDTH-1:0] din06_VN_RU03;
|
||||
wire [WIDTH-1:0] dout01_RU03 ;
|
||||
wire [WIDTH-1:0] dout02_RU03 ;
|
||||
wire [WIDTH-1:0] dout03_RU03 ;
|
||||
wire [WIDTH-1:0] dout04_RU03 ;
|
||||
wire [WIDTH-1:0] dout05_RU03 ;
|
||||
wire [WIDTH-1:0] dout06_RU03 ;
|
||||
|
||||
|
||||
|
||||
CNU_3din #(.WIDTH(WIDTH)) RU_01 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU01),
|
||||
.din02_VN_RU(din02_VN_RU01),
|
||||
.din03_VN_RU(din03_VN_RU01),
|
||||
.dout01_RU(dout01_RU01),
|
||||
.dout02_RU(dout02_RU01),
|
||||
.dout03_RU(dout03_RU01)
|
||||
);
|
||||
|
||||
CNU_6din #(.WIDTH(WIDTH)) RU_02 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU02),
|
||||
.din02_VN_RU(din02_VN_RU02),
|
||||
.din03_VN_RU(din03_VN_RU02),
|
||||
.din04_VN_RU(din04_VN_RU02),
|
||||
.din05_VN_RU(din05_VN_RU02),
|
||||
.din06_VN_RU(din06_VN_RU02),
|
||||
.dout01_RU(dout01_RU02),
|
||||
.dout02_RU(dout02_RU02),
|
||||
.dout03_RU(dout03_RU02),
|
||||
.dout04_RU(dout04_RU02),
|
||||
.dout05_RU(dout05_RU02),
|
||||
.dout06_RU(dout06_RU02)
|
||||
);
|
||||
|
||||
CNU_6din #(.WIDTH(WIDTH)) RU_03 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU03),
|
||||
.din02_VN_RU(din02_VN_RU03),
|
||||
.din03_VN_RU(din03_VN_RU03),
|
||||
.din04_VN_RU(din04_VN_RU03),
|
||||
.din05_VN_RU(din05_VN_RU03),
|
||||
.din06_VN_RU(din06_VN_RU03),
|
||||
.dout01_RU(dout01_RU03),
|
||||
.dout02_RU(dout02_RU03),
|
||||
.dout03_RU(dout03_RU03),
|
||||
.dout04_RU(dout04_RU03),
|
||||
.dout05_RU(dout05_RU03),
|
||||
.dout06_RU(dout06_RU03)
|
||||
);
|
||||
// 设置读操作的时延
|
||||
parameter DELAY_RD = 11'd6;
|
||||
// RU模块的输入
|
||||
assign din01_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_00 : 8'd0;
|
||||
assign din03_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_01 : 8'd0;
|
||||
assign din01_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_02_00 : 8'd0;
|
||||
assign din03_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_03_00 : 8'd0;
|
||||
assign din04_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_02 : 8'd0;
|
||||
assign din05_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_03 : 8'd0;
|
||||
assign din06_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_04 : 8'd0;
|
||||
assign din01_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_05 : 8'd0;
|
||||
assign din03_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_06 : 8'd0;
|
||||
assign din04_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_07 : 8'd0;
|
||||
assign din05_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_08 : 8'd0;
|
||||
assign din06_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_04_00 : 8'd0;
|
||||
|
||||
// 设置写操作的时延
|
||||
parameter DELAY_WR = 11'd15;
|
||||
|
||||
// 控制CN的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_CN) begin
|
||||
CN_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR)
|
||||
CN_wea <= 1'd1;
|
||||
else
|
||||
CN_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制CN存储的写地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
CN1_addr_wr_01_00 <= 9'd511;
|
||||
CN1_addr_wr_02_00 <= 10'd1023;
|
||||
CN2_addr_wr_01_00 <= 9'd511;
|
||||
CN2_addr_wr_02_00 <= 9'd511;
|
||||
CN2_addr_wr_03_00 <= 9'd511;
|
||||
CN3_addr_wr_01_00 <= 9'd511;
|
||||
CN3_addr_wr_04_00 <= 9'd511;
|
||||
|
||||
CN1_addr_wr_02_01 <= 10'd511;
|
||||
CN2_addr_wr_04_02 <= 10'd1023;
|
||||
CN2_addr_wr_04_03 <= 10'd511;
|
||||
CN2_addr_wr_04_04 <= 9'd511;
|
||||
CN3_addr_wr_02_05 <= 10'd1023;
|
||||
CN3_addr_wr_02_06 <= 10'd511;
|
||||
CN3_addr_wr_03_07 <= 10'd1023;
|
||||
CN3_addr_wr_03_08 <= 10'd511;
|
||||
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
|
||||
CN1_addr_wr_01_00 <= CN1_addr_wr_01_00 + 9'd1;
|
||||
CN1_addr_wr_02_00 <= CN1_addr_wr_02_00 + 9'd1;
|
||||
CN2_addr_wr_01_00 <= CN2_addr_wr_01_00 + 9'd1;
|
||||
CN2_addr_wr_02_00 <= CN2_addr_wr_02_00 + 9'd1;
|
||||
CN2_addr_wr_03_00 <= CN2_addr_wr_03_00 + 9'd1;
|
||||
CN3_addr_wr_01_00 <= CN3_addr_wr_01_00 + 9'd1;
|
||||
CN3_addr_wr_04_00 <= CN3_addr_wr_04_00 + 9'd1;
|
||||
CN1_addr_wr_02_01 <= CN1_addr_wr_02_01 + 10'd1;
|
||||
CN2_addr_wr_04_02 <= CN2_addr_wr_04_02 + 10'd1;
|
||||
CN2_addr_wr_04_03 <= CN2_addr_wr_04_03 + 10'd1;
|
||||
CN2_addr_wr_04_04 <= CN2_addr_wr_04_04 + 9'd1;
|
||||
CN3_addr_wr_02_05 <= CN3_addr_wr_02_05 + 10'd1;
|
||||
CN3_addr_wr_02_06 <= CN3_addr_wr_02_06 + 10'd1;
|
||||
CN3_addr_wr_03_07 <= CN3_addr_wr_03_07 + 10'd1;
|
||||
CN3_addr_wr_03_08 <= CN3_addr_wr_03_08 + 10'd1;
|
||||
end else begin
|
||||
CN1_addr_wr_01_00 <= 9'd511;
|
||||
CN1_addr_wr_02_00 <= 10'd1023;
|
||||
CN2_addr_wr_01_00 <= 9'd511;
|
||||
CN2_addr_wr_02_00 <= 9'd511;
|
||||
CN2_addr_wr_03_00 <= 9'd511;
|
||||
CN3_addr_wr_01_00 <= 9'd511;
|
||||
CN3_addr_wr_04_00 <= 9'd511;
|
||||
CN1_addr_wr_02_01 <= 10'd511;
|
||||
CN2_addr_wr_04_02 <= 10'd1023;
|
||||
CN2_addr_wr_04_03 <= 10'd511;
|
||||
CN2_addr_wr_04_04 <= 9'd511;
|
||||
CN3_addr_wr_02_05 <= 10'd1023;
|
||||
CN3_addr_wr_02_06 <= 10'd511;
|
||||
CN3_addr_wr_03_07 <= 10'd1023;
|
||||
CN3_addr_wr_03_08 <= 10'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制CN的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
CN1_din_01_00 <= 8'd0;
|
||||
CN1_din_02_00 <= 8'd0;
|
||||
CN2_din_01_00 <= 8'd0;
|
||||
CN2_din_02_00 <= 8'd0;
|
||||
CN2_din_03_00 <= 8'd0;
|
||||
CN3_din_01_00 <= 8'd0;
|
||||
CN3_din_04_00 <= 8'd0;
|
||||
CN1_din_02_01 <= 8'd0;
|
||||
CN2_din_04_02 <= 8'd0;
|
||||
CN2_din_04_03 <= 8'd0;
|
||||
CN2_din_04_04 <= 8'd0;
|
||||
CN3_din_02_05 <= 8'd0;
|
||||
CN3_din_02_06 <= 8'd0;
|
||||
CN3_din_03_07 <= 8'd0;
|
||||
CN3_din_03_08 <= 8'd0;
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
|
||||
CN1_din_01_00 <= dout01_RU01;
|
||||
CN1_din_02_00 <= dout02_RU01;
|
||||
CN2_din_01_00 <= dout01_RU02;
|
||||
CN2_din_02_00 <= dout02_RU02;
|
||||
CN2_din_03_00 <= dout03_RU02;
|
||||
CN3_din_01_00 <= dout01_RU03;
|
||||
CN3_din_04_00 <= dout06_RU03;
|
||||
CN1_din_02_01 <= dout03_RU01;
|
||||
CN2_din_04_02 <= dout04_RU02;
|
||||
CN2_din_04_03 <= dout05_RU02;
|
||||
CN2_din_04_04 <= dout06_RU02;
|
||||
CN3_din_02_05 <= dout02_RU03;
|
||||
CN3_din_02_06 <= dout03_RU03;
|
||||
CN3_din_03_07 <= dout04_RU03;
|
||||
CN3_din_03_08 <= dout05_RU03;
|
||||
end else begin
|
||||
CN1_din_01_00 <= 8'd0;
|
||||
CN1_din_02_00 <= 8'd0;
|
||||
CN2_din_01_00 <= 8'd0;
|
||||
CN2_din_02_00 <= 8'd0;
|
||||
CN2_din_03_00 <= 8'd0;
|
||||
CN3_din_01_00 <= 8'd0;
|
||||
CN3_din_04_00 <= 8'd0;
|
||||
CN1_din_02_01 <= 8'd0;
|
||||
CN2_din_04_02 <= 8'd0;
|
||||
CN2_din_04_03 <= 8'd0;
|
||||
CN2_din_04_04 <= 8'd0;
|
||||
CN3_din_02_05 <= 8'd0;
|
||||
CN3_din_02_06 <= 8'd0;
|
||||
CN3_din_03_07 <= 8'd0;
|
||||
CN3_din_03_08 <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//状态指示
|
||||
assign end_CN = (cnt_CN == 11'd512 + DELAY_WR + 11'd2) ? 1'd1 : 1'd0;
|
||||
endmodule
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1074
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,193 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: LDPC_TopManage_2
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module LDPC_TopManage_2 #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk, //工作时钟,100MHz
|
||||
input Rst, //同步复位信号,高有效
|
||||
input FrameSync_TM, //帧同步标志,高脉冲
|
||||
input Nd_TM, //译码输入数据有效标志,高有效
|
||||
input [WIDTH-1:0] Din_TM, //译码输入数据,软信息
|
||||
//A
|
||||
output FrameSync_A_TM, //帧同步标志,高脉冲
|
||||
output Nd_A_TM, //译码输入数据有效标志,高有效
|
||||
output [WIDTH-1:0] Din_A_TM, //译码输入数据,软信息
|
||||
//B
|
||||
output FrameSync_B_TM, //帧同步标志,高脉冲
|
||||
output Nd_B_TM, //译码输入数据有效标志,高有效
|
||||
output [WIDTH-1:0] Din_B_TM, //译码输入数据,软信息
|
||||
// flag A
|
||||
input LDPC_SyncOut_A_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
input Rdy_A_TM, //译码输出信号有效标志,高有效
|
||||
input [ 0:0] LDPC_Dout_A_TM, //译码输出信号
|
||||
input [ 8:0] good_frames_A_TM, //译码好帧计数
|
||||
input [ 8:0] bad_frames_A_TM, //译码坏帧计数
|
||||
input [ 8:0] total_frames_A_TM, //译码总帧数计数
|
||||
//flag B
|
||||
input LDPC_SyncOut_B_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
input Rdy_B_TM, //译码输出信号有效标志,高有效
|
||||
input [ 0:0] LDPC_Dout_B_TM, //译码输出信号
|
||||
input [ 8:0] good_frames_B_TM, //译码好帧计数
|
||||
input [ 8:0] bad_frames_B_TM, //译码坏帧计数
|
||||
input [ 8:0] total_frames_B_TM, //译码总帧数计数
|
||||
//result
|
||||
output LDPC_SyncOut_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
output Rdy_TM, //译码输出信号有效标志,高有效
|
||||
output [ 0:0] LDPC_Dout_TM, //译码输出信号
|
||||
output [ 8:0] good_frames_TM, //译码好帧计数
|
||||
output [ 8:0] bad_frames_TM, //译码坏帧计数
|
||||
output [ 8:0] total_frames_TM //译码总帧数计数
|
||||
);
|
||||
|
||||
reg FrameSync_TM_reg0, FrameSync_TM_reg1;
|
||||
reg Nd_TM_reg0, Nd_TM_reg1;
|
||||
reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;
|
||||
|
||||
//******输入过程控制
|
||||
always @(posedge clk) begin //接收数据缓存过程
|
||||
FrameSync_TM_reg0 <= FrameSync_TM;
|
||||
FrameSync_TM_reg1 <= FrameSync_TM_reg0;
|
||||
Nd_TM_reg0 <= Nd_TM;
|
||||
Nd_TM_reg1 <= Nd_TM_reg0;
|
||||
Din_TM_reg0 <= Din_TM;
|
||||
Din_TM_reg1 <= Din_TM_reg0;
|
||||
end
|
||||
|
||||
reg [0:0] flag_switch_in = 1'b1;
|
||||
always @(posedge clk) begin //输入乒乓控制过程
|
||||
if (Rst) begin
|
||||
flag_switch_in <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
if (FrameSync_TM) begin
|
||||
flag_switch_in <= ~flag_switch_in;
|
||||
end
|
||||
else flag_switch_in <= flag_switch_in;
|
||||
end
|
||||
end
|
||||
|
||||
assign FrameSync_A_TM = (flag_switch_in == 1'b0) ? FrameSync_TM_reg1 : 1'b0;
|
||||
assign Nd_A_TM = (flag_switch_in == 1'b0) ? Nd_TM_reg1 : 1'b0;
|
||||
assign Din_A_TM = (flag_switch_in == 1'b0) ? Din_TM_reg1 : 8'd0;
|
||||
|
||||
assign FrameSync_B_TM = (flag_switch_in == 1'b1) ? FrameSync_TM_reg1 : 1'b0;
|
||||
assign Nd_B_TM = (flag_switch_in == 1'b1) ? Nd_TM_reg1 : 1'b0;
|
||||
assign Din_B_TM = (flag_switch_in == 1'b1) ? Din_TM_reg1 : 8'd0;
|
||||
|
||||
reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;
|
||||
reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;
|
||||
reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;
|
||||
reg [8:0] good_frames_A_TM_reg0, good_frames_A_TM_reg1;
|
||||
reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;
|
||||
reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;
|
||||
|
||||
reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;
|
||||
reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;
|
||||
reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;
|
||||
reg [8:0] good_frames_B_TM_reg0, good_frames_B_TM_reg1;
|
||||
reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;
|
||||
reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;
|
||||
|
||||
//******输入过程控制
|
||||
always @(posedge clk) begin //输出数据缓存过程
|
||||
if (Rst) begin
|
||||
LDPC_SyncOut_A_TM_reg0 <= 1'b0;
|
||||
LDPC_SyncOut_A_TM_reg1 <= 1'b0;
|
||||
Rdy_A_TM_reg0 <= 1'b0;
|
||||
Rdy_A_TM_reg1 <= 1'b0;
|
||||
LDPC_Dout_A_TM_reg0 <= 1'b0;
|
||||
LDPC_Dout_A_TM_reg1 <= 1'b0;
|
||||
good_frames_A_TM_reg0 <= 9'd0;
|
||||
good_frames_A_TM_reg1 <= 9'd0;
|
||||
bad_frames_A_TM_reg0 <= 9'd0;
|
||||
bad_frames_A_TM_reg1 <= 9'd0;
|
||||
total_frames_A_TM_reg0 <= 9'd0;
|
||||
total_frames_A_TM_reg1 <= 9'd0;
|
||||
|
||||
LDPC_SyncOut_B_TM_reg0 <= 1'b0;
|
||||
LDPC_SyncOut_B_TM_reg1 <= 1'b0;
|
||||
Rdy_B_TM_reg0 <= 1'b0;
|
||||
Rdy_B_TM_reg1 <= 1'b0;
|
||||
LDPC_Dout_B_TM_reg0 <= 1'b0;
|
||||
LDPC_Dout_B_TM_reg1 <= 1'b0;
|
||||
good_frames_B_TM_reg0 <= 9'd0;
|
||||
good_frames_B_TM_reg1 <= 9'd0;
|
||||
bad_frames_B_TM_reg0 <= 9'd0;
|
||||
bad_frames_B_TM_reg1 <= 9'd0;
|
||||
total_frames_B_TM_reg0 <= 9'd0;
|
||||
total_frames_B_TM_reg1 <= 9'd0;
|
||||
end
|
||||
else begin
|
||||
LDPC_SyncOut_A_TM_reg0 <= LDPC_SyncOut_A_TM;
|
||||
LDPC_SyncOut_A_TM_reg1 <= LDPC_SyncOut_A_TM_reg0;
|
||||
Rdy_A_TM_reg0 <= Rdy_A_TM;
|
||||
Rdy_A_TM_reg1 <= Rdy_A_TM_reg0;
|
||||
LDPC_Dout_A_TM_reg0 <= LDPC_Dout_A_TM;
|
||||
LDPC_Dout_A_TM_reg1 <= LDPC_Dout_A_TM_reg0;
|
||||
good_frames_A_TM_reg0 <= good_frames_A_TM;
|
||||
good_frames_A_TM_reg1 <= good_frames_A_TM_reg0;
|
||||
bad_frames_A_TM_reg0 <= bad_frames_A_TM;
|
||||
bad_frames_A_TM_reg1 <= bad_frames_A_TM_reg0;
|
||||
total_frames_A_TM_reg0 <= total_frames_A_TM;
|
||||
total_frames_A_TM_reg1 <= total_frames_A_TM_reg0;
|
||||
|
||||
LDPC_SyncOut_B_TM_reg0 <= LDPC_SyncOut_B_TM;
|
||||
LDPC_SyncOut_B_TM_reg1 <= LDPC_SyncOut_B_TM_reg0;
|
||||
Rdy_B_TM_reg0 <= Rdy_B_TM;
|
||||
Rdy_B_TM_reg1 <= Rdy_B_TM_reg0;
|
||||
LDPC_Dout_B_TM_reg0 <= LDPC_Dout_B_TM;
|
||||
LDPC_Dout_B_TM_reg1 <= LDPC_Dout_B_TM_reg0;
|
||||
good_frames_B_TM_reg0 <= good_frames_B_TM;
|
||||
good_frames_B_TM_reg1 <= good_frames_B_TM_reg0;
|
||||
bad_frames_B_TM_reg0 <= bad_frames_B_TM;
|
||||
bad_frames_B_TM_reg1 <= bad_frames_B_TM_reg0;
|
||||
total_frames_B_TM_reg0 <= total_frames_B_TM;
|
||||
total_frames_B_TM_reg1 <= total_frames_B_TM_reg0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [0:0] flag_switch_out = 1'b1;
|
||||
always @(posedge clk) begin //输出乒乓控制过程
|
||||
if (Rst) begin
|
||||
flag_switch_out <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
if (LDPC_SyncOut_A_TM || LDPC_SyncOut_B_TM) flag_switch_out <= ~flag_switch_out;
|
||||
else flag_switch_out <= flag_switch_out;
|
||||
end
|
||||
end
|
||||
|
||||
assign LDPC_SyncOut_TM = (flag_switch_out == 1'b0) ? LDPC_SyncOut_A_TM_reg1 : LDPC_SyncOut_B_TM_reg1;
|
||||
assign Rdy_TM = (flag_switch_out == 1'b0) ? Rdy_A_TM_reg1 : Rdy_B_TM_reg1;
|
||||
assign LDPC_Dout_TM = (flag_switch_out == 1'b0) ? LDPC_Dout_A_TM_reg1 : LDPC_Dout_B_TM_reg1;
|
||||
|
||||
assign good_frames_TM = good_frames_B_TM_reg1 + good_frames_A_TM_reg1;
|
||||
assign bad_frames_TM = bad_frames_B_TM_reg1 + bad_frames_A_TM_reg1;
|
||||
assign total_frames_TM = total_frames_B_TM_reg1 + total_frames_A_TM_reg1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module MagnitudeEstimator #(
|
||||
parameter VEC_WIDTH = 21
|
||||
|
||||
@@ -0,0 +1,385 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: Message_Store
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Message_Store #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input rst_MS,
|
||||
input framesync_MS, //帧同步标志，高脉冲
|
||||
input nd_MS, //译码输入数据有效标志，高有效
|
||||
input [WIDTH-1:0] din_MS, //译码输入软信息
|
||||
input [ 0:0] oe_MS, //使能输出信号，高脉冲
|
||||
|
||||
output deal_end_MS, //转换完成标志
|
||||
output syncout_MS, //高脉冲
|
||||
output rdy_MS, //高有效的连续信号
|
||||
output reg [WIDTH-1:0] dout01_MS = 8'd0, // 输出数据
|
||||
output reg [WIDTH-1:0] dout02_MS = 8'd0,
|
||||
output reg [WIDTH-1:0] dout03_MS = 8'd0,
|
||||
output reg [WIDTH-1:0] dout04_MS = 8'd0
|
||||
);
|
||||
reg [10:0] cnt_MS = 11'd0;
|
||||
reg flag_end = 1'd0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
flag_end <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (framesync_MS) flag_end <= 1'd1;
|
||||
else if (nd_MS && cnt_MS == 11'd2047) flag_end <= 1'd0;
|
||||
else flag_end <= flag_end;
|
||||
end
|
||||
end
|
||||
|
||||
// 产生基准计数
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
cnt_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_end) begin
|
||||
if (nd_MS) cnt_MS <= cnt_MS + 11'd1;
|
||||
else begin
|
||||
cnt_MS <= cnt_MS;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_MS <= cnt_MS;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 = 1'd0, wea2_03 = 1'd0, wea2_04 = 1'd0;
|
||||
reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'd511, addr_wr2_01 = 9'd511, addr_wr2_02 = 9'd511, addr_wr2_03 = 9'd511, addr_wr2_04 = 9'd511;
|
||||
reg [WIDTH-1:0] din1_01 = 8'd0, din1_02 = 8'd0, din1_03 = 8'd0, din1_04 = 8'd0, din2_01 = 8'd0, din2_02 = 8'd0, din2_03 = 8'd0, din2_04 = 8'd0;
|
||||
reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'd511, addr_rd2_01 = 9'd511, addr_rd2_02 = 9'd511, addr_rd2_03 = 9'd511, addr_rd2_04 = 9'd511;
|
||||
wire [WIDTH-1:0] dout1_01, dout1_02, dout1_03, dout1_04, dout2_01, dout2_02, dout2_03, dout2_04;
|
||||
|
||||
RAM_512_8 Lp1_01 (
|
||||
.clka (clk),
|
||||
.wea (wea1_01),
|
||||
.addra(addr_wr1_01),
|
||||
.dina (din1_01),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_01),
|
||||
.doutb(dout1_01)
|
||||
);
|
||||
RAM_512_8 Lp1_02 (
|
||||
.clka (clk),
|
||||
.wea (wea1_02),
|
||||
.addra(addr_wr1_02),
|
||||
.dina (din1_02),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_02),
|
||||
.doutb(dout1_02)
|
||||
);
|
||||
RAM_512_8 Lp1_03 (
|
||||
.clka (clk),
|
||||
.wea (wea1_03),
|
||||
.addra(addr_wr1_03),
|
||||
.dina (din1_03),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_03),
|
||||
.doutb(dout1_03)
|
||||
);
|
||||
RAM_512_8 Lp1_04 (
|
||||
.clka (clk),
|
||||
.wea (wea1_04),
|
||||
.addra(addr_wr1_04),
|
||||
.dina (din1_04),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_04),
|
||||
.doutb(dout1_04)
|
||||
);
|
||||
RAM_512_8 Lp2_01 (
|
||||
.clka (clk),
|
||||
.wea (wea2_01),
|
||||
.addra(addr_wr2_01),
|
||||
.dina (din2_01),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_01),
|
||||
.doutb(dout2_01)
|
||||
);
|
||||
RAM_512_8 Lp2_02 (
|
||||
.clka (clk),
|
||||
.wea (wea2_02),
|
||||
.addra(addr_wr2_02),
|
||||
.dina (din2_02),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_02),
|
||||
.doutb(dout2_02)
|
||||
);
|
||||
RAM_512_8 Lp2_03 (
|
||||
.clka (clk),
|
||||
.wea (wea2_03),
|
||||
.addra(addr_wr2_03),
|
||||
.dina (din2_03),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_03),
|
||||
.doutb(dout2_03)
|
||||
);
|
||||
RAM_512_8 Lp2_04 (
|
||||
.clka (clk),
|
||||
.wea (wea2_04),
|
||||
.addra(addr_wr2_04),
|
||||
.dina (din2_04),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_04),
|
||||
.doutb(dout2_04)
|
||||
);
|
||||
|
||||
reg flag_switch_MS = 1'd0;
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) flag_switch_MS <= 1'd0;
|
||||
else begin
|
||||
if (nd_MS && cnt_MS == 11'd2047) flag_switch_MS <= ~flag_switch_MS;
|
||||
else flag_switch_MS <= flag_switch_MS;
|
||||
end
|
||||
end
|
||||
|
||||
// 乒乓写缓存过程
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
wea1_01 <= 1'd0;
|
||||
wea1_02 <= 1'd0;
|
||||
wea1_03 <= 1'd0;
|
||||
wea1_04 <= 1'd0;
|
||||
wea2_01 <= 1'd0;
|
||||
wea2_02 <= 1'd0;
|
||||
wea2_03 <= 1'd0;
|
||||
wea2_04 <= 1'd0;
|
||||
addr_wr1_01 <= 9'd511;
|
||||
addr_wr1_02 <= 9'd511;
|
||||
addr_wr1_03 <= 9'd511;
|
||||
addr_wr1_04 <= 9'd511;
|
||||
addr_wr2_01 <= 9'd511;
|
||||
addr_wr2_02 <= 9'd511;
|
||||
addr_wr2_03 <= 9'd511;
|
||||
addr_wr2_04 <= 9'd511;
|
||||
din1_01 <= 8'd0;
|
||||
din1_02 <= 8'd0;
|
||||
din1_03 <= 8'd0;
|
||||
din1_04 <= 8'd0;
|
||||
din2_01 <= 8'd0;
|
||||
din2_02 <= 8'd0;
|
||||
din2_03 <= 8'd0;
|
||||
din2_04 <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (nd_MS) //所有的写操作均在nd_MS有效时进行
|
||||
if (flag_switch_MS == 1'd0) begin //写第一个缓存区
|
||||
if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
|
||||
wea1_01 <= 1'd1;
|
||||
addr_wr1_01 <= addr_wr1_01 + 9'd1;
|
||||
din1_01 <= din_MS;
|
||||
end
|
||||
else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
|
||||
wea1_02 <= 1'd1;
|
||||
addr_wr1_02 <= addr_wr1_02 + 9'd1;
|
||||
din1_02 <= din_MS;
|
||||
wea1_01 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
|
||||
wea1_03 <= 1'd1;
|
||||
addr_wr1_03 <= addr_wr1_03 + 9'd1;
|
||||
din1_03 <= din_MS;
|
||||
wea1_02 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
|
||||
wea1_04 <= 1'd1;
|
||||
addr_wr1_04 <= addr_wr1_04 + 9'd1;
|
||||
din1_04 <= din_MS;
|
||||
wea1_03 <= 1'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
|
||||
wea2_01 <= 1'd1;
|
||||
addr_wr2_01 <= addr_wr2_01 + 9'd1;
|
||||
din2_01 <= din_MS;
|
||||
end
|
||||
else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
|
||||
wea2_02 <= 1'd1;
|
||||
addr_wr2_02 <= addr_wr2_02 + 9'd1;
|
||||
din2_02 <= din_MS;
|
||||
wea2_01 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
|
||||
wea2_03 <= 1'd1;
|
||||
addr_wr2_03 <= addr_wr2_03 + 9'd1;
|
||||
din2_03 <= din_MS;
|
||||
wea2_02 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
|
||||
wea2_04 <= 1'd1;
|
||||
addr_wr2_04 <= addr_wr2_04 + 9'd1;
|
||||
din2_04 <= din_MS;
|
||||
wea2_03 <= 1'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
wea1_01 <= 1'd0;
|
||||
wea1_02 <= 1'd0;
|
||||
wea1_03 <= 1'd0;
|
||||
wea1_04 <= 1'd0;
|
||||
wea2_01 <= 1'd0;
|
||||
wea2_02 <= 1'd0;
|
||||
wea2_03 <= 1'd0;
|
||||
wea2_04 <= 1'd0;
|
||||
din1_01 <= 8'd0;
|
||||
din1_02 <= 8'd0;
|
||||
din1_03 <= 8'd0;
|
||||
din1_04 <= 8'd0;
|
||||
din2_01 <= 8'd0;
|
||||
din2_02 <= 8'd0;
|
||||
din2_03 <= 8'd0;
|
||||
din2_04 <= 8'd0;
|
||||
addr_wr1_01 <= addr_wr1_01;
|
||||
addr_wr1_02 <= addr_wr1_02;
|
||||
addr_wr1_03 <= addr_wr1_03;
|
||||
addr_wr1_04 <= addr_wr1_04;
|
||||
addr_wr2_01 <= addr_wr2_01;
|
||||
addr_wr2_02 <= addr_wr2_02;
|
||||
addr_wr2_03 <= addr_wr2_03;
|
||||
addr_wr2_04 <= addr_wr2_04;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg flag_out = 1'd0;
|
||||
reg [10:0] cnt_out_MS = 11'd0;
|
||||
// 产生输出计数器
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
flag_out <= 1'd0;
|
||||
cnt_out_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (oe_MS) begin
|
||||
flag_out <= 1'd1;
|
||||
cnt_out_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_out && cnt_out_MS < 11'd540) begin
|
||||
cnt_out_MS <= cnt_out_MS + 11'd1;
|
||||
end
|
||||
else begin
|
||||
flag_out <= 1'd0;
|
||||
cnt_out_MS <= cnt_out_MS;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// 控制输出缓存地址
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
addr_rd1_01 <= 9'd511;
|
||||
addr_rd1_02 <= 9'd511;
|
||||
addr_rd1_03 <= 9'd511;
|
||||
addr_rd1_04 <= 9'd511;
|
||||
addr_rd2_01 <= 9'd511;
|
||||
addr_rd2_02 <= 9'd511;
|
||||
addr_rd2_03 <= 9'd511;
|
||||
addr_rd2_04 <= 9'd511;
|
||||
end
|
||||
else begin
|
||||
if (flag_switch_MS) begin // 输出缓存１中的数据
|
||||
if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
|
||||
addr_rd1_01 <= addr_rd1_01 + 9'd1;
|
||||
addr_rd1_02 <= addr_rd1_02 + 9'd1;
|
||||
addr_rd1_03 <= addr_rd1_03 + 9'd1;
|
||||
addr_rd1_04 <= addr_rd1_04 + 9'd1;
|
||||
end
|
||||
else begin
|
||||
addr_rd1_01 <= 9'd511;
|
||||
addr_rd1_02 <= 9'd511;
|
||||
addr_rd1_03 <= 9'd511;
|
||||
addr_rd1_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
else begin // 输出缓存2中的数据
|
||||
if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
|
||||
addr_rd2_01 <= addr_rd2_01 + 9'd1;
|
||||
addr_rd2_02 <= addr_rd2_02 + 9'd1;
|
||||
addr_rd2_03 <= addr_rd2_03 + 9'd1;
|
||||
addr_rd2_04 <= addr_rd2_04 + 9'd1;
|
||||
end
|
||||
else begin
|
||||
addr_rd2_01 <= 9'd511;
|
||||
addr_rd2_02 <= 9'd511;
|
||||
addr_rd2_03 <= 9'd511;
|
||||
addr_rd2_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 输出缓存数据到译码器
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_switch_MS) begin
|
||||
if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
|
||||
dout01_MS <= dout1_01;
|
||||
dout02_MS <= dout1_02;
|
||||
dout03_MS <= dout1_03;
|
||||
dout04_MS <= dout1_04;
|
||||
end
|
||||
else begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
|
||||
dout01_MS <= dout2_01;
|
||||
dout02_MS <= dout2_02;
|
||||
dout03_MS <= dout2_03;
|
||||
dout04_MS <= dout2_04;
|
||||
end
|
||||
else begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
// 输出处理完成、同步脉冲和使能标志
|
||||
assign deal_end_MS = (cnt_MS == 11'd2047 && nd_MS) ? 1'd1 : 1'd0;
|
||||
assign syncout_MS = (cnt_out_MS == 11'd5) ? 1'd1 : 1'd0;
|
||||
assign rdy_MS = (cnt_out_MS >= 11'd6 && cnt_out_MS <= 11'd517) ? 1'd1 : 1'd0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 21:27:25 01/18/2018
|
||||
// Design Name:
|
||||
// Module Name: Normalization_Factor_0_8125
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Normalization_Factor_0_8125 #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] din_NF, //输入为非负数
|
||||
output reg [WIDTH-1:0] dout_NF = 8'd0 //输出相对输入延时3个时钟周期
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] din_NF_reg0 = 8'd0, din_NF_reg1 = 8'd0;
|
||||
reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;
|
||||
always @(posedge clk) begin
|
||||
din_NF_reg0 <= din_NF;
|
||||
din_NF_reg1 <= din_NF_reg0;
|
||||
end
|
||||
always @(posedge clk) begin //对输入数据乘以系数0.8125
|
||||
sum_1 <= (din_NF >> 1) + (din_NF >> 2);
|
||||
sum_2 <= sum_1 + (din_NF_reg0 >> 4);
|
||||
case ({
|
||||
din_NF_reg1[3:0]
|
||||
}) //matlab中用round函数，verilog中默认是floor函数
|
||||
4'b0000: dout_NF <= sum_2 + 8'd0;
|
||||
4'b0001: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0010: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0011: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0100: dout_NF <= sum_2 + 8'd0;
|
||||
4'b0101: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0110: dout_NF <= sum_2 + 8'd1; //32个数，0~15和16~31的数是一样的，所以用din_NF_reg1&4'b1111，
|
||||
4'b0111: dout_NF <= sum_2 + 8'd2; //例如，din_NF_reg1=6'd19,经过din_NF_reg1&4'b1111之后，变成了6'd3
|
||||
4'b1000: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1001: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1010: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1011: dout_NF <= sum_2 + 8'd2;
|
||||
4'b1100: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1101: dout_NF <= sum_2 + 8'd2;
|
||||
4'b1110: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1111: dout_NF <= sum_2 + 8'd2;
|
||||
default: dout_NF <= 8'd0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
+144
@@ -0,0 +1,144 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: OUT_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module OUT_PRO
|
||||
#(
|
||||
parameter OUT_ONLY_INFORMATION = 1'd0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_OUT,
|
||||
input start_OUT,
|
||||
|
||||
input [0:0] DR_dout_01,
|
||||
input [0:0] DR_dout_02,
|
||||
input [0:0] DR_dout_03,
|
||||
input [0:0] DR_dout_04,
|
||||
|
||||
output reg [8:0] DR_addr_rd_01=9'd511,
|
||||
output reg [8:0] DR_addr_rd_02=9'd511,
|
||||
output reg [8:0] DR_addr_rd_03=9'd511,
|
||||
output reg [8:0] DR_addr_rd_04=9'd511,
|
||||
|
||||
output ldpc_syncout_OUT,
|
||||
output rdy_OUT,
|
||||
output reg [0:0] ldpc_dout_OUT=1'd0
|
||||
);
|
||||
|
||||
reg [11:0] cnt_OUT=12'd0;
|
||||
reg flag_OUT=1'd0;
|
||||
always @ (posedge clk) begin//产生该模块的计数基准
|
||||
if(rst_OUT) begin
|
||||
cnt_OUT <= 12'd0;
|
||||
flag_OUT <= 1'b0;
|
||||
end else begin
|
||||
if(start_OUT) begin
|
||||
flag_OUT <= 1'b1;
|
||||
cnt_OUT <= 12'd0;
|
||||
end else begin
|
||||
if(flag_OUT) begin
|
||||
if(cnt_OUT<12'd2080)begin
|
||||
flag_OUT <= flag_OUT;
|
||||
cnt_OUT <= cnt_OUT + 12'd1;
|
||||
end else begin
|
||||
cnt_OUT <= cnt_OUT;
|
||||
flag_OUT <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_OUT <= cnt_OUT;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
// 控制DR的读地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUT) begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
DR_addr_rd_03 <= 9'd511;
|
||||
DR_addr_rd_04 <= 9'd511;
|
||||
end else begin
|
||||
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
|
||||
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
|
||||
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
|
||||
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
|
||||
else begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
end
|
||||
end else begin // 输出整个码字
|
||||
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
|
||||
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
|
||||
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd1025 && cnt_OUT <= 12'd1536)
|
||||
DR_addr_rd_03 <= DR_addr_rd_03 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd1537 && cnt_OUT <= 12'd2048)
|
||||
DR_addr_rd_04 <= DR_addr_rd_04 + 9'd1;
|
||||
else begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
DR_addr_rd_03 <= 9'd511;
|
||||
DR_addr_rd_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
parameter DELAY_OUT = 4'd6;
|
||||
// 控制DR的输出数据到译码器的输出
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUT) begin
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end else begin
|
||||
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
|
||||
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_01;
|
||||
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_02;
|
||||
else
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end else begin // 输出整个码字
|
||||
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_01;
|
||||
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_02;
|
||||
else if (cnt_OUT >= 12'd1025 + DELAY_OUT && cnt_OUT <= 12'd1536 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_03;
|
||||
else if (cnt_OUT >= 12'd1537 + DELAY_OUT && cnt_OUT <= 12'd2048 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_04;
|
||||
else
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 产生状态指示标志
|
||||
assign ldpc_syncout_OUT = (cnt_OUT == 12'd1 + DELAY_OUT) ? 1'd1 : 1'd0;
|
||||
|
||||
assign rdy_OUT = (OUT_ONLY_INFORMATION == 1'd0) ?
|
||||
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd2048 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0) :
|
||||
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd1024 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0);
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
// +------------------------------+
|
||||
// | |
|
||||
|
||||
+144
-219
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
@@ -20,103 +20,102 @@
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RecvTop (
|
||||
input clk,
|
||||
input clk2,
|
||||
input clk_60M_mac,
|
||||
input clk_2x, // clk_2x
|
||||
input clk_4x,
|
||||
input rst,
|
||||
input rst2,
|
||||
|
||||
input rst2, // TODO： delete the signal
|
||||
// phy wave
|
||||
input [11:0] dini,
|
||||
input [11:0] dinq,
|
||||
|
||||
// mgc control
|
||||
output [ 3:0] ad9361_ctrl_in,
|
||||
|
||||
//vio
|
||||
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
|
||||
input EQUenable_vio, //为1时启用均衡
|
||||
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
|
||||
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
|
||||
// stop signal
|
||||
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
|
||||
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
||||
|
||||
input [6:0] vio_stopbit, //寻找停止位，默认值为7'd60
|
||||
|
||||
//debug
|
||||
//trigger
|
||||
output rst_TimeSync,
|
||||
output rst_freq,
|
||||
output DAGC_rdy,
|
||||
output framesync, //帧同步峰
|
||||
output framesync_delay, //帧同步峰，与频率补偿输出对应
|
||||
output framesync_tsync, //帧同步标志，与TSync输出对应
|
||||
output IntpARdy, //TSync输出nd
|
||||
output nd_SC_FDE_dout, //SC_FDE输出nd
|
||||
output framerdy, //一帧译码结果存储完毕标志
|
||||
output reg flag_bercount = 1'd0,
|
||||
output reg flag_badframe = 1'd0,
|
||||
output reg flag_ber = 1'd0,
|
||||
//各模块输出，星座图
|
||||
output [11:0] dc_removal_dout_i, //MGC_adaptation、去直流输出
|
||||
output [11:0] dc_removal_dout_q,
|
||||
output [ 9:0] matchfilterout_i, //MF输出
|
||||
output [ 9:0] matchfilterout_q,
|
||||
output [ 9:0] DAGC_out_i, //DAGC输出
|
||||
output [ 9:0] DAGC_out_q,
|
||||
output [ 9:0] freqdataout_i, //频率补偿输出
|
||||
output [ 9:0] freqdataout_q,
|
||||
output [ 9:0] IntpOuti, //TSync输出
|
||||
output [ 9:0] IntpOutq,
|
||||
output [ 9:0] SC_FDE_douti, //SC_FDE输出
|
||||
output [ 9:0] SC_FDE_doutq,
|
||||
//MGC_adaptation
|
||||
output [24:0] mean_temp,
|
||||
output [12:0] acc_mean,
|
||||
output [ 4:0] state_mgc,
|
||||
output mgc1_rdy,
|
||||
output flag_state_mgc,
|
||||
output [ 2:0] state_rst,
|
||||
output flag_overflow,
|
||||
output flag_small,
|
||||
//DC
|
||||
output [11:0] dc_value_i,
|
||||
output [11:0] dc_value_q,
|
||||
output flag_dc,
|
||||
//DAGC
|
||||
output flag_agch,
|
||||
output flag_agcl,
|
||||
output flag_agc_power,
|
||||
output [12:0] agc_ref,
|
||||
output [12:0] agc_check,
|
||||
//power test
|
||||
output flag_powerabsh,
|
||||
output flag_powerabsl,
|
||||
output flag_abs_power,
|
||||
output [10:0] abs_ref,
|
||||
output [10:0] abs_check,
|
||||
//TSync
|
||||
output [ 3:0] flag_clk_4bit, //位同步选取通道结果
|
||||
//SC_FDE,溢出标志
|
||||
output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||||
output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||||
output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
|
||||
output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
|
||||
output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
|
||||
output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
output flagoverflow_FDE_dataout_29to10q, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
output reg flagoverflow = 1'd0, //总溢出标志
|
||||
output Pilot_rdy_hide1_d1,
|
||||
|
||||
// mac frame header
|
||||
output [63:0] recvNetData,
|
||||
output recvNetDataNd,
|
||||
input debug_loss
|
||||
output recvNetDataNd
|
||||
);
|
||||
|
||||
wire rst_TimeSync;
|
||||
wire rst_freq;
|
||||
wire DAGC_rdy;
|
||||
wire framesync; //帧同步峰
|
||||
wire framesync_delay; //帧同步峰，与频率补偿输出对应
|
||||
wire framesync_tsync; //帧同步标志，与TSync输出对应
|
||||
wire IntpARdy; //TSync输出nd
|
||||
wire nd_SC_FDE_dout; //SC_FDE输出nd
|
||||
wire framerdy; //一帧译码结果存储完毕标志
|
||||
reg flag_bercount = 1'd0;
|
||||
reg flag_badframe = 1'd0;
|
||||
reg flag_ber = 1'd0;
|
||||
wire [11:0] dc_removal_dout_i; //MGC_adaptation、去直流输出
|
||||
wire [11:0] dc_removal_dout_q;
|
||||
wire [ 9:0] matchfilterout_i; //MF输出
|
||||
wire [ 9:0] matchfilterout_q;
|
||||
wire [ 9:0] DAGC_out_i; //DAGC输出
|
||||
wire [ 9:0] DAGC_out_q;
|
||||
wire [ 9:0] freqdataout_i; //频率补偿输出
|
||||
wire [ 9:0] freqdataout_q;
|
||||
wire [ 9:0] IntpOuti; //TSync输出
|
||||
wire [ 9:0] IntpOutq;
|
||||
wire [ 9:0] SC_FDE_douti; //SC_FDE输出
|
||||
wire [ 9:0] SC_FDE_doutq;
|
||||
wire [24:0] mean_temp;
|
||||
wire [12:0] acc_mean;
|
||||
wire [ 4:0] state_mgc;
|
||||
wire mgc1_rdy;
|
||||
wire flag_state_mgc;
|
||||
wire [ 2:0] state_rst;
|
||||
wire flag_overflow;
|
||||
wire flag_small;
|
||||
wire [11:0] dc_value_i;
|
||||
wire [11:0] dc_value_q;
|
||||
wire flag_dc;
|
||||
wire flag_agch;
|
||||
wire flag_agcl;
|
||||
wire flag_agc_power;
|
||||
wire [12:0] agc_ref;
|
||||
wire [12:0] agc_check;
|
||||
wire flag_powerabsh;
|
||||
wire flag_powerabsl;
|
||||
wire flag_abs_power;
|
||||
wire [10:0] abs_ref;
|
||||
wire [10:0] abs_check;
|
||||
wire [ 3:0] flag_clk_4bit; //位同步选取通道结果
|
||||
wire flagoverflow_fftpilot_26to14; //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||||
wire flagoverflow_ChnZF_26to18; //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||||
wire flagoverflow_comdiv_34to20i; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
wire flagoverflow_comdiv_34to20q; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
wire flagoverflow_ifftzero_29to17i; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
wire flagoverflow_ifftzero_29to17q; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
wire flagoverflow_MMSEdiv_divisor_31to28; //第2个除法器，即MMSE除法的分母截位，31截到28
|
||||
wire flagoverflow_divmmse_34to11; //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
wire flagoverflow_ifftindata_28to20i; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
wire flagoverflow_ifftindata_28to20q; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
wire flagoverflow_fftdata_26to16i; //数据段ow的fft输出截位，26截到16
|
||||
wire flagoverflow_fftdata_26to16q; //数据段ow的fft输出截位，26截到16
|
||||
wire flagoverflow_FDE_dataout_29to10i; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
wire flagoverflow_FDE_dataout_29to10q; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
reg flagoverflow = 1'd0; //总溢出标志
|
||||
wire Pilot_rdy_hide1_d1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg [ 7:0] cnt_mgc_delay;
|
||||
wire mgc_start;
|
||||
wire flag_mgc_done; // level flag
|
||||
wire flag_mgc_done_4x; // level flag
|
||||
|
||||
// startup delay
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_mgc_delay <= 0;
|
||||
@@ -131,6 +130,7 @@ module RecvTop (
|
||||
|
||||
assign mgc_start = (cnt_mgc_delay == 8'hFE);
|
||||
|
||||
// * MGC module
|
||||
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
@@ -141,6 +141,8 @@ module RecvTop (
|
||||
.flag_mgc_done (flag_mgc_done)
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg MF_rdy; // flag_mgc_done_d1
|
||||
wire MF_rst; // flag_mgc_done_pulse_d2
|
||||
always @(posedge clk) begin
|
||||
@@ -197,13 +199,14 @@ module RecvTop (
|
||||
end
|
||||
|
||||
|
||||
|
||||
wire mf_fir_s_tready_i;
|
||||
wire mf_fir_s_tready_q;
|
||||
|
||||
// Match filter
|
||||
fir_match_interp4 u_fir_match_filter_interp4_i (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
@@ -211,7 +214,7 @@ module RecvTop (
|
||||
fir_match_interp4 u_fir_match_filter_interp4_q (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
@@ -252,24 +255,31 @@ module RecvTop (
|
||||
.m_axis_data_tdata (dmf_tdata_interp4_q)
|
||||
);
|
||||
|
||||
localparam CNT_CHU_SEQ_SYNC_MAX = 8;//! should not less than 3 due to the minimum rst of aresetn
|
||||
|
||||
wire [21:0] mag;
|
||||
wire mag_valid;
|
||||
wire frame_sync_4x;
|
||||
wire frame_sync_pulse; // in domain clk
|
||||
reg flag_frame_sync; // active high level
|
||||
// calc the magnitude
|
||||
wire rst_frame_sync; // derive from frame sync pulse
|
||||
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
|
||||
|
||||
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
|
||||
|
||||
//* calc the magnitude
|
||||
MagnitudeEstimator #(
|
||||
.VEC_WIDTH(21)
|
||||
) u_MagnitudeEstimator (
|
||||
.clk (clk_4x),
|
||||
.rst (rst),
|
||||
.vec_valid(dmf_tvalid_interp4_i),
|
||||
.I (dmf_tdata_interp4_i),
|
||||
.Q (dmf_tdata_interp4_q),
|
||||
.I (dmf_tdata_interp4_i[20:0]),
|
||||
.Q (dmf_tdata_interp4_q[20:0]),
|
||||
.mag (mag),
|
||||
.mag_valid(mag_valid)
|
||||
);
|
||||
// frame sync threashold judgement
|
||||
//* frame sync threashold judgement
|
||||
PAPR #(
|
||||
.MAG_WIDTH (22),
|
||||
.WINDOW_DEPTH(1023)
|
||||
@@ -279,22 +289,34 @@ module RecvTop (
|
||||
.vec_mag (mag),
|
||||
.mag_valid (mag_valid),
|
||||
.frame_sync (frame_sync_4x),
|
||||
.frame_sync_pulse()
|
||||
.frame_sync_pulse() // under clk_4x
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (frame_sync_pulse) begin
|
||||
cnt_chu_seq_sync <= 1;
|
||||
end
|
||||
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
|
||||
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
|
||||
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_chu_seq_sync <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_frame_sync <= 0;
|
||||
end
|
||||
else if (frame_sync_pulse) begin
|
||||
else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
|
||||
flag_frame_sync <= 1;
|
||||
end
|
||||
else begin
|
||||
flag_frame_sync <= flag_frame_sync;
|
||||
end
|
||||
end
|
||||
// wire [9:0] DAGC_out_i;
|
||||
// wire [9:0] DAGC_out_q;
|
||||
|
||||
|
||||
wire [ 9:0] FrameSync_douti;
|
||||
wire [ 9:0] FrameSync_doutq;
|
||||
@@ -302,18 +324,12 @@ module RecvTop (
|
||||
wire mgc_rdy;
|
||||
wire rst_dagc;
|
||||
|
||||
//帧同步模块
|
||||
|
||||
assign FrameSync_dini = DAGC_out_i;
|
||||
assign FrameSync_dinq = DAGC_out_q;
|
||||
// wire framesync;
|
||||
|
||||
|
||||
// * lost the connection with other nodes
|
||||
reg [20:0] cnt_lost;
|
||||
reg framelost;
|
||||
always @(posedge clk) begin
|
||||
if (Pilot_rdy_hide1_d1) begin
|
||||
if (rst_frame_sync) begin
|
||||
cnt_lost <= 21'd0;
|
||||
framelost <= 1'b0;
|
||||
end
|
||||
@@ -353,13 +369,7 @@ module RecvTop (
|
||||
);
|
||||
|
||||
|
||||
//载波频偏补偿
|
||||
// wire [9:0] freqdataout_i;
|
||||
// wire [9:0] freqdataout_q;
|
||||
// wire framesync_delay;
|
||||
wire data_save; //debug用，暂不需使用
|
||||
// wire rst_freq;
|
||||
|
||||
// CFO estimation
|
||||
freqestm freqestm (
|
||||
.clk (clk),
|
||||
.rst (mgc_start),
|
||||
@@ -376,10 +386,9 @@ module RecvTop (
|
||||
|
||||
//位同步
|
||||
wire [1:0] cnt_tsync;
|
||||
// wire framesync_tsync; //帧同步标志
|
||||
TimeSync_top TimeSync_top (
|
||||
.clk (clk),
|
||||
.rst (Pilot_rdy_hide1_d1),
|
||||
.rst (rst_frame_sync),
|
||||
.dini (freqdataout_i),
|
||||
.dinq (freqdataout_q),
|
||||
.rdy (IntpARdy),
|
||||
@@ -398,14 +407,12 @@ module RecvTop (
|
||||
|
||||
|
||||
// SC-FDE
|
||||
|
||||
SC_FDE_TOP SC_FDE_TOP_djy (
|
||||
.clk (clk),
|
||||
.rst(Pilot_rdy_hide1_d1),
|
||||
|
||||
.rst (rst_frame_sync),
|
||||
// param
|
||||
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
|
||||
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
|
||||
|
||||
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
|
||||
.nd (IntpARdy),
|
||||
.dini (IntpOuti),
|
||||
@@ -414,20 +421,20 @@ module RecvTop (
|
||||
.SC_FDE_douti (SC_FDE_douti),
|
||||
.SC_FDE_doutq (SC_FDE_doutq),
|
||||
// debug,溢出标志
|
||||
.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14),
|
||||
.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18),
|
||||
.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i),
|
||||
.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q),
|
||||
.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i),
|
||||
.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q),
|
||||
.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28),
|
||||
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11),
|
||||
.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i),
|
||||
.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q),
|
||||
.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i),
|
||||
.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q),
|
||||
.flagoverflow_FDE_dataout_29to10i (flagoverflow_FDE_dataout_29to10i),
|
||||
.flagoverflow_FDE_dataout_29to10q (flagoverflow_FDE_dataout_29to10q)
|
||||
.flagoverflow_fftpilot_26to14 (),
|
||||
.flagoverflow_ChnZF_26to18 (),
|
||||
.flagoverflow_comdiv_34to20i (),
|
||||
.flagoverflow_comdiv_34to20q (),
|
||||
.flagoverflow_ifftzero_29to17i (),
|
||||
.flagoverflow_ifftzero_29to17q (),
|
||||
.flagoverflow_MMSEdiv_divisor_31to28(),
|
||||
.flagoverflow_divmmse_34to11 (),
|
||||
.flagoverflow_ifftindata_28to20i (),
|
||||
.flagoverflow_ifftindata_28to20q (),
|
||||
.flagoverflow_fftdata_26to16i (),
|
||||
.flagoverflow_fftdata_26to16q (),
|
||||
.flagoverflow_FDE_dataout_29to10i (),
|
||||
.flagoverflow_FDE_dataout_29to10q ()
|
||||
);
|
||||
|
||||
|
||||
@@ -436,7 +443,7 @@ module RecvTop (
|
||||
wire [9:0] phase_adjust_doutq;
|
||||
phase_adjust phase_adjust (
|
||||
.clk (clk),
|
||||
.rst (Pilot_rdy_hide1_d1),
|
||||
.rst (rst_frame_sync),
|
||||
.din_i (SC_FDE_douti),
|
||||
.din_q (SC_FDE_doutq),
|
||||
.nd (nd_SC_FDE_dout),
|
||||
@@ -452,8 +459,8 @@ module RecvTop (
|
||||
|
||||
IQmerge IQmerge (
|
||||
.clk (clk),
|
||||
.clk2 (clk2),
|
||||
.rst (rst2 || Pilot_rdy_hide1_d1),
|
||||
.clk2 (clk_2x),
|
||||
.rst (rst2 || rst_frame_sync),
|
||||
.nd (phase_adjust_rdy),
|
||||
.framesync (framesync_tsync),
|
||||
.dini (phase_adjust_douti),
|
||||
@@ -469,9 +476,10 @@ module RecvTop (
|
||||
wire [8:0] good_frames;
|
||||
wire [8:0] bad_frames;
|
||||
wire [8:0] total_frames;
|
||||
|
||||
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
|
||||
.clk (clk2),
|
||||
.Rst (rst2 || Pilot_rdy_hide1_d1),
|
||||
.clk (clk_2x),
|
||||
.Rst (rst2 || rst_frame_sync),
|
||||
.FrameSync (ldpcsyncin),
|
||||
.Nd (IQmergerdy),
|
||||
.Din (IQmergedout),
|
||||
@@ -487,89 +495,6 @@ module RecvTop (
|
||||
|
||||
|
||||
|
||||
wire flag_notbyte; //为1时说明得到的有效数据不以字节为单位
|
||||
wire [ 1:0] state_ram;
|
||||
wire berstart_1d;
|
||||
wire bercompare;
|
||||
wire [16:0] bercount;
|
||||
wire [16:0] bercount_max;
|
||||
wire [16:0] ROMaddra_d2;
|
||||
wire RAMdout_d1;
|
||||
wire validnd_new_new;
|
||||
wire [63:0] stop_temp_new;
|
||||
wire flag_stop_0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
|
||||
wire [16:0] addr_stop_0;
|
||||
wire [ 2:0] cnt_8;
|
||||
wire state_8;
|
||||
wire rdy_scramble;
|
||||
wire dout_scramble;
|
||||
wire [16:0] RAMaddra; //比较误码率
|
||||
wire [16:0] ROMaddra; //比较误码率
|
||||
wire nd_ber;
|
||||
|
||||
FrameMerge FrameMerge (
|
||||
.clk (clk2),
|
||||
.rst (Pilot_rdy_hide1_d1),
|
||||
.rst2(rst2),
|
||||
.sync(LDPC_SyncOut),
|
||||
.nd (LDPC_Rdy),
|
||||
.din (LDPC_Dout),
|
||||
|
||||
.vio_stopbit(vio_stopbit),
|
||||
|
||||
.frameIDnd(Pilot_rdy_hide1_d1),
|
||||
.clk2 (clk_60M_mac),
|
||||
.framerdy (framerdy),
|
||||
|
||||
.recv_addr_new_0 (recv_addr_new_0),
|
||||
.recv_addr_new_1 (recv_addr_new_1),
|
||||
.recv_addr_new_2 (recv_addr_new_2),
|
||||
.recv_addr_new_3 (recv_addr_new_3),
|
||||
.recv_data_new_0 (recv_data_new_0),
|
||||
.recv_data_new_1 (recv_data_new_1),
|
||||
.recv_data_new_2 (recv_data_new_2),
|
||||
.recv_data_new_3 (recv_data_new_3),
|
||||
.RAMaddra_write_0(RAMaddra_write_0),
|
||||
.RAMaddra_write_1(RAMaddra_write_1),
|
||||
.RAMaddra_write_2(RAMaddra_write_2),
|
||||
.RAMaddra_write_3(RAMaddra_write_3),
|
||||
.RAMaddra_new_0 (RAMaddra_new_0),
|
||||
.RAMaddra_new_1 (RAMaddra_new_1),
|
||||
.RAMaddra_new_2 (RAMaddra_new_2),
|
||||
.RAMaddra_new_3 (RAMaddra_new_3),
|
||||
|
||||
.flag_notbyte(flag_notbyte),
|
||||
.state_ram (state_ram),
|
||||
.flag_stop (flag_stop), //给shx，拉高8个clk表示当前时帧有效数据接收完毕
|
||||
.addr_stop (addr_stop), //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
||||
//debug
|
||||
.berstart_1d (berstart_1d),
|
||||
.bercompare (bercompare),
|
||||
.bercount (bercount),
|
||||
.bercount_max(bercount_max),
|
||||
.ROMaddra_d2 (ROMaddra_d2),
|
||||
.RAMdout_d1 (RAMdout_d1),
|
||||
|
||||
.validnd_new_new(validnd_new_new),
|
||||
|
||||
.stop_temp_new(stop_temp_new),
|
||||
|
||||
.flag_stop_0(flag_stop_0),
|
||||
.addr_stop_0(addr_stop_0),
|
||||
.cnt_8 (cnt_8),
|
||||
.state_8 (state_8),
|
||||
|
||||
.rdy_scramble (rdy_scramble),
|
||||
.dout_scramble(dout_scramble),
|
||||
|
||||
.RAMaddra (RAMaddra),
|
||||
.ROMaddra (ROMaddra),
|
||||
.nd_ber (nd_ber),
|
||||
.recvNetData (recvNetData),
|
||||
.recvNetDataNd(recvNetDataNd)
|
||||
);
|
||||
|
||||
|
||||
// ***** cdc *****
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
||||
@@ -586,8 +511,8 @@ module RecvTop (
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK(1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) xpm_cdc_frame_sync_pulse_inst (
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+4
-129
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
@@ -231,18 +231,18 @@ module SC_FDE_TOP(
|
||||
.s_axis_config_tdata (8'd1), // input wire [7 : 0] s_axis_config_tdata
|
||||
.s_axis_config_tvalid (fft_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tready (fft_config_tready), // output wire s_axis_config_tready
|
||||
|
||||
// s data
|
||||
.s_axis_data_tdata ({7'd0, fft_in_q, 7'd0, fft_in_i}), // input wire [47 : 0] s_axis_data_tdata
|
||||
.s_axis_data_tvalid (fft_in_nd), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready (fft_in_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tlast (1'd0), // input wire s_axis_data_tlastn不用给这个信号
|
||||
|
||||
// m data
|
||||
.m_axis_data_tdata (fft_out_tdata), // output wire [63 : 0] m_axis_data_tdata
|
||||
.m_axis_data_tuser (fft_index), // output wire [7 : 0] m_axis_data_tuser
|
||||
.m_axis_data_tvalid (fft_out_nd), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tready (1'd1), // input wire m_axis_data_tready
|
||||
.m_axis_data_tlast (m_axis_data_tlast), // output wire m_axis_data_tlast
|
||||
|
||||
//flag
|
||||
.event_frame_started (event_frame_started), // output wire event_frame_started
|
||||
.event_tlast_unexpected (event_tlast_unexpected), // output wire event_tlast_unexpected
|
||||
.event_tlast_missing (event_tlast_missing), // output wire event_tlast_missing
|
||||
@@ -322,10 +322,6 @@ module SC_FDE_TOP(
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//------------------------------------------ifft核，及其输入输出控制器------------------------------------------//
|
||||
reg ifft_config_tvalid = 1'd0;
|
||||
wire ifft_config_tready;
|
||||
@@ -447,10 +443,6 @@ module SC_FDE_TOP(
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------MMSE信道估计结果RAM--------------------------------------------------//
|
||||
wire write_MMSE_wea;
|
||||
wire [ 7:0] addrin_MMSE;
|
||||
@@ -468,12 +460,6 @@ module SC_FDE_TOP(
|
||||
.doutb(dout_MMSE) // output wire [21 : 0] doutb
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------MMSE信道估计模块--------------------------------------------------//
|
||||
Chn_Estimate Chn_Estimate_djy (
|
||||
.clk (clk),
|
||||
@@ -521,12 +507,6 @@ module SC_FDE_TOP(
|
||||
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11) //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//------------------------------------------------------------均衡模块-------------------------------------------------------//
|
||||
|
||||
data_equalizer data_equalizer_djy (
|
||||
@@ -576,109 +556,4 @@ module SC_FDE_TOP(
|
||||
.flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------写测试文件---------------------------------------------------------------------//
|
||||
//----------------------------------------验证data_ow----------------------------------//
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
// integer handle05;
|
||||
// integer handle06;
|
||||
// integer handle07;
|
||||
// integer handle08;
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("pilot_datai.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("pilot_dataq.txt","w"); $fclose(handle02);
|
||||
// handle03=$fopen("pilot_noisei.txt","w"); $fclose(handle03);
|
||||
// handle04=$fopen("pilot_noiseq.txt","w"); $fclose(handle04);
|
||||
|
||||
// handle05=$fopen("din_data1i.txt","w"); $fclose(handle05);
|
||||
// handle06=$fopen("din_data1q.txt","w"); $fclose(handle06);
|
||||
// handle07=$fopen("din_data2i.txt","w"); $fclose(handle07);
|
||||
// handle08=$fopen("din_data2q.txt","w"); $fclose(handle08);
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
// if(nd_pilot2)begin
|
||||
// handle01=$fopen("pilot_datai.txt","a+");$fwrite(handle01,"%d\n",$signed(pilot_datai));$fclose(handle01);
|
||||
// handle02=$fopen("pilot_dataq.txt","a+");$fwrite(handle02,"%d\n",$signed(pilot_dataq));$fclose(handle02);
|
||||
// handle03=$fopen("pilot_noisei.txt","a+");$fwrite(handle03,"%d\n",$signed(pilot_noisei));$fclose(handle03);
|
||||
// handle04=$fopen("pilot_noiseq.txt","a+");$fwrite(handle04,"%d\n",$signed(pilot_noiseq));$fclose(handle04);
|
||||
// end
|
||||
// if(wr_en_data1)begin
|
||||
// handle05=$fopen("din_data1i.txt","a+");$fwrite(handle05,"%d\n",$signed(din_data1i));$fclose(handle05);
|
||||
// handle06=$fopen("din_data1q.txt","a+");$fwrite(handle06,"%d\n",$signed(din_data1q));$fclose(handle06);
|
||||
// end
|
||||
// if(wr_en_data2)begin
|
||||
// handle07=$fopen("din_data2i.txt","a+");$fwrite(handle07,"%d\n",$signed(din_data2i));$fclose(handle07);
|
||||
// handle08=$fopen("din_data2q.txt","a+");$fwrite(handle08,"%d\n",$signed(din_data2q));$fclose(handle08);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
// ----------------------------------------验证data_ow----------------------------------//
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
// integer handle05;
|
||||
// integer handle06;
|
||||
// integer handle07;
|
||||
// integer handle08;
|
||||
// integer handle09;
|
||||
// integer handle10;
|
||||
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("fft_out_i.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("fft_out_q.txt","w"); $fclose(handle02);
|
||||
// handle03=$fopen("ifft_out_i.txt","w"); $fclose(handle03);
|
||||
// handle04=$fopen("ifft_out_q.txt","w"); $fclose(handle04);
|
||||
// handle05=$fopen("fft_in_i.txt","w"); $fclose(handle05);
|
||||
// handle06=$fopen("fft_in_q.txt","w"); $fclose(handle06);
|
||||
// handle07=$fopen("ifft_in_i.txt","w"); $fclose(handle07);
|
||||
// handle08=$fopen("ifft_in_q.txt","w"); $fclose(handle08);
|
||||
// handle09=$fopen("SC_FDE_douti.txt","w"); $fclose(handle09);
|
||||
// handle10=$fopen("SC_FDE_doutq.txt","w"); $fclose(handle10);
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
// if(fft_out_nd)begin
|
||||
// handle01=$fopen("fft_out_i.txt","a+");$fwrite(handle01,"%d\n",$signed(fft_out_i));$fclose(handle01);
|
||||
// handle02=$fopen("fft_out_q.txt","a+");$fwrite(handle02,"%d\n",$signed(fft_out_q));$fclose(handle02);
|
||||
// end
|
||||
// if(ifft_out_nd)begin
|
||||
// handle03=$fopen("ifft_out_i.txt","a+");$fwrite(handle03,"%d\n",$signed(ifft_out_i));$fclose(handle03);
|
||||
// handle04=$fopen("ifft_out_q.txt","a+");$fwrite(handle04,"%d\n",$signed(ifft_out_q));$fclose(handle04);
|
||||
// end
|
||||
// if(fft_in_nd)begin
|
||||
// handle05=$fopen("fft_in_i.txt","a+");$fwrite(handle05,"%d\n",$signed(fft_in_i));$fclose(handle05);
|
||||
// handle06=$fopen("fft_in_q.txt","a+");$fwrite(handle06,"%d\n",$signed(fft_in_q));$fclose(handle06);
|
||||
// end
|
||||
// if(ifft_in_nd)begin
|
||||
// handle07=$fopen("ifft_in_i.txt","a+");$fwrite(handle07,"%d\n",$signed(ifft_in_i));$fclose(handle07);
|
||||
// handle08=$fopen("ifft_in_q.txt","a+");$fwrite(handle08,"%d\n",$signed(ifft_in_q));$fclose(handle08);
|
||||
// end
|
||||
// if(nd_SC_FDE_dout)begin
|
||||
// handle09=$fopen("SC_FDE_douti.txt","a+");$fwrite(handle09,"%d\n",$signed(SC_FDE_douti));$fclose(handle09);
|
||||
// handle10=$fopen("SC_FDE_doutq.txt","a+");$fwrite(handle10,"%d\n",$signed(SC_FDE_doutq));$fclose(handle10);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_1din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_1din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [0:0] dout02_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
|
||||
reg [8:0] sum=9'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
reg [0:0] result_reg4=1'd0;
|
||||
|
||||
reg [8:0] din01_CN_CU_9bit=9'd0;
|
||||
reg [8:0] din02_CHNL_CU_9bit=9'd0;
|
||||
|
||||
reg [7:0] din02_CHNL_CU_reg0=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg1=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg2=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg3=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg4=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg5=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg6=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为9bit
|
||||
din01_CN_CU_9bit <= {din01_CN_CU[7],din01_CN_CU[7:0]};
|
||||
din02_CHNL_CU_9bit <= {din02_CHNL_CU[7],din02_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum <= din01_CN_CU_9bit + din02_CHNL_CU_9bit;
|
||||
result_reg0 <= {sum[8]};
|
||||
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
result_reg4 <= result_reg3;
|
||||
dout02_result_CU <= result_reg4;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
din02_CHNL_CU_reg0 <= din02_CHNL_CU;
|
||||
din02_CHNL_CU_reg1 <= din02_CHNL_CU_reg0;
|
||||
din02_CHNL_CU_reg2 <= din02_CHNL_CU_reg1;
|
||||
din02_CHNL_CU_reg3 <= din02_CHNL_CU_reg2;
|
||||
din02_CHNL_CU_reg4 <= din02_CHNL_CU_reg3;
|
||||
din02_CHNL_CU_reg5 <= din02_CHNL_CU_reg4;
|
||||
din02_CHNL_CU_reg6 <= din02_CHNL_CU_reg5;
|
||||
dout01_CU <= din02_CHNL_CU_reg6;
|
||||
end
|
||||
endmodule
|
||||
|
||||
+143
@@ -0,0 +1,143 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_2din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_2din(//注意：所有的输入数据同时进来本模块，即数据clk是对齐的
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din03_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0, //校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0, //校验节点更新输出
|
||||
output reg [0:0] dout03_result_CU=1'd0 //判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
reg [9:0] din01_CN_CU_10bit=10'd0,din01_CN_CU_10bit_reg0=10'd0,din01_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit=10'd0,din02_CN_CU_10bit_reg0=10'd0,din02_CN_CU_10bit_reg1=10'd0;
|
||||
|
||||
|
||||
reg [9:0] din03_CHNL_CU_10bit=10'd0;
|
||||
reg [9:0] din03_CHNL_CU_10bit_reg0=10'd0;
|
||||
|
||||
reg [9:0] sum1=10'd0;
|
||||
reg [9:0] sum=10'd0;
|
||||
|
||||
reg [9:0] minus1=10'd0;
|
||||
reg [9:0] minus2=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg0=10'd0;
|
||||
reg [9:0] minus2_reg0=10'd0;
|
||||
|
||||
|
||||
reg [9:0] minus1_reg1=10'd0;
|
||||
reg [9:0] minus2_reg1=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg2=10'd0;
|
||||
reg [9:0] minus2_reg2=10'd0;
|
||||
|
||||
reg [9:0] minus1_abs=10'd0;
|
||||
reg [9:0] minus2_abs=10'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为10bit
|
||||
din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CHNL_CU_10bit <= {{2{din03_CHNL_CU[7]}},din03_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
|
||||
din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
|
||||
|
||||
din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
|
||||
din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
|
||||
|
||||
din03_CHNL_CU_10bit_reg0 <= din03_CHNL_CU_10bit;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
|
||||
minus1_reg2 <= minus1_reg1;
|
||||
minus2_reg2 <= minus2_reg1;
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk) begin //结果更新过程
|
||||
sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
|
||||
sum <= sum1 + din03_CHNL_CU_10bit_reg0;
|
||||
|
||||
result_reg0 <= {sum[9]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
dout03_result_CU <= result_reg3;
|
||||
|
||||
minus1 <= sum - din01_CN_CU_10bit_reg1;
|
||||
minus2 <= sum - din02_CN_CU_10bit_reg1;
|
||||
|
||||
if(minus1_reg1[9])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg1 + 10'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg1;
|
||||
if(minus1_reg2[9]) begin//限幅操作
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end else begin
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end
|
||||
|
||||
if(minus2_reg1[9])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg1 + 10'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg1;
|
||||
if(minus2_reg2[9]) begin//限幅操作
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end else begin
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+179
@@ -0,0 +1,179 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_3din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_3din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
input [7:0] din03_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din04_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
|
||||
|
||||
output reg [0:0] dout04_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit=10'd0;
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit_reg0=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit_reg0=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit_reg0=10'd0;
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit_reg1=10'd0;
|
||||
|
||||
reg [9:0] din04_CHNL_CU_10bit=10'd0;
|
||||
|
||||
reg [9:0] sum1=10'd0;
|
||||
reg [9:0] sum2=10'd0;
|
||||
reg [9:0] sum=10'd0;
|
||||
|
||||
reg [9:0] minus1=10'd0;
|
||||
reg [9:0] minus2=10'd0;
|
||||
reg [9:0] minus3=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg0=10'd0;
|
||||
reg [9:0] minus2_reg0=10'd0;
|
||||
reg [9:0] minus3_reg0=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg1=10'd0;
|
||||
reg [9:0] minus2_reg1=10'd0;
|
||||
reg [9:0] minus3_reg1=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg2=10'd0;
|
||||
reg [9:0] minus2_reg2=10'd0;
|
||||
reg [9:0] minus3_reg2=10'd0;
|
||||
|
||||
reg [9:0] minus1_abs=10'd0;
|
||||
reg [9:0] minus2_abs=10'd0;
|
||||
reg [9:0] minus3_abs=10'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
always @ (posedge clk) begin//先把输入转换为10bit
|
||||
din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CN_CU_10bit <= {{2{din03_CN_CU[7]}},din03_CN_CU[7:0]};
|
||||
din04_CHNL_CU_10bit <= {{2{din04_CHNL_CU[7]}},din04_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
|
||||
din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
|
||||
din03_CN_CU_10bit_reg0 <= din03_CN_CU_10bit;
|
||||
|
||||
din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
|
||||
din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
|
||||
din03_CN_CU_10bit_reg1 <= din03_CN_CU_10bit_reg0;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
minus3_reg0 <= minus3;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
minus3_reg1 <= minus3_reg0;
|
||||
|
||||
minus1_reg2 <= minus1_reg1;
|
||||
minus2_reg2 <= minus2_reg1;
|
||||
minus3_reg2 <= minus3_reg1;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
|
||||
sum2 <= din03_CN_CU_10bit + din04_CHNL_CU_10bit;
|
||||
sum <= sum1 + sum2;
|
||||
|
||||
result_reg0 <= {sum[9]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
dout04_result_CU <= result_reg3;
|
||||
minus1 <= sum - din01_CN_CU_10bit_reg1;
|
||||
minus2 <= sum - din02_CN_CU_10bit_reg1;
|
||||
minus3 <= sum - din03_CN_CU_10bit_reg1;
|
||||
|
||||
if(minus1_reg1[9])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg1 + 10'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg1;
|
||||
if(minus1_reg2[9]) begin//限幅操作
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end else begin
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end
|
||||
|
||||
if(minus2_reg1[9])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg1 + 10'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg1;
|
||||
if(minus2_reg2[9]) begin//限幅操作
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end else begin
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end
|
||||
|
||||
if(minus3_reg1[9])//限幅前求绝对值操作
|
||||
minus3_abs <= ~minus3_reg1 + 10'd1;
|
||||
else
|
||||
minus3_abs <= minus3_reg1;
|
||||
if(minus3_reg2[9]) begin//限幅操作
|
||||
if(minus3_abs>10'd127)
|
||||
dout03_CU <= -8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
|
||||
// dout03_CU <= minus3_reg2;
|
||||
end else begin
|
||||
if(minus3_abs>10'd127)
|
||||
dout03_CU <= 8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
|
||||
// dout03_CU <= minus3_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+292
@@ -0,0 +1,292 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_6din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_6din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
input [7:0] din03_CN_CU, //校验节点信息输入
|
||||
input [7:0] din04_CN_CU, //校验节点信息输入
|
||||
input [7:0] din05_CN_CU, //校验节点信息输入
|
||||
input [7:0] din06_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din07_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout04_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout05_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout06_CU=8'd0,//校验节点更新输出
|
||||
|
||||
output reg [0:0] dout07_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg0=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg1=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg2=11'd0;
|
||||
|
||||
reg [10:0] din07_CHNL_CU_11bit=11'd0;
|
||||
reg [10:0] din07_CHNL_CU_11bit_reg0=11'd0;
|
||||
|
||||
|
||||
reg [10:0] sum1=11'd0;
|
||||
reg [10:0] sum2=11'd0;
|
||||
reg [10:0] sum3=11'd0;
|
||||
reg [10:0] sum4=11'd0;
|
||||
reg [10:0] sum5=11'd0;
|
||||
reg [10:0] sum=11'd0;
|
||||
|
||||
reg [10:0] minus1=11'd0;
|
||||
reg [10:0] minus2=11'd0;
|
||||
reg [10:0] minus3=11'd0;
|
||||
reg [10:0] minus4=11'd0;
|
||||
reg [10:0] minus5=11'd0;
|
||||
reg [10:0] minus6=11'd0;
|
||||
|
||||
reg [10:0] minus1_reg0=11'd0;
|
||||
reg [10:0] minus2_reg0=11'd0;
|
||||
reg [10:0] minus3_reg0=11'd0;
|
||||
reg [10:0] minus4_reg0=11'd0;
|
||||
reg [10:0] minus5_reg0=11'd0;
|
||||
reg [10:0] minus6_reg0=11'd0;
|
||||
|
||||
reg [10:0] minus1_reg1=11'd0;
|
||||
reg [10:0] minus2_reg1=11'd0;
|
||||
reg [10:0] minus3_reg1=11'd0;
|
||||
reg [10:0] minus4_reg1=11'd0;
|
||||
reg [10:0] minus5_reg1=11'd0;
|
||||
reg [10:0] minus6_reg1=11'd0;
|
||||
|
||||
reg [10:0] minus1_abs=11'd0;
|
||||
reg [10:0] minus2_abs=11'd0;
|
||||
reg [10:0] minus3_abs=11'd0;
|
||||
reg [10:0] minus4_abs=11'd0;
|
||||
reg [10:0] minus5_abs=11'd0;
|
||||
reg [10:0] minus6_abs=11'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为11bit
|
||||
din01_CN_CU_11bit <= {{3{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_11bit <= {{3{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CN_CU_11bit <= {{3{din03_CN_CU[7]}},din03_CN_CU[7:0]};
|
||||
din04_CN_CU_11bit <= {{3{din04_CN_CU[7]}},din04_CN_CU[7:0]};
|
||||
din05_CN_CU_11bit <= {{3{din05_CN_CU[7]}},din05_CN_CU[7:0]};
|
||||
din06_CN_CU_11bit <= {{3{din06_CN_CU[7]}},din06_CN_CU[7:0]};
|
||||
din07_CHNL_CU_11bit <= {{3{din07_CHNL_CU[7]}},din07_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_11bit_reg0 <= din01_CN_CU_11bit;
|
||||
din02_CN_CU_11bit_reg0 <= din02_CN_CU_11bit;
|
||||
din03_CN_CU_11bit_reg0 <= din03_CN_CU_11bit;
|
||||
din04_CN_CU_11bit_reg0 <= din04_CN_CU_11bit;
|
||||
din05_CN_CU_11bit_reg0 <= din05_CN_CU_11bit;
|
||||
din06_CN_CU_11bit_reg0 <= din06_CN_CU_11bit;
|
||||
din07_CHNL_CU_11bit_reg0 <= din07_CHNL_CU_11bit;
|
||||
|
||||
din01_CN_CU_11bit_reg1 <= din01_CN_CU_11bit_reg0;
|
||||
din02_CN_CU_11bit_reg1 <= din02_CN_CU_11bit_reg0;
|
||||
din03_CN_CU_11bit_reg1 <= din03_CN_CU_11bit_reg0;
|
||||
din04_CN_CU_11bit_reg1 <= din04_CN_CU_11bit_reg0;
|
||||
din05_CN_CU_11bit_reg1 <= din05_CN_CU_11bit_reg0;
|
||||
din06_CN_CU_11bit_reg1 <= din06_CN_CU_11bit_reg0;
|
||||
|
||||
din01_CN_CU_11bit_reg2 <= din01_CN_CU_11bit_reg1;
|
||||
din02_CN_CU_11bit_reg2 <= din02_CN_CU_11bit_reg1;
|
||||
din03_CN_CU_11bit_reg2 <= din03_CN_CU_11bit_reg1;
|
||||
din04_CN_CU_11bit_reg2 <= din04_CN_CU_11bit_reg1;
|
||||
din05_CN_CU_11bit_reg2 <= din05_CN_CU_11bit_reg1;
|
||||
din06_CN_CU_11bit_reg2 <= din06_CN_CU_11bit_reg1;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
minus3_reg0 <= minus3;
|
||||
minus4_reg0 <= minus4;
|
||||
minus5_reg0 <= minus5;
|
||||
minus6_reg0 <= minus6;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
minus3_reg1 <= minus3_reg0;
|
||||
minus4_reg1 <= minus4_reg0;
|
||||
minus5_reg1 <= minus5_reg0;
|
||||
minus6_reg1 <= minus6_reg0;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum1 <= din01_CN_CU_11bit + din02_CN_CU_11bit;
|
||||
sum2 <= din03_CN_CU_11bit + din04_CN_CU_11bit;
|
||||
sum3 <= din05_CN_CU_11bit + din06_CN_CU_11bit;
|
||||
sum4 <= sum1 + sum2;
|
||||
sum5 <= sum3 + din07_CHNL_CU_11bit_reg0;
|
||||
sum <= sum4 + sum5;
|
||||
|
||||
result_reg0 <= {sum[10]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
dout07_result_CU <= result_reg2;
|
||||
minus1 <= sum - din01_CN_CU_11bit_reg2;
|
||||
minus2 <= sum - din02_CN_CU_11bit_reg2;
|
||||
minus3 <= sum - din03_CN_CU_11bit_reg2;
|
||||
minus4 <= sum - din04_CN_CU_11bit_reg2;
|
||||
minus5 <= sum - din05_CN_CU_11bit_reg2;
|
||||
minus6 <= sum - din06_CN_CU_11bit_reg2;
|
||||
|
||||
if(minus1_reg0[10])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg0 + 11'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg0;
|
||||
if(minus1_reg1[10]) begin//限幅操作
|
||||
if(minus1_abs>11'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
|
||||
// dout01_CU <= minus1_reg1;
|
||||
end else begin
|
||||
if(minus1_abs>11'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
|
||||
// dout01_CU <= minus1_reg1;
|
||||
end
|
||||
|
||||
if(minus2_reg0[10])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg0 + 11'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg0;
|
||||
if(minus2_reg1[10]) begin//限幅操作
|
||||
if(minus2_abs>11'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
|
||||
// dout02_CU <= minus2_reg1;
|
||||
end else begin
|
||||
if(minus2_abs>11'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
|
||||
// dout02_CU <= minus2_reg1;
|
||||
end
|
||||
|
||||
if(minus3_reg0[10])//限幅前求绝对值操作
|
||||
minus3_abs <= ~minus3_reg0 + 11'd1;
|
||||
else
|
||||
minus3_abs <= minus3_reg0;
|
||||
if(minus3_reg1[10]) begin//限幅操作
|
||||
if(minus3_abs>11'd127)
|
||||
dout03_CU <= -8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
|
||||
// dout03_CU <= minus3_reg1;
|
||||
end else begin
|
||||
if(minus3_abs>11'd127)
|
||||
dout03_CU <= 8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
|
||||
// dout03_CU <= minus3_reg1;
|
||||
end
|
||||
|
||||
if(minus4_reg0[10])//限幅前求绝对值操作
|
||||
minus4_abs <= ~minus4_reg0 + 11'd1;
|
||||
else
|
||||
minus4_abs <= minus4_reg0;
|
||||
if(minus4_reg1[10]) begin//限幅操作
|
||||
if(minus4_abs>11'd127)
|
||||
dout04_CU <= -8'd127;
|
||||
else
|
||||
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
|
||||
// dout04_CU <= minus4_reg1;
|
||||
end else begin
|
||||
if(minus4_abs>11'd127)
|
||||
dout04_CU <= 8'd127;
|
||||
else
|
||||
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
|
||||
// dout04_CU <= minus4_reg1;
|
||||
end
|
||||
|
||||
if(minus5_reg0[10])//限幅前求绝对值操作
|
||||
minus5_abs <= ~minus5_reg0 + 11'd1;
|
||||
else
|
||||
minus5_abs <= minus5_reg0;
|
||||
if(minus5_reg1[10]) begin//限幅操作
|
||||
if(minus5_abs>11'd127)
|
||||
dout05_CU <= -8'd127;
|
||||
else
|
||||
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
|
||||
// dout05_CU <= minus5_reg1;
|
||||
end else begin
|
||||
if(minus5_abs>11'd127)
|
||||
dout05_CU <= 8'd127;
|
||||
else
|
||||
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
|
||||
// dout05_CU <= minus5_reg1;
|
||||
end
|
||||
|
||||
if(minus6_reg0[10])//限幅前求绝对值操作
|
||||
minus6_abs <= ~minus6_reg0 + 11'd1;
|
||||
else
|
||||
minus6_abs <= minus6_reg0;
|
||||
if(minus6_reg1[10]) begin//限幅操作
|
||||
if(minus6_abs>11'd127)
|
||||
dout06_CU <= -8'd127;
|
||||
else
|
||||
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
|
||||
// dout06_CU <= minus6_reg1;
|
||||
end else begin
|
||||
if(minus6_abs>11'd127)
|
||||
dout06_CU <= 8'd127;
|
||||
else
|
||||
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
|
||||
// dout06_CU <= minus6_reg1;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
+937
@@ -0,0 +1,937 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VN_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VN_PRO
|
||||
#(
|
||||
parameter MAX_ITER_NUM = 6'd14, //最大迭代次数
|
||||
parameter WIDTH = 4'd8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_VN,
|
||||
input start_VN, // VN更新启动脉冲
|
||||
input start_frame_VN, // VN更新启动脉冲(新的1帧的开始)
|
||||
|
||||
input [WIDTH-1:0] CHNL_dout_01,//信道信息输入
|
||||
input [WIDTH-1:0] CHNL_dout_02,
|
||||
input [WIDTH-1:0] CHNL_dout_03,
|
||||
input [WIDTH-1:0] CHNL_dout_04,
|
||||
|
||||
//校验节点信息输入，H阵第１行
|
||||
input [WIDTH-1:0] CN1_dout_01_00,
|
||||
input [WIDTH-1:0] CN1_dout_02_00, //后面的00代表H阵原模图的IM
|
||||
input [WIDTH-1:0] CN1_dout_02_01, //后面的01代表H阵原模图的II1
|
||||
|
||||
|
||||
input [WIDTH-1:0] CN2_dout_01_00,
|
||||
input [WIDTH-1:0] CN2_dout_02_00,
|
||||
input [WIDTH-1:0] CN2_dout_03_00,
|
||||
input [WIDTH-1:0] CN2_dout_04_02, //后面的02代表H阵原模图的II2
|
||||
input [WIDTH-1:0] CN2_dout_04_03, //后面的03代表H阵原模图的II3
|
||||
input [WIDTH-1:0] CN2_dout_04_04, //后面的04代表H阵原模图的II4
|
||||
//校验节点信息输入，H阵第３行
|
||||
input [WIDTH-1:0] CN3_dout_01_00,
|
||||
input [WIDTH-1:0] CN3_dout_02_05, //后面的05代表H阵原模图的II5
|
||||
input [WIDTH-1:0] CN3_dout_02_06, //后面的06代表H阵原模图的II6
|
||||
input [WIDTH-1:0] CN3_dout_03_07, //后面的07代表H阵原模图的II7
|
||||
input [WIDTH-1:0] CN3_dout_03_08, //后面的08代表H阵原模图的II8
|
||||
input [WIDTH-1:0] CN3_dout_04_00,
|
||||
|
||||
|
||||
output ask_din, //向数据缓存区请求信道数据
|
||||
|
||||
//校验节点信息读地址，H阵第１行
|
||||
output reg [8:0] CN1_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] CN1_addr_rd_02_00=10'd1023,
|
||||
output reg [9:0] CN1_addr_rd_02_01=10'd511,
|
||||
|
||||
//校验节点信息读地址，H阵第２行
|
||||
output reg [8:0] CN2_addr_rd_01_00=9'd511,
|
||||
output reg [8:0] CN2_addr_rd_02_00=9'd511,
|
||||
output reg [8:0] CN2_addr_rd_03_00=9'd511,
|
||||
output reg [9:0] CN2_addr_rd_04_02=10'd1023,
|
||||
output reg [9:0] CN2_addr_rd_04_03=10'd511,
|
||||
output reg [8:0] CN2_addr_rd_04_04=9'd511,
|
||||
|
||||
//校验节点信息读地址，H阵第３行
|
||||
output reg [8:0] CN3_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] CN3_addr_rd_02_05=10'd1023,
|
||||
output reg [9:0] CN3_addr_rd_02_06=10'd511,
|
||||
output reg [9:0] CN3_addr_rd_03_07=10'd1023,
|
||||
output reg [9:0] CN3_addr_rd_03_08=10'd511,
|
||||
output reg [8:0] CN3_addr_rd_04_00=9'd511,
|
||||
|
||||
//变量节点写使能
|
||||
output reg [0:0] VN_wea=1'd0,
|
||||
|
||||
//变量节点写地址，H阵第１行
|
||||
output reg [8:0] VN1_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] VN1_addr_wr_02_00=10'd1023,
|
||||
output reg [9:0] VN1_addr_wr_02_01=10'd511,
|
||||
|
||||
//变量节点写地址，H阵第２行
|
||||
output reg [8:0] VN2_addr_wr_01_00=9'd511,
|
||||
output reg [8:0] VN2_addr_wr_02_00=9'd511,
|
||||
output reg [8:0] VN2_addr_wr_03_00=9'd511,
|
||||
output reg [9:0] VN2_addr_wr_04_02=10'd1023,
|
||||
output reg [9:0] VN2_addr_wr_04_03=10'd511,
|
||||
output reg [8:0] VN2_addr_wr_04_04=9'd511,
|
||||
|
||||
//变量节点写地址，H阵第３行
|
||||
output reg [8:0] VN3_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] VN3_addr_wr_02_05=10'd1023,
|
||||
output reg [9:0] VN3_addr_wr_02_06=10'd511,
|
||||
output reg [9:0] VN3_addr_wr_03_07=10'd1023,
|
||||
output reg [9:0] VN3_addr_wr_03_08=10'd511,
|
||||
output reg [8:0] VN3_addr_wr_04_00=9'd511,
|
||||
|
||||
|
||||
//变量节点写数据，H阵第１行
|
||||
output reg [WIDTH-1:0] VN1_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN1_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN1_din_02_01=8'd0,
|
||||
|
||||
//变量节点写数据，H阵第２行
|
||||
output reg [WIDTH-1:0] VN2_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_03_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_02=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_03=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_04=8'd0,
|
||||
|
||||
//变量节点写数据，H阵第３行
|
||||
output reg [WIDTH-1:0] VN3_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_02_05=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_02_06=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_03_07=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_03_08=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_04_00=8'd0,
|
||||
|
||||
//判决结果写使能
|
||||
output reg [0:0] DR_wea=8'd0,
|
||||
|
||||
//判决结果写地址
|
||||
output reg [8:0] DR_addr_wr=9'd511,
|
||||
|
||||
output reg [0:0] DR_din_01=1'd0, //判决结果写数据
|
||||
output reg [0:0] DR_din_02=1'd0,
|
||||
output reg [0:0] DR_din_03=1'd0,
|
||||
output reg [0:0] DR_din_04=1'd0,
|
||||
output reg [0:0] DR_din_05=1'd0,
|
||||
|
||||
|
||||
output data_start_ck_VN, //产生判决结果数据开始存储标志，高脉冲
|
||||
output data_start_VN, //产生判决结果数据可以输出标志，高脉冲
|
||||
output end_VN //模块结束标志，高脉冲
|
||||
);
|
||||
|
||||
assign ask_din = (rst_VN) ? 1'd0 : ((start_VN) ? 1'd1:1'd0);
|
||||
|
||||
reg [5:0] iter_num = 6'd0;
|
||||
// 迭代次数控制
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN || start_frame_VN) begin
|
||||
iter_num <= 6'd0;
|
||||
end else begin
|
||||
if(end_VN)
|
||||
if (iter_num < MAX_ITER_NUM)
|
||||
iter_num <= iter_num + 6'd1;
|
||||
else
|
||||
iter_num <= iter_num;
|
||||
else
|
||||
iter_num <= iter_num;
|
||||
end
|
||||
end
|
||||
|
||||
reg [10:0] cnt_VN= 11'd0,cnt_2_VN= 11'd0;
|
||||
reg flag_VN=1'd0;
|
||||
// 产生该模块的计数基准
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
cnt_VN <= 11'd0;
|
||||
cnt_2_VN <= 11'd0;
|
||||
flag_VN <= 1'b0;
|
||||
end else begin
|
||||
if(start_VN) begin
|
||||
flag_VN <= 1'b1;
|
||||
cnt_VN <= 11'd0;
|
||||
cnt_2_VN <= 11'd0;
|
||||
end else begin
|
||||
if(flag_VN) begin
|
||||
if(cnt_VN<11'd560)begin
|
||||
flag_VN <= flag_VN;
|
||||
cnt_VN <= cnt_VN + 11'd1;
|
||||
end else begin
|
||||
cnt_VN <= cnt_VN;
|
||||
flag_VN<= 1'b0;
|
||||
end
|
||||
if(cnt_2_VN<11'd560)begin
|
||||
flag_VN <= flag_VN;
|
||||
cnt_2_VN <= cnt_2_VN + 11'd1;
|
||||
end else begin
|
||||
cnt_2_VN <= cnt_2_VN;
|
||||
flag_VN<= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_VN <= cnt_VN;
|
||||
cnt_2_VN <= cnt_2_VN;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
parameter DELAY_RD = 11'd3;
|
||||
|
||||
// 对所有IM进行CN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
CN1_addr_rd_01_00 <= 9'd511;
|
||||
CN1_addr_rd_02_00 <= 10'd1023;
|
||||
CN2_addr_rd_01_00 <= 9'd511;
|
||||
CN2_addr_rd_02_00 <= 9'd511;
|
||||
CN2_addr_rd_03_00 <= 9'd511;
|
||||
CN3_addr_rd_01_00 <= 9'd511;
|
||||
CN3_addr_rd_04_00 <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin
|
||||
CN1_addr_rd_01_00 <= CN1_addr_rd_01_00 + 9'd1;
|
||||
CN1_addr_rd_02_00 <= CN1_addr_rd_02_00 + 10'd1;
|
||||
CN2_addr_rd_01_00 <= CN2_addr_rd_01_00 + 9'd1;
|
||||
CN2_addr_rd_02_00 <= CN2_addr_rd_02_00 + 9'd1;
|
||||
CN2_addr_rd_03_00 <= CN2_addr_rd_03_00 + 9'd1;
|
||||
CN3_addr_rd_01_00 <= CN3_addr_rd_01_00 + 9'd1;
|
||||
CN3_addr_rd_04_00 <= CN3_addr_rd_04_00 + 9'd1;
|
||||
end else begin
|
||||
CN1_addr_rd_01_00 <= 9'd511;
|
||||
CN1_addr_rd_02_00 <= 10'd1023;
|
||||
CN2_addr_rd_01_00 <= 9'd511;
|
||||
CN2_addr_rd_02_00 <= 9'd511;
|
||||
CN2_addr_rd_03_00 <= 9'd511;
|
||||
CN3_addr_rd_01_00 <= 9'd511;
|
||||
CN3_addr_rd_04_00 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg first_flag_cn_01=1'd1,first_flag_cn_02=1'd1,first_flag_cn_03=1'd1,first_flag_cn_04=1'd1;
|
||||
reg first_flag_cn_05=1'd1,first_flag_cn_06=1'd1,first_flag_cn_07=1'd1,first_flag_cn_08=1'd1;
|
||||
reg first_flag_vn_01=1'd1,first_flag_vn_02=1'd1,first_flag_vn_03=1'd1,first_flag_vn_04=1'd1;
|
||||
reg first_flag_vn_05=1'd1,first_flag_vn_06=1'd1,first_flag_vn_07=1'd1,first_flag_vn_08=1'd1;
|
||||
|
||||
// 对II1-II8进行CN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
CN1_addr_rd_02_01 <= 10'd639;
|
||||
CN2_addr_rd_04_02 <= 10'd24;
|
||||
CN2_addr_rd_04_03 <= 10'd926;
|
||||
CN2_addr_rd_04_04 <= 9'd294;
|
||||
CN3_addr_rd_02_05 <= 10'd352;
|
||||
CN3_addr_rd_02_06 <= 10'd639;
|
||||
CN3_addr_rd_03_07 <= 10'd12;
|
||||
CN3_addr_rd_03_08 <= 10'd929;
|
||||
first_flag_cn_01 <= 1'd1;
|
||||
first_flag_cn_02 <= 1'd1;
|
||||
first_flag_cn_03 <= 1'd1;
|
||||
first_flag_cn_04 <= 1'd1;
|
||||
first_flag_cn_05 <= 1'd1;
|
||||
first_flag_cn_06 <= 1'd1;
|
||||
first_flag_cn_07 <= 1'd1;
|
||||
first_flag_cn_08 <= 1'd1;
|
||||
end else begin
|
||||
if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin
|
||||
//对II1地址进行操作，确保初始化地址先加1
|
||||
if (first_flag_cn_05) begin
|
||||
CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1;
|
||||
first_flag_cn_05 <= 1'd0;
|
||||
end else begin
|
||||
if (CN1_addr_rd_02_01 == 10'd1023)
|
||||
CN1_addr_rd_02_01 <= 10'd624;
|
||||
else if (CN1_addr_rd_02_01 == 10'd639)
|
||||
CN1_addr_rd_02_01 <= 10'd512;
|
||||
else
|
||||
CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1;
|
||||
end
|
||||
// 对II2地址进行操作
|
||||
if (first_flag_cn_06) begin
|
||||
CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1;
|
||||
first_flag_cn_06<= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_02 == 10'd127)
|
||||
CN2_addr_rd_04_02 <= 10'd0;
|
||||
else if (CN2_addr_rd_04_02 == 10'd24)
|
||||
CN2_addr_rd_04_02 <= 10'd203;
|
||||
else if (CN2_addr_rd_04_02 == 10'd255)
|
||||
CN2_addr_rd_04_02 <= 10'd128;
|
||||
else if (CN2_addr_rd_04_02 == 10'd202)
|
||||
CN2_addr_rd_04_02 <= 10'd376;
|
||||
else if (CN2_addr_rd_04_02 == 10'd383)
|
||||
CN2_addr_rd_04_02 <= 10'd256;
|
||||
else if (CN2_addr_rd_04_02 == 10'd375)
|
||||
CN2_addr_rd_04_02 <= 10'd477;
|
||||
else if (CN2_addr_rd_04_02 == 10'd511)
|
||||
CN2_addr_rd_04_02 <= 10'd384;
|
||||
else
|
||||
CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1;
|
||||
end
|
||||
// 对II3地址进行操作
|
||||
if (first_flag_cn_07) begin
|
||||
CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1;
|
||||
first_flag_cn_07 <= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_03 == 10'd1023)
|
||||
CN2_addr_rd_04_03 <= 10'd896;
|
||||
else if (CN2_addr_rd_04_03 == 10'd926)
|
||||
CN2_addr_rd_04_03 <= 10'd535;
|
||||
else if (CN2_addr_rd_04_03 == 10'd639)
|
||||
CN2_addr_rd_04_03 <= 10'd512;
|
||||
else if (CN2_addr_rd_04_03 == 10'd534)
|
||||
CN2_addr_rd_04_03 <= 10'd694;
|
||||
else if (CN2_addr_rd_04_03 == 10'd767)
|
||||
CN2_addr_rd_04_03 <= 10'd640;
|
||||
else if (CN2_addr_rd_04_03 == 10'd693)
|
||||
CN2_addr_rd_04_03 <= 10'd777;
|
||||
else if (CN2_addr_rd_04_03 == 10'd895)
|
||||
CN2_addr_rd_04_03 <= 10'd768;
|
||||
else
|
||||
CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1;
|
||||
end
|
||||
// 对II4地址进行操作
|
||||
if (first_flag_cn_08) begin
|
||||
CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1;
|
||||
first_flag_cn_08 <= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_04 == 9'd383)
|
||||
CN2_addr_rd_04_04 <= 9'd256;
|
||||
else if (CN2_addr_rd_04_04 == 9'd294)
|
||||
CN2_addr_rd_04_04 <= 9'd400;
|
||||
else if (CN2_addr_rd_04_04 == 9'd511)
|
||||
CN2_addr_rd_04_04 <= 9'd384;
|
||||
else if (CN2_addr_rd_04_04 == 9'd399)
|
||||
CN2_addr_rd_04_04 <= 9'd0;
|
||||
else if (CN2_addr_rd_04_04 == 9'd127)
|
||||
CN2_addr_rd_04_04 <= 9'd211;
|
||||
else if (CN2_addr_rd_04_04 == 9'd255)
|
||||
CN2_addr_rd_04_04 <= 9'd128;
|
||||
else
|
||||
CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1;
|
||||
end
|
||||
// 对II5地址进行操作
|
||||
if (first_flag_cn_01) begin //确保初始化地址先加1
|
||||
CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1;
|
||||
first_flag_cn_01 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_02_05 == 10'd383)
|
||||
CN3_addr_rd_02_05 <= 10'd256;
|
||||
else if (CN3_addr_rd_02_05 == 10'd352)
|
||||
CN3_addr_rd_02_05 <= 10'd448;
|
||||
else if (CN3_addr_rd_02_05 == 10'd511)
|
||||
CN3_addr_rd_02_05 <= 10'd384;
|
||||
else if (CN3_addr_rd_02_05 == 10'd447)
|
||||
CN3_addr_rd_02_05 <= 10'd78;
|
||||
else if (CN3_addr_rd_02_05 == 10'd127)
|
||||
CN3_addr_rd_02_05 <= 10'd0;
|
||||
else if (CN3_addr_rd_02_05 == 10'd77)
|
||||
CN3_addr_rd_02_05 <= 10'd209;
|
||||
else if (CN3_addr_rd_02_05 == 10'd255)
|
||||
CN3_addr_rd_02_05 <= 10'd128;
|
||||
else
|
||||
CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1;
|
||||
end
|
||||
// 对II6地址进行操作
|
||||
if (first_flag_cn_02) begin
|
||||
CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1;
|
||||
first_flag_cn_02 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_02_06 == 10'd767)
|
||||
CN3_addr_rd_02_06 <= 10'd774;
|
||||
else if (CN3_addr_rd_02_06 == 10'd895)
|
||||
CN3_addr_rd_02_06 <= 10'd768;
|
||||
else if (CN3_addr_rd_02_06 == 10'd773)
|
||||
CN3_addr_rd_02_06 <= 10'd931;
|
||||
else if (CN3_addr_rd_02_06 == 10'd1023)
|
||||
CN3_addr_rd_02_06 <= 10'd896;
|
||||
else if (CN3_addr_rd_02_06 == 10'd930)
|
||||
CN3_addr_rd_02_06 <= 10'd611;
|
||||
else if (CN3_addr_rd_02_06 == 10'd639)
|
||||
CN3_addr_rd_02_06 <= 10'd512;
|
||||
else
|
||||
CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1;
|
||||
end
|
||||
// 对II7地址进行操作
|
||||
if (first_flag_cn_03) begin //确保初始化地址先加1
|
||||
CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1;
|
||||
first_flag_cn_03 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_03_07 == 10'd127)
|
||||
CN3_addr_rd_03_07 <= 10'd0;
|
||||
else if (CN3_addr_rd_03_07 == 10'd12)
|
||||
CN3_addr_rd_03_07 <= 10'd197;
|
||||
else if (CN3_addr_rd_03_07 == 10'd255)
|
||||
CN3_addr_rd_03_07 <= 10'd128;
|
||||
else if (CN3_addr_rd_03_07 == 10'd196)
|
||||
CN3_addr_rd_03_07 <= 10'd383;
|
||||
else if (CN3_addr_rd_03_07 == 10'd383)
|
||||
CN3_addr_rd_03_07 <= 10'd256;
|
||||
else if (CN3_addr_rd_03_07 == 10'd382)
|
||||
CN3_addr_rd_03_07 <= 10'd413;
|
||||
else if (CN3_addr_rd_03_07 == 10'd511)
|
||||
CN3_addr_rd_03_07 <= 10'd384;
|
||||
else
|
||||
CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1;
|
||||
end
|
||||
// 对II8地址进行操作
|
||||
if (first_flag_cn_04) begin
|
||||
CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1;
|
||||
first_flag_cn_04 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_03_08 == 10'd1023)
|
||||
CN3_addr_rd_03_08 <= 10'd896;
|
||||
else if (CN3_addr_rd_03_08 == 10'd929)
|
||||
CN3_addr_rd_03_08 <= 10'd610;
|
||||
else if (CN3_addr_rd_03_08 == 10'd639)
|
||||
CN3_addr_rd_03_08 <= 10'd512;
|
||||
else if (CN3_addr_rd_03_08 == 10'd609)
|
||||
CN3_addr_rd_03_08 <= 10'd666;
|
||||
else if (CN3_addr_rd_03_08 == 10'd767)
|
||||
CN3_addr_rd_03_08 <= 10'd640;
|
||||
else if (CN3_addr_rd_03_08 == 10'd665)
|
||||
CN3_addr_rd_03_08 <= 10'd827;
|
||||
else if (CN3_addr_rd_03_08 == 10'd895)
|
||||
CN3_addr_rd_03_08 <= 10'd768;
|
||||
else
|
||||
CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1;
|
||||
end
|
||||
end else begin
|
||||
CN1_addr_rd_02_01 <= 10'd639;
|
||||
CN2_addr_rd_04_02 <= 10'd24;
|
||||
CN2_addr_rd_04_03 <= 10'd926;
|
||||
CN2_addr_rd_04_04 <= 9'd294;
|
||||
CN3_addr_rd_02_05 <= 10'd352;
|
||||
CN3_addr_rd_02_06 <= 10'd639;
|
||||
CN3_addr_rd_03_07 <= 10'd12;
|
||||
CN3_addr_rd_03_08 <= 10'd929;
|
||||
first_flag_cn_01 <= 1'd1;
|
||||
first_flag_cn_02 <= 1'd1;
|
||||
first_flag_cn_03 <= 1'd1;
|
||||
first_flag_cn_04 <= 1'd1;
|
||||
first_flag_cn_05 <= 1'd1;
|
||||
first_flag_cn_06 <= 1'd1;
|
||||
first_flag_cn_07 <= 1'd1;
|
||||
first_flag_cn_08 <= 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU01; //第1列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU01;
|
||||
wire [WIDTH-1:0] din03_CHNL_CU01;
|
||||
wire [WIDTH-1:0] dout01_CU01;
|
||||
wire [WIDTH-1:0] dout02_CU01;
|
||||
wire [0:0] dout03_result_CU01;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU02; //第2列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU02;
|
||||
wire [WIDTH-1:0] din03_CN_CU02;
|
||||
wire [WIDTH-1:0] din04_CHNL_CU02;
|
||||
wire [WIDTH-1:0] dout01_CU02;
|
||||
wire [WIDTH-1:0] dout02_CU02;
|
||||
wire [WIDTH-1:0] dout03_CU02;
|
||||
wire [0:0] dout04_result_CU02;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU03; //第3列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CHNL_CU03;
|
||||
wire [WIDTH-1:0] dout01_CU03;
|
||||
wire [0:0] dout02_result_CU03;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU04; //第4列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU04;
|
||||
wire [WIDTH-1:0] din03_CN_CU04;
|
||||
wire [WIDTH-1:0] din04_CHNL_CU04;
|
||||
wire [WIDTH-1:0] dout01_CU04;
|
||||
wire [WIDTH-1:0] dout02_CU04;
|
||||
wire [WIDTH-1:0] dout03_CU04;
|
||||
wire [0:0] dout04_result_CU04;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU05; //第5列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU05;
|
||||
wire [WIDTH-1:0] din03_CN_CU05;
|
||||
wire [WIDTH-1:0] din04_CN_CU05;
|
||||
wire [WIDTH-1:0] din05_CN_CU05;
|
||||
wire [WIDTH-1:0] din06_CN_CU05;
|
||||
wire [WIDTH-1:0] din07_CHNL_CU05;
|
||||
wire [WIDTH-1:0] dout01_CU05;
|
||||
wire [WIDTH-1:0] dout02_CU05;
|
||||
wire [WIDTH-1:0] dout03_CU05;
|
||||
wire [WIDTH-1:0] dout04_CU05;
|
||||
wire [WIDTH-1:0] dout05_CU05;
|
||||
wire [WIDTH-1:0] dout06_CU05;
|
||||
wire [0:0] dout07_result_CU05;
|
||||
|
||||
// CU模块的输入
|
||||
assign din01_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_01_00;
|
||||
assign din02_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_01_00;
|
||||
|
||||
assign din01_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_02_00;
|
||||
assign din02_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_05;
|
||||
assign din03_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_06;
|
||||
|
||||
assign din01_CN_CU03 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_01_00;
|
||||
|
||||
assign din01_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_03_00;
|
||||
assign din02_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_07;
|
||||
assign din03_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_08;
|
||||
|
||||
assign din01_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_00;
|
||||
assign din02_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_01;
|
||||
assign din03_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_02;
|
||||
assign din04_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_03;
|
||||
assign din05_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_04;
|
||||
assign din06_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_04_00;
|
||||
|
||||
assign din03_CHNL_CU01 = CHNL_dout_01;
|
||||
assign din04_CHNL_CU02 = CHNL_dout_02;
|
||||
assign din02_CHNL_CU03 = CHNL_dout_03;
|
||||
assign din04_CHNL_CU04 = CHNL_dout_04;
|
||||
assign din07_CHNL_CU05 = 8'd0; //信道传输的数据只有2048bit，这里H矩阵是2560bit，所以在后512位上补0
|
||||
|
||||
|
||||
|
||||
VNU_2din CU_01 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU01),
|
||||
.din02_CN_CU(din02_CN_CU01),
|
||||
.din03_CHNL_CU(din03_CHNL_CU01),
|
||||
.dout01_CU(dout01_CU01),
|
||||
.dout02_CU(dout02_CU01),
|
||||
.dout03_result_CU(dout03_result_CU01));
|
||||
|
||||
VNU_3din CU_02 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU02),
|
||||
.din02_CN_CU(din02_CN_CU02),
|
||||
.din03_CN_CU(din03_CN_CU02),
|
||||
.din04_CHNL_CU(din04_CHNL_CU02),
|
||||
.dout01_CU(dout01_CU02),
|
||||
.dout02_CU(dout02_CU02),
|
||||
.dout03_CU(dout03_CU02),
|
||||
.dout04_result_CU(dout04_result_CU02)
|
||||
);
|
||||
|
||||
VNU_1din CU_03 (.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU03),
|
||||
.din02_CHNL_CU(din02_CHNL_CU03),
|
||||
.dout01_CU(dout01_CU03),
|
||||
.dout02_result_CU(dout02_result_CU03));
|
||||
|
||||
VNU_3din CU_04 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU04),
|
||||
.din02_CN_CU(din02_CN_CU04),
|
||||
.din03_CN_CU(din03_CN_CU04),
|
||||
.din04_CHNL_CU(din04_CHNL_CU04),
|
||||
.dout01_CU(dout01_CU04),
|
||||
.dout02_CU(dout02_CU04),
|
||||
.dout03_CU(dout03_CU04),
|
||||
.dout04_result_CU(dout04_result_CU04)
|
||||
);
|
||||
|
||||
VNU_6din CU_05 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU05),
|
||||
.din02_CN_CU(din02_CN_CU05),
|
||||
.din03_CN_CU(din03_CN_CU05),
|
||||
.din04_CN_CU(din04_CN_CU05),
|
||||
.din05_CN_CU(din05_CN_CU05),
|
||||
.din06_CN_CU(din06_CN_CU05),
|
||||
.din07_CHNL_CU(din07_CHNL_CU05),
|
||||
.dout01_CU(dout01_CU05),
|
||||
.dout02_CU(dout02_CU05),
|
||||
.dout03_CU(dout03_CU05),
|
||||
.dout04_CU(dout04_CU05),
|
||||
.dout05_CU(dout05_CU05),
|
||||
.dout06_CU(dout06_CU05),
|
||||
.dout07_result_CU(dout07_result_CU05)
|
||||
);
|
||||
|
||||
|
||||
// 设置写操作的时延
|
||||
parameter DELAY_WR = 11'd17;
|
||||
|
||||
// 控制VN的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
VN_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR)
|
||||
VN_wea <= 1'd1;
|
||||
else
|
||||
VN_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN存储的写地址(所有IM)
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_addr_wr_01_00 <= 9'd511;
|
||||
VN1_addr_wr_02_00 <= 10'd1023;
|
||||
VN2_addr_wr_01_00 <= 9'd511;
|
||||
VN2_addr_wr_02_00 <= 9'd511;
|
||||
VN2_addr_wr_03_00 <= 9'd511;
|
||||
VN3_addr_wr_01_00 <= 9'd511;
|
||||
VN3_addr_wr_04_00 <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
VN1_addr_wr_01_00 <= VN1_addr_wr_01_00 + 9'd1;
|
||||
VN1_addr_wr_02_00 <= VN1_addr_wr_02_00 + 10'd1;
|
||||
VN2_addr_wr_01_00 <= VN2_addr_wr_01_00 + 9'd1;
|
||||
VN2_addr_wr_02_00 <= VN2_addr_wr_02_00 + 9'd1;
|
||||
VN2_addr_wr_03_00 <= VN2_addr_wr_03_00 + 9'd1;
|
||||
VN3_addr_wr_01_00 <= VN3_addr_wr_01_00 + 9'd1;
|
||||
VN3_addr_wr_04_00 <= VN3_addr_wr_04_00 + 9'd1;
|
||||
end else begin
|
||||
VN1_addr_wr_01_00 <= 9'd511;
|
||||
VN1_addr_wr_02_00 <= 10'd1023;
|
||||
VN2_addr_wr_01_00 <= 9'd511;
|
||||
VN2_addr_wr_02_00 <= 9'd511;
|
||||
VN2_addr_wr_03_00 <= 9'd511;
|
||||
VN3_addr_wr_01_00 <= 9'd511;
|
||||
VN3_addr_wr_04_00 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN存储的写地址(II1-II8)
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_addr_wr_02_01 <= 10'd639;
|
||||
VN2_addr_wr_04_02 <= 10'd24;
|
||||
VN2_addr_wr_04_03 <= 10'd926;
|
||||
VN2_addr_wr_04_04 <= 9'd294;
|
||||
VN3_addr_wr_02_05 <= 10'd352;
|
||||
VN3_addr_wr_02_06 <= 10'd639;
|
||||
VN3_addr_wr_03_07 <= 10'd12;
|
||||
VN3_addr_wr_03_08 <= 10'd929;
|
||||
first_flag_vn_01 <= 1'd1;
|
||||
first_flag_vn_02 <= 1'd1;
|
||||
first_flag_vn_03 <= 1'd1;
|
||||
first_flag_vn_04 <= 1'd1;
|
||||
first_flag_vn_05 <= 1'd1;
|
||||
first_flag_vn_06 <= 1'd1;
|
||||
first_flag_vn_07 <= 1'd1;
|
||||
first_flag_vn_08 <= 1'd1;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
//对II1地址进行操作，确保初始化地址先加1
|
||||
if (first_flag_vn_05) begin
|
||||
VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1;
|
||||
first_flag_vn_05 <= 1'd0;
|
||||
end else begin
|
||||
if (VN1_addr_wr_02_01 == 10'd1023)
|
||||
VN1_addr_wr_02_01 <= 10'd624;
|
||||
else if (VN1_addr_wr_02_01 == 10'd639)
|
||||
VN1_addr_wr_02_01 <= 10'd512;
|
||||
else
|
||||
VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1;
|
||||
end
|
||||
// 对II2地址进行操作
|
||||
if (first_flag_vn_06) begin
|
||||
VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1;
|
||||
first_flag_vn_06<= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_02 == 10'd127)
|
||||
VN2_addr_wr_04_02 <= 10'd0;
|
||||
else if (VN2_addr_wr_04_02 == 10'd24)
|
||||
VN2_addr_wr_04_02 <= 10'd203;
|
||||
else if (VN2_addr_wr_04_02 == 10'd255)
|
||||
VN2_addr_wr_04_02 <= 10'd128;
|
||||
else if (VN2_addr_wr_04_02 == 10'd202)
|
||||
VN2_addr_wr_04_02 <= 10'd376;
|
||||
else if (VN2_addr_wr_04_02 == 10'd383)
|
||||
VN2_addr_wr_04_02 <= 10'd256;
|
||||
else if (VN2_addr_wr_04_02 == 10'd375)
|
||||
VN2_addr_wr_04_02 <= 10'd477;
|
||||
else if (VN2_addr_wr_04_02 == 10'd511)
|
||||
VN2_addr_wr_04_02 <= 10'd384;
|
||||
else
|
||||
VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1;
|
||||
end
|
||||
// 对II3地址进行操作
|
||||
if (first_flag_vn_07) begin
|
||||
VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1;
|
||||
first_flag_vn_07 <= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_03 == 10'd1023)
|
||||
VN2_addr_wr_04_03 <= 10'd896;
|
||||
else if (VN2_addr_wr_04_03 == 10'd926)
|
||||
VN2_addr_wr_04_03 <= 10'd535;
|
||||
else if (VN2_addr_wr_04_03 == 10'd639)
|
||||
VN2_addr_wr_04_03 <= 10'd512;
|
||||
else if (VN2_addr_wr_04_03 == 10'd534)
|
||||
VN2_addr_wr_04_03 <= 10'd694;
|
||||
else if (VN2_addr_wr_04_03 == 10'd767)
|
||||
VN2_addr_wr_04_03 <= 10'd640;
|
||||
else if (VN2_addr_wr_04_03 == 10'd693)
|
||||
VN2_addr_wr_04_03 <= 10'd777;
|
||||
else if (VN2_addr_wr_04_03 == 10'd895)
|
||||
VN2_addr_wr_04_03 <= 10'd768;
|
||||
else
|
||||
VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1;
|
||||
end
|
||||
// 对II4地址进行操作
|
||||
if (first_flag_vn_08) begin
|
||||
VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1;
|
||||
first_flag_vn_08 <= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_04 == 9'd383)
|
||||
VN2_addr_wr_04_04 <= 9'd256;
|
||||
else if (VN2_addr_wr_04_04 == 9'd294)
|
||||
VN2_addr_wr_04_04 <= 9'd400;
|
||||
else if (VN2_addr_wr_04_04 == 9'd511)
|
||||
VN2_addr_wr_04_04 <= 9'd384;
|
||||
else if (VN2_addr_wr_04_04 == 9'd399)
|
||||
VN2_addr_wr_04_04 <= 9'd0;
|
||||
else if (VN2_addr_wr_04_04 == 9'd127)
|
||||
VN2_addr_wr_04_04 <= 9'd211;
|
||||
else if (VN2_addr_wr_04_04 == 9'd255)
|
||||
VN2_addr_wr_04_04 <= 9'd128;
|
||||
else
|
||||
VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1;
|
||||
end
|
||||
// 对II5地址进行操作
|
||||
if (first_flag_vn_01) begin //确保初始化地址先加1
|
||||
VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1;
|
||||
first_flag_vn_01 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_02_05 == 10'd383)
|
||||
VN3_addr_wr_02_05 <= 10'd256;
|
||||
else if (VN3_addr_wr_02_05 == 10'd352)
|
||||
VN3_addr_wr_02_05 <= 10'd448;
|
||||
else if (VN3_addr_wr_02_05 == 10'd511)
|
||||
VN3_addr_wr_02_05 <= 10'd384;
|
||||
else if (VN3_addr_wr_02_05 == 10'd447)
|
||||
VN3_addr_wr_02_05 <= 10'd78;
|
||||
else if (VN3_addr_wr_02_05 == 10'd127)
|
||||
VN3_addr_wr_02_05 <= 10'd0;
|
||||
else if (VN3_addr_wr_02_05 == 10'd77)
|
||||
VN3_addr_wr_02_05 <= 10'd209;
|
||||
else if (VN3_addr_wr_02_05 == 10'd255)
|
||||
VN3_addr_wr_02_05 <= 10'd128;
|
||||
else
|
||||
VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1;
|
||||
end
|
||||
// 对II6地址进行操作
|
||||
if (first_flag_vn_02) begin
|
||||
VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1;
|
||||
first_flag_vn_02 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_02_06 == 10'd767)
|
||||
VN3_addr_wr_02_06 <= 10'd774;
|
||||
else if (VN3_addr_wr_02_06 == 10'd895)
|
||||
VN3_addr_wr_02_06 <= 10'd768;
|
||||
else if (VN3_addr_wr_02_06 == 10'd773)
|
||||
VN3_addr_wr_02_06 <= 10'd931;
|
||||
else if (VN3_addr_wr_02_06 == 10'd1023)
|
||||
VN3_addr_wr_02_06 <= 10'd896;
|
||||
else if (VN3_addr_wr_02_06 == 10'd930)
|
||||
VN3_addr_wr_02_06 <= 10'd611;
|
||||
else if (VN3_addr_wr_02_06 == 10'd639)
|
||||
VN3_addr_wr_02_06 <= 10'd512;
|
||||
else
|
||||
VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1;
|
||||
end
|
||||
// 对II7地址进行操作
|
||||
if (first_flag_vn_03) begin //确保初始化地址先加1
|
||||
VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1;
|
||||
first_flag_vn_03 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_03_07 == 10'd127)
|
||||
VN3_addr_wr_03_07 <= 10'd0;
|
||||
else if (VN3_addr_wr_03_07 == 10'd12)
|
||||
VN3_addr_wr_03_07 <= 10'd197;
|
||||
else if (VN3_addr_wr_03_07 == 10'd255)
|
||||
VN3_addr_wr_03_07 <= 10'd128;
|
||||
else if (VN3_addr_wr_03_07 == 10'd196)
|
||||
VN3_addr_wr_03_07 <= 10'd383;
|
||||
else if (VN3_addr_wr_03_07 == 10'd383)
|
||||
VN3_addr_wr_03_07 <= 10'd256;
|
||||
else if (VN3_addr_wr_03_07 == 10'd382)
|
||||
VN3_addr_wr_03_07 <= 10'd413;
|
||||
else if (VN3_addr_wr_03_07 == 10'd511)
|
||||
VN3_addr_wr_03_07 <= 10'd384;
|
||||
else
|
||||
VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1;
|
||||
end
|
||||
// 对II8地址进行操作
|
||||
if (first_flag_vn_04) begin
|
||||
VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1;
|
||||
first_flag_vn_04 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_03_08 == 10'd1023)
|
||||
VN3_addr_wr_03_08 <= 10'd896;
|
||||
else if (VN3_addr_wr_03_08 == 10'd929)
|
||||
VN3_addr_wr_03_08 <= 10'd610;
|
||||
else if (VN3_addr_wr_03_08 == 10'd639)
|
||||
VN3_addr_wr_03_08 <= 10'd512;
|
||||
else if (VN3_addr_wr_03_08 == 10'd609)
|
||||
VN3_addr_wr_03_08 <= 10'd666;
|
||||
else if (VN3_addr_wr_03_08 == 10'd767)
|
||||
VN3_addr_wr_03_08 <= 10'd640;
|
||||
else if (VN3_addr_wr_03_08 == 10'd665)
|
||||
VN3_addr_wr_03_08 <= 10'd827;
|
||||
else if (VN3_addr_wr_03_08 == 10'd895)
|
||||
VN3_addr_wr_03_08 <= 10'd768;
|
||||
else
|
||||
VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1;
|
||||
end
|
||||
end else begin
|
||||
VN1_addr_wr_02_01 <= 10'd639;
|
||||
VN2_addr_wr_04_02 <= 10'd24;
|
||||
VN2_addr_wr_04_03 <= 10'd926;
|
||||
VN2_addr_wr_04_04 <= 9'd294;
|
||||
VN3_addr_wr_02_05 <= 10'd352;
|
||||
VN3_addr_wr_02_06 <= 10'd639;
|
||||
VN3_addr_wr_03_07 <= 10'd12;
|
||||
VN3_addr_wr_03_08 <= 10'd929;
|
||||
first_flag_vn_01 <= 1'd1;
|
||||
first_flag_vn_02 <= 1'd1;
|
||||
first_flag_vn_03 <= 1'd1;
|
||||
first_flag_vn_04 <= 1'd1;
|
||||
first_flag_vn_05 <= 1'd1;
|
||||
first_flag_vn_06 <= 1'd1;
|
||||
first_flag_vn_07 <= 1'd1;
|
||||
first_flag_vn_08 <= 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_din_01_00 <= 8'd0;
|
||||
VN1_din_02_00 <= 8'd0;
|
||||
VN2_din_01_00 <= 8'd0;
|
||||
VN2_din_02_00 <= 8'd0;
|
||||
VN2_din_03_00 <= 8'd0;
|
||||
VN3_din_01_00 <= 8'd0;
|
||||
VN3_din_04_00 <= 8'd0;
|
||||
VN1_din_02_01 <= 8'd0;
|
||||
VN2_din_04_02 <= 8'd0;
|
||||
VN2_din_04_03 <= 8'd0;
|
||||
VN2_din_04_04 <= 8'd0;
|
||||
VN3_din_02_05 <= 8'd0;
|
||||
VN3_din_02_06 <= 8'd0;
|
||||
VN3_din_03_07 <= 8'd0;
|
||||
VN3_din_03_08 <= 8'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
VN1_din_01_00 <= dout01_CU03;
|
||||
VN1_din_02_00 <= dout01_CU05;
|
||||
VN2_din_01_00 <= dout01_CU01;
|
||||
VN2_din_02_00 <= dout01_CU02;
|
||||
VN2_din_03_00 <= dout01_CU04;
|
||||
VN3_din_01_00 <= dout02_CU01;
|
||||
VN3_din_04_00 <= dout06_CU05;
|
||||
VN1_din_02_01 <= dout02_CU05;
|
||||
VN2_din_04_02 <= dout03_CU05;
|
||||
VN2_din_04_03 <= dout04_CU05;
|
||||
VN2_din_04_04 <= dout05_CU05;
|
||||
VN3_din_02_05 <= dout02_CU02;
|
||||
VN3_din_02_06 <= dout03_CU02;
|
||||
VN3_din_03_07 <= dout02_CU04;
|
||||
VN3_din_03_08 <= dout03_CU04;
|
||||
end else begin
|
||||
VN1_din_01_00 <= 8'd0;
|
||||
VN1_din_02_00 <= 8'd0;
|
||||
VN2_din_01_00 <= 8'd0;
|
||||
VN2_din_02_00 <= 8'd0;
|
||||
VN2_din_03_00 <= 8'd0;
|
||||
VN3_din_01_00 <= 8'd0;
|
||||
VN3_din_04_00 <= 8'd0;
|
||||
VN1_din_02_01 <= 8'd0;
|
||||
VN2_din_04_02 <= 8'd0;
|
||||
VN2_din_04_03 <= 8'd0;
|
||||
VN2_din_04_04 <= 8'd0;
|
||||
VN3_din_02_05 <= 8'd0;
|
||||
VN3_din_02_06 <= 8'd0;
|
||||
VN3_din_03_07 <= 8'd0;
|
||||
VN3_din_03_08 <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
DR_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR && iter_num == MAX_ITER_NUM - 1)
|
||||
// 对写全能用迭代次数进行限制，防止输出译码结果时有新的数据写入
|
||||
DR_wea <= 1'd1;
|
||||
else
|
||||
DR_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR存储的写地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
DR_addr_wr <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR)
|
||||
DR_addr_wr <= DR_addr_wr + 9'd1;
|
||||
else
|
||||
DR_addr_wr <= 9'd511;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR存储的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
DR_din_01 <= 1'd0;
|
||||
DR_din_02 <= 1'd0;
|
||||
DR_din_03 <= 1'd0;
|
||||
DR_din_04 <= 1'd0;
|
||||
DR_din_05 <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
DR_din_01 <= dout03_result_CU01;
|
||||
DR_din_02 <= dout04_result_CU02;
|
||||
DR_din_03 <= dout02_result_CU03;
|
||||
DR_din_04 <= dout04_result_CU04;
|
||||
DR_din_05 <= dout07_result_CU05;
|
||||
end else begin
|
||||
DR_din_01 <= 1'd0;
|
||||
DR_din_02 <= 1'd0;
|
||||
DR_din_03 <= 1'd0;
|
||||
DR_din_04 <= 1'd0;
|
||||
DR_din_05 <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//状态指示
|
||||
assign data_start_ck_VN = (cnt_VN == 11'd1 + DELAY_WR - 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0;
|
||||
assign data_start_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0;
|
||||
assign end_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd2 && iter_num <= MAX_ITER_NUM - 2) ? 1'd1 : 1'd0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 21:36:07 01/20/2018
|
||||
// Design Name:
|
||||
// Module Name: abs_min_4din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module abs_min_4din #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01, //din01<din02
|
||||
input [WIDTH-1:0] din02,
|
||||
input [WIDTH-1:0] din03, //din03<din04
|
||||
input [WIDTH-1:0] din04,
|
||||
output reg [WIDTH-1:0] dout_min = 8'd0,
|
||||
output reg [WIDTH-1:0] dout_sec = 8'd0
|
||||
); //输出相对输入延时1个周期
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (din02 <= din03) begin
|
||||
dout_min <= din01;
|
||||
dout_sec <= din02;
|
||||
end
|
||||
else begin
|
||||
if (din01 <= din03) begin
|
||||
dout_min <= din01;
|
||||
dout_sec <= din03;
|
||||
end
|
||||
else begin
|
||||
dout_min <= din03;
|
||||
dout_sec <= (din01 < din04) ? din01 : din04;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer: liu yongxin
|
||||
|
||||
+22
-13
@@ -21,7 +21,7 @@ module ad9361_mgc_pin_ctrl (
|
||||
input [11:0] rx_data_q,
|
||||
// this port is from zynq to ad9361
|
||||
output wire [ 3:0] ad9361_ctrl_in,
|
||||
output reg flag_mgc_done // active high level signal
|
||||
output reg flag_mgc_done = 0 // active high level signal
|
||||
|
||||
);
|
||||
|
||||
@@ -117,15 +117,24 @@ module ad9361_mgc_pin_ctrl (
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_DEC: begin
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_DONE: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
@@ -151,18 +160,18 @@ module ad9361_mgc_pin_ctrl (
|
||||
// .probe_out0(start) // output wire [0 : 0] probe_out0
|
||||
// );
|
||||
|
||||
ila_ad9361_mgc u_ila_ad9361_mgc (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(start_posedge), // input wire [0:0] probe0
|
||||
.probe1(rx_data_i), // input wire [11:0] probe1
|
||||
.probe2(u_power_measure.cs), // input wire [2:0] probe2
|
||||
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
|
||||
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
|
||||
.probe5(flag_too_high), // input wire [0:0] probe5
|
||||
.probe6(flag_too_low), // input wire [0:0] probe6
|
||||
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
|
||||
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
|
||||
);
|
||||
// ila_ad9361_mgc u_ila_ad9361_mgc (
|
||||
// .clk (clk), // input wire clk
|
||||
// .probe0(start_posedge), // input wire [0:0] probe0
|
||||
// .probe1(rx_data_i), // input wire [11:0] probe1
|
||||
// .probe2(u_power_measure.cs), // input wire [2:0] probe2
|
||||
// .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
|
||||
// .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
|
||||
// .probe5(flag_too_high), // input wire [0:0] probe5
|
||||
// .probe6(flag_too_low), // input wire [0:0] probe6
|
||||
// .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
|
||||
// .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
|
||||
// );
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns / 1ns
|
||||
module tb_recv_top ();
|
||||
|
||||
reg clk = 0;
|
||||
reg clk_2x = 0;
|
||||
reg clk_4x = 0;
|
||||
reg rst = 1;
|
||||
|
||||
always #(4) clk = ~clk;
|
||||
always #(2) clk_2x = ~clk_2x;
|
||||
always #(1) clk_4x = ~clk_4x;
|
||||
|
||||
initial begin
|
||||
#20 rst <= 0;
|
||||
end
|
||||
|
||||
reg signed [11:0] ad9361_rx_data_i;
|
||||
reg signed [11:0] ad9361_rx_data_q;
|
||||
reg [ 9:0] k1;
|
||||
reg [ 9:0] k2;
|
||||
reg [11:0] mem_i [0:637049];
|
||||
reg [11:0] mem_q [0:637049];
|
||||
|
||||
initial begin
|
||||
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_i2_new2.txt", mem_i);
|
||||
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_q2_new2.txt", mem_q);
|
||||
$display("Read mem done ");
|
||||
end
|
||||
|
||||
// reg [31:0] idx = 46500 - 8000;
|
||||
reg [31:0] idx = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
idx <= idx + 1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ad9361_rx_data_i <= 0;
|
||||
ad9361_rx_data_q <= 0;
|
||||
k1 <= 0;
|
||||
k2 <= 0;
|
||||
end
|
||||
else begin
|
||||
ad9361_rx_data_i <= $signed(k1);
|
||||
ad9361_rx_data_q <= $signed(k2);
|
||||
k1 <= mem_i[idx];
|
||||
k2 <= mem_q[idx];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
RecvTop u_RecvTop (
|
||||
.clk (clk),
|
||||
.clk_2x (clk_2x),
|
||||
.clk_4x (clk_4x),
|
||||
.rst (rst),
|
||||
.rst2 (rst),
|
||||
.dini (ad9361_rx_data_i),
|
||||
.dinq (ad9361_rx_data_q),
|
||||
.ad9361_ctrl_in (),
|
||||
.vio_tsync_inter16(1),
|
||||
.EQUenable_vio (1),
|
||||
.Zerozone_vio (8'd29),
|
||||
.vio_stopbit (7'd60),
|
||||
.flag_stop (flag_stop),
|
||||
.addr_stop (addr_stop),
|
||||
.recvNetData (recvNetData),
|
||||
.recvNetDataNd (recvNetDataNd)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
module tb_width_convert ();
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user