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base: ZoroGH/MM7020:PhyDone
Branches Tags
ZoroGH/MM7020:main ZoroGH/MM7020:speed_3125
ZoroGH/MM7020:ThirdTestRelease ZoroGH/MM7020:release_3125_v1.1 ZoroGH/MM7020:release_3125_v1 ZoroGH/MM7020:PhyTested ZoroGH/MM7020:PhyDone ZoroGH/MM7020:TxDone
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compare: ZoroGH/MM7020:main
Branches Tags
ZoroGH/MM7020:speed_3125 ZoroGH/MM7020:main
ZoroGH/MM7020:ThirdTestRelease ZoroGH/MM7020:release_3125_v1.1 ZoroGH/MM7020:release_3125_v1 ZoroGH/MM7020:PhyTested ZoroGH/MM7020:PhyDone ZoroGH/MM7020:TxDone
7 Commits
PhyDone .. main
Author SHA1 Message Date
ZoroGH 9d566f6b74 feat(top): add abnormal logic to pass 3rd test 2024-10-18 14:05:04 +08:00
ZoroGH fea952e06a merge(sys): merge tdma update 2024-10-12 11:02:35 +08:00
ZoroGH ae78b3092d feat(tdma): update tdma logic 2024-10-09 20:13:52 +08:00
ZoroGH 5e8d69a0b0 feat(top): new (de)scrambler, crc16 2024-08-13 22:07:58 +08:00
ZoroGH a4eb609aae refactor(top): set ps config param, adjust timing 2024-08-03 21:02:08 +08:00
ZoroGH 145e8c0930 fix(top): reverse iq in recv 2024-08-02 20:51:37 +08:00
ZoroGH 92583b785c feat(top): add mac layer control, half tested 2024-07-29 19:04:48 +08:00
22 changed files with 3588 additions and 915 deletions
Expand all files Collapse all files
.tags
+1792 -373
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File diff suppressed because it is too large Load Diff
coe/bram_scramble.coe
+11
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@@ -0,0 +1,11 @@
memory_initialization_radix=2;
memory_initialization_vector=
01010101111100101000010011111111
11111010011001101010001100000111
00101001010100111011101100111101
01100011110011100110001011010010
01111101101111010111010001000011
10010000010101101101011001011000
00010010111000000110010010011011
00000101111000110100000001000111
;
coe/rf_control_map.coe
+10
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@@ -0,0 +1,10 @@
memory_initialization_radix=2;
memory_initialization_vector=
1000
0100
0001
1001
0101
1101
0111
1111;
contraint/mm7020_timing.xdc
+12 -2
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@@ -1,3 +1,13 @@
set_property MAX_FANOUT 512 [get_nets *u_Receiver/mag*]
set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*]
# set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid]
set_false_path -through [get_nets u_Receiver/rst]
# set_false_path -through [get_nets u_Receiver/rst]
# set_false_path -through [get_nets u_RecvTop/SR[0]]
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rst]
set_false_path -through [get_nets phy_tx_test_flag]
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_tx_iq_reverse]
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse]
set_false_path -through [get_nets tdma_flag_is_master]
set_false_path -through [get_nets tdma_slot_len*]
set_false_path -through [get_nets tdma_tic_2_ps*]
set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
set_false_path -through [get_nets rx_rst]
hdl/CCSDS_LDPC_DEC_K1024_R12_TOPP.v
+92 -100
View File
@@ -20,126 +20,118 @@
//////////////////////////////////////////////////////////////////////////////////
module CCSDS_LDPC_DEC_K1024_R12_TOPP
#(
parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量
parameter WIDTH = 4'd8, //量化比特
parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
)
(
input clk, //工作时钟,100MHz
input Rst, //同步复位信号,高有效
input FrameSync, //帧同步标志,高脉冲
input Nd, //译码输入数据有效标志,高有效
input [WIDTH-1:0] Din, //译码输入数据,软信息
module CCSDS_LDPC_DEC_K1024_R12_TOPP #(
parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量
parameter WIDTH = 4'd8, //量化比特
parameter OUT_ONLY_INFORMATION = 1'b1 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
) (
input clk, //工作时钟,100MHz
input Rst, //同步复位信号,高有效
input FrameSync, //帧同步标志,高脉冲
input Nd, //译码输入数据有效标志,高有效
input [WIDTH-1:0] Din, //译码输入数据,软信息
output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
output Rdy, //译码输出信号有效标志,高有效
output [0:0] LDPC_Dout, //译码输出信号,MSB输出
output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
output Rdy, //译码输出信号有效标志,高有效
output [0:0] LDPC_Dout, //译码输出信号,MSB输出
output [8:0] good_frames, //译码好帧计数
output [8:0] bad_frames, //译码坏帧计数
output [8:0] total_frames //译码总帧数计数
);
output [8:0] good_frames, //译码好帧计数
output [8:0] bad_frames, //译码坏帧计数
output [8:0] total_frames //译码总帧数计数
);
wire FrameSync_A_TM;
wire Nd_A_TM;
wire FrameSync_A_TM;
wire Nd_A_TM;
wire [WIDTH-1:0] Din_A_TM;
wire FrameSync_B_TM;
wire Nd_B_TM;
wire FrameSync_B_TM;
wire Nd_B_TM;
wire [WIDTH-1:0] Din_B_TM;
wire LDPC_SyncOut_A;
wire Rdy_A;
wire [0:0] LDPC_Dout_A;
wire [8:0] good_frames_A;
wire [8:0] bad_frames_A;
wire [8:0] total_frames_A;
wire LDPC_SyncOut_A;
wire Rdy_A;
wire [ 0:0] LDPC_Dout_A;
wire [ 8:0] good_frames_A;
wire [ 8:0] bad_frames_A;
wire [ 8:0] total_frames_A;
wire LDPC_SyncOut_B;
wire Rdy_B;
wire [0:0] LDPC_Dout_B;
wire [8:0] good_frames_B;
wire [8:0] bad_frames_B;
wire [8:0] total_frames_B;
wire LDPC_SyncOut_B;
wire Rdy_B;
wire [ 0:0] LDPC_Dout_B;
wire [ 8:0] good_frames_B;
wire [ 8:0] bad_frames_B;
wire [ 8:0] total_frames_B;
LDPC_TopManage_2
#(
LDPC_TopManage_2 #(
.WIDTH(WIDTH)
)
TM (
.clk(clk),
.Rst(Rst),
.FrameSync_TM(FrameSync),
.Nd_TM(Nd),
.Din_TM(Din),
.FrameSync_A_TM(FrameSync_A_TM),
.Nd_A_TM(Nd_A_TM),
.Din_A_TM(Din_A_TM),
.FrameSync_B_TM(FrameSync_B_TM),
.Nd_B_TM(Nd_B_TM),
.Din_B_TM(Din_B_TM),
.LDPC_SyncOut_A_TM(LDPC_SyncOut_A),
.Rdy_A_TM(Rdy_A),
.LDPC_Dout_A_TM(LDPC_Dout_A),
.good_frames_A_TM(good_frames_A),
.bad_frames_A_TM(bad_frames_A),
.total_frames_A_TM(total_frames_A),
.LDPC_SyncOut_B_TM(LDPC_SyncOut_B),
.Rdy_B_TM(Rdy_B),
.LDPC_Dout_B_TM(LDPC_Dout_B),
.good_frames_B_TM(good_frames_B),
.bad_frames_B_TM(bad_frames_B),
.total_frames_B_TM(total_frames_B),
.LDPC_SyncOut_TM(LDPC_SyncOut),
.Rdy_TM(Rdy),
.LDPC_Dout_TM(LDPC_Dout),
.good_frames_TM(good_frames),
.bad_frames_TM(bad_frames),
.total_frames_TM(total_frames)
) TM (
.clk (clk),
.Rst (Rst),
.FrameSync_TM (FrameSync),
.Nd_TM (Nd),
.Din_TM (Din),
.FrameSync_A_TM (FrameSync_A_TM),
.Nd_A_TM (Nd_A_TM),
.Din_A_TM (Din_A_TM),
.FrameSync_B_TM (FrameSync_B_TM),
.Nd_B_TM (Nd_B_TM),
.Din_B_TM (Din_B_TM),
.LDPC_SyncOut_A_TM(LDPC_SyncOut_A),
.Rdy_A_TM (Rdy_A),
.LDPC_Dout_A_TM (LDPC_Dout_A),
.good_frames_A_TM (good_frames_A),
.bad_frames_A_TM (bad_frames_A),
.total_frames_A_TM(total_frames_A),
.LDPC_SyncOut_B_TM(LDPC_SyncOut_B),
.Rdy_B_TM (Rdy_B),
.LDPC_Dout_B_TM (LDPC_Dout_B),
.good_frames_B_TM (good_frames_B),
.bad_frames_B_TM (bad_frames_B),
.total_frames_B_TM(total_frames_B),
.LDPC_SyncOut_TM (LDPC_SyncOut),
.Rdy_TM (Rdy),
.LDPC_Dout_TM (LDPC_Dout),
.good_frames_TM (good_frames),
.bad_frames_TM (bad_frames),
.total_frames_TM (total_frames)
);
CCSDS_LDPC_DEC_K1024_R12
#(
.MAX_ITER_NUM(MAX_ITER_NUM),
CCSDS_LDPC_DEC_K1024_R12 #(
.MAX_ITER_NUM(MAX_ITER_NUM),
.WIDTH(WIDTH),
.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
)
inst_DEC_A (
.clk(clk),
.Rst(Rst),
.FrameSync(FrameSync_A_TM),
.Nd(Nd_A_TM),
.Din(Din_A_TM),
.LDPC_SyncOut(LDPC_SyncOut_A),
.Rdy(Rdy_A),
.LDPC_Dout(LDPC_Dout_A),
.good_frames(good_frames_A),
.bad_frames(bad_frames_A),
.total_frames(total_frames_A)
) inst_DEC_A (
.clk (clk),
.Rst (Rst),
.FrameSync (FrameSync_A_TM),
.Nd (Nd_A_TM),
.Din (Din_A_TM),
.LDPC_SyncOut(LDPC_SyncOut_A),
.Rdy (Rdy_A),
.LDPC_Dout (LDPC_Dout_A),
.good_frames (good_frames_A),
.bad_frames (bad_frames_A),
.total_frames(total_frames_A)
);
CCSDS_LDPC_DEC_K1024_R12
#(
.MAX_ITER_NUM(MAX_ITER_NUM),
CCSDS_LDPC_DEC_K1024_R12 #(
.MAX_ITER_NUM(MAX_ITER_NUM),
.WIDTH(WIDTH),
.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
)
inst_DEC_B (
.clk(clk),
.Rst(Rst),
.FrameSync(FrameSync_B_TM),
.Nd(Nd_B_TM),
.Din(Din_B_TM),
.LDPC_SyncOut(LDPC_SyncOut_B),
.Rdy(Rdy_B),
.LDPC_Dout(LDPC_Dout_B),
.good_frames(good_frames_B),
.bad_frames(bad_frames_B),
.total_frames(total_frames_B)
) inst_DEC_B (
.clk (clk),
.Rst (Rst),
.FrameSync (FrameSync_B_TM),
.Nd (Nd_B_TM),
.Din (Din_B_TM),
.LDPC_SyncOut(LDPC_SyncOut_B),
.Rdy (Rdy_B),
.LDPC_Dout (LDPC_Dout_B),
.good_frames (good_frames_B),
.bad_frames (bad_frames_B),
.total_frames(total_frames_B)
);
hdl/PAPR.v
+103 -75
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@@ -36,19 +36,32 @@ module PAPR #(
);
localparam SUM_WIDTH = 32;
localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
localparam CNT_END = 44; // 88*4 / 8
localparam PULSE_PERIOD = 32;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg [MAG_WIDTH-1:0] vec_mag_reserved;
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 7:0] cnt;
wire [MAG_WIDTH-1:0] data_avg;
reg [SUM_WIDTH-1:0] data_sum;
assign data_avg = data_sum[SUM_WIDTH-1:10];
reg mag_valid_d1;
reg [MAG_WIDTH-1:0] vec_mag_d1;
reg [MAG_WIDTH-1:0] vec_mag_d2;
reg [MAG_WIDTH-1:0] vec_mag_d3;
reg frame_sync_d1;
always @(posedge clk) begin
mag_valid_d1 <= mag_valid;
if (rst) begin
vec_mag_d1 <= 'd0;
vec_mag_d2 <= 'd0;
vec_mag_d3 <= 'd0;
vec_mag_d1 <= 0;
vec_mag_d2 <= 0;
vec_mag_d3 <= 0;
end
else if (mag_valid) begin
vec_mag_d1 <= vec_mag;
@@ -61,14 +74,7 @@ module PAPR #(
vec_mag_d3 <= vec_mag_d3;
end
end
// accumulate ==> average ==> papr
wire [MAG_WIDTH-1:0] vec_mag_1024;
reg [ 5:0] cnt;
// shift_1024 shift_1024 (
// .D (vec_mag), // input wire [21 : 0] D
// .CLK(clk), // input wire CLK
// .Q (vec_mag_1024) // output wire [21 : 0] Q
// );
shift_reg #(
.DATA_WIDTH(MAG_WIDTH),
@@ -82,10 +88,9 @@ module PAPR #(
);
reg [SUM_WIDTH-1:0] data_sum;
always @(posedge clk) begin
if (rst) begin
data_sum <= 'd0;
data_sum <= 0;
end
else begin
if (mag_valid) begin
@@ -97,71 +102,94 @@ module PAPR #(
end
end
wire [MAG_WIDTH-1:0] data_avg;
assign data_avg = data_sum[SUM_WIDTH-1:10];
// FSM
reg [2:0] cs = 0;
reg [2:0] ns = 0;
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
0: begin
if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
ns = 1;
end
end
1: begin
if (cnt == CNT_START - 1) begin
ns = 2;
end
end
2: begin
if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
ns = 0;
end
else if (cnt == CNT_END - 1) begin
ns = 3;
end
end
3: begin
// generate pulse
ns = 4;
end
4: begin
if (cnt == PULSE_PERIOD - 1) begin
ns = 0;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
frame_sync <= 1'd0;
if (cs == 0 && ns == 1) begin
vec_mag_reserved <= vec_mag_d2;
end
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
frame_sync <= 1'd1;
end
else if (cnt == 6'b111111) begin
frame_sync <= 1'd0;
end
else begin
frame_sync <= frame_sync;
else if (cs == 0) begin
vec_mag_reserved <= 0;
end
end
always @(posedge clk) begin
if (cs == 1 || cs == 2) begin
if (mag_valid) begin
cnt <= cnt + 1;
end
end
else if (cs == 4) begin
cnt <= cnt + 1;
end
else if (cs == 0) begin
cnt <= 0;
end
end
always @(posedge clk) begin
frame_sync_pulse <= (cs == 3);
if (cs == 4) begin
frame_sync <= 1;
end
else begin
frame_sync <= frame_sync;
frame_sync <= 0;
end
end
always @(posedge clk) begin
frame_sync_d1 <= frame_sync;
if (frame_sync && ~frame_sync_d1) begin
frame_sync_pulse <= 1'd1;
end
else begin
frame_sync_pulse <= 1'd0;
end
end
always @(posedge clk) begin
if (rst) begin
cnt <= 6'd0;
end
else if (frame_sync && mag_valid_d1) begin
cnt <= cnt + 6'd1;
end
else if (cnt == 6'b111111) begin
cnt <= 6'd0;
end
end
// ******** Wire & Reg ********
// ******** Assingment ********
// ******** Logic Block ********
// ******** Inst ********
// ******** Debug ********
// NOTE: comment
ila_frame_sync u_ila_frame_sync (
.clk (clk), // input wire clk
.probe0(vec_mag), // input wire [21:0] probe0
.probe1(mag_valid), // input wire [0:0] probe1
.probe2(frame_sync) // input wire [0:0] probe2
);
// ila_frame_sync u_ila_frame_sync (
// .clk (clk), // input wire clk
// .probe0(vec_mag), // input wire [21:0] probe0
// .probe1(data_avg), // input wire [21:0] probe0
// .probe2(cs), // input wire [2:0] probe2
// .probe3(cnt), // input wire [7:0] probe2
// .probe4(frame_sync), // input wire [0:0] probe2
// .probe5(vec_mag_reserved) // input wire [21:0] probe2
// );
hdl/RecvTop.v
+124 -39
View File
@@ -19,34 +19,43 @@
//
//////////////////////////////////////////////////////////////////////////////////
module RecvTop (
input clk,
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
input clk,
input clk_2x, // clk_2x
input clk_4x,
input rst,
input rst2, // TODO： delete the signal
// phy wave
input [11:0] dini,
input [11:0] dinq,
input [11:0] dini,
input [11:0] dinq,
// mgc control
output [ 3:0] ad9361_ctrl_in,
output [ 3:0] ad9361_ctrl_in,
output wire flag_mgc_done_pulse, // active high pulse signal
output wire frame_sync_pulse, // in domain clk
//vio
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
input EQUenable_vio, //为1时启用均衡
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
// stop signal
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
// mac frame header
output [63:0] recvNetData,
output recvNetDataNd
output [63:0] recvNetData,
output recvNetDataNd,
// rx data src
output wire [31:0] rx_data_src_fifo_tdata,
output wire rx_data_src_fifo_tlast,
input wire rx_data_src_fifo_tready,
output wire rx_data_src_fifo_tvalid,
// ber
output reg err_flag_pos
);
wire rst_TimeSync;
wire rst_freq;
wire DAGC_rdy;
wire framesync; //帧同步峰
wire framesync_delay; //帧同步峰，与频率补偿输出对应
wire flag_cfo_done; //帧同步峰，与频率补偿输出对应
wire framesync_tsync; //帧同步标志，与TSync输出对应
wire IntpARdy; //TSync输出nd
wire nd_SC_FDE_dout; //SC_FDE输出nd
@@ -132,13 +141,14 @@ module RecvTop (
// * MGC module
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in(ad9361_ctrl_in),
.flag_mgc_done (flag_mgc_done)
.clk (clk),
.rst (rst),
.start (mgc_start),
.rx_data_i (dini),
.rx_data_q (dinq),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse(flag_mgc_done_pulse),
.flag_mgc_done (flag_mgc_done)
);
@@ -255,17 +265,18 @@ module RecvTop (
.m_axis_data_tdata (dmf_tdata_interp4_q)
);
localparam CNT_CHU_SEQ_SYNC_MAX = 40;//! should not less than 3 due to the minimum rst of aresetn
wire [7:0] cnt_chu_seq_sync_max_vio;
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
wire [21:0] mag;
wire mag_valid;
wire frame_sync_4x;
wire frame_sync_pulse; // in domain clk
// wire frame_sync_pulse;
reg flag_frame_sync; // active high level
wire rst_frame_sync; // derive from frame sync pulse
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX));
//* calc the magnitude
MagnitudeEstimator #(
@@ -293,11 +304,11 @@ module RecvTop (
);
always @(posedge clk) begin
if (frame_sync_pulse) begin
if (frame_sync_pulse && ~flag_frame_sync) begin
cnt_chu_seq_sync <= 1;
end
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
end
else begin
@@ -305,11 +316,13 @@ module RecvTop (
end
end
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
always @(posedge clk) begin
if (rst) begin
flag_frame_sync <= 0;
end
else if (cnt_chu_seq_sync == CNT_CHU_SEQ_SYNC_MAX) begin
else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin
flag_frame_sync <= 1;
end
else begin
@@ -345,6 +358,19 @@ module RecvTop (
end
end
wire [9:0] dagc_data_in_i;
wire [9:0] dagc_data_in_q;
shift_register_64 u_shift_register_64_i (
.D (mf_data_interp4_i[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_i) // output wire [9 : 0] Q
);
shift_register_64 u_shift_register_64_q (
.D (mf_data_interp4_q[29-:10]), // input wire [9 : 0] D
.CLK(clk), // input wire CLK
.Q (dagc_data_in_q) // output wire [9 : 0] Q
);
DAGC_v2 DAGC_v2 (
.clk (clk),
@@ -353,10 +379,10 @@ module RecvTop (
.framesync_d0 (flag_frame_sync),
.vio_powertest_h (2'b00),
.vio_powertest_l (2'b00),
.matchfilterout_i(mf_data_interp4_i[29-:10]), // input,
.matchfilterout_q(mf_data_interp4_q[29-:10]), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
.matchfilterout_i(dagc_data_in_i), // input,
.matchfilterout_q(dagc_data_in_q), // input
.DAGC_out_i (DAGC_out_i), // output
.DAGC_out_q (DAGC_out_q), // output
// debug
.flag_agch (flag_agch),
.flag_agcl (flag_agcl),
@@ -379,7 +405,7 @@ module RecvTop (
.datain_q (DAGC_out_q),
.dataout_i (freqdataout_i),
.dataout_q (freqdataout_q),
.framesync_delay(framesync_delay),
.framesync_delay(flag_cfo_done),
.data_save (data_save),
.rst_freq (rst_freq)
);
@@ -395,7 +421,7 @@ module RecvTop (
.douti (IntpOuti),
.doutq (IntpOutq),
.vio_tsync_inter16(vio_tsync_inter16),
.framesync (framesync_delay), //帧同步标志
.framesync (flag_cfo_done), //帧同步标志
.framesync_tsync (framesync_tsync), //帧同步标志
//debug
.cnt_tsync (cnt_tsync),
@@ -411,9 +437,9 @@ module RecvTop (
.clk (clk),
.rst (rst_frame_sync),
// param
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
.nd (IntpARdy),
.dini (IntpOuti),
.dinq (IntpOutq),
@@ -491,6 +517,33 @@ module RecvTop (
.total_frames(total_frames)
);
extract_mac_frame u_extract_mac_frame (
.clk (clk_2x),
.rst (rst2 || rst_frame_sync),
.ldpc_dec_out_start (LDPC_SyncOut),
.ldpc_dec_out_valid (LDPC_Rdy),
.ldpc_dec_out_data (LDPC_Dout),
.m_axis_mac_frame_tvalid(rx_data_src_fifo_tvalid),
.m_axis_mac_frame_tdata (rx_data_src_fifo_tdata),
.m_axis_mac_frame_tready(rx_data_src_fifo_tready),
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
);
reg err_flag;
reg err_flag_d1;
// reg err_flag_pos;
always @(posedge clk) begin
if (rst2 || rst_frame_sync) begin
err_flag <= 0;
end
else if (total_frames == 105 && bad_frames > 0) begin
err_flag <= 1;
end
err_flag_d1 <= err_flag;
err_flag_pos <= err_flag & ~err_flag_d1;
end
@@ -533,6 +586,38 @@ module RecvTop (
.src_rst () // 1-bit input: optional; required when RST_USED = 1
);
// ***** debug *****
vio_recv_top u_vio_recv_top (
.clk (clk),
.probe_out0(cnt_chu_seq_sync_max_vio)
);
ila_recv_top u_ila_recv_top (
.clk (clk),
.probe0 (dini), // width: 12
.probe1 (dinq), // width: 12
.probe2 (dagc_data_in_i), // width: 12
.probe3 (dagc_data_in_q), // width: 12
.probe4 (flag_mgc_done), // width: 1
.probe5 (flag_frame_sync), // width: 1
.probe6 (flag_cfo_done), // width: 1
.probe7 (freqdataout_i), // width: 10
.probe8 (freqdataout_q), // width: 10
.probe9 (IntpARdy), // width: 1
.probe10(IntpOuti), // width: 10
.probe11(IntpOutq), // width: 10
.probe12(nd_SC_FDE_dout), // width: 1
.probe13(SC_FDE_douti), // width: 10
.probe14(SC_FDE_doutq), // width: 10
.probe15(phase_adjust_rdy), // width: 1
.probe16(phase_adjust_douti), // width: 10
.probe17(phase_adjust_doutq), // width: 10
.probe18(LDPC_Rdy), // width: 1
.probe19(LDPC_Dout), // width: 1
.probe20(good_frames), // width: 9
.probe21(bad_frames) // width: 9
);
endmodule
hdl/ad9361_mgc_pin_ctrl.v
+9 -7
View File
@@ -21,7 +21,8 @@ module ad9361_mgc_pin_ctrl (
input [11:0] rx_data_q,
// this port is from zynq to ad9361
output wire [ 3:0] ad9361_ctrl_in,
output reg flag_mgc_done = 0 // active high level signal
output wire flag_mgc_done_pulse, // active high pulse signal
output reg flag_mgc_done = 0 // active high level signal
);
@@ -54,14 +55,15 @@ module ad9361_mgc_pin_ctrl (
reg [2:0] ns;
// ******** Assingment ********
assign ad9361_ctrl_in[0] = inc_pulse;
assign ad9361_ctrl_in[1] = dec_pulse;
assign ad9361_ctrl_in[0] = inc_pulse;
assign ad9361_ctrl_in[1] = dec_pulse;
assign flag_adjust = flag_too_high | flag_too_low;
assign inc_pulse = (cs == S_INC);
assign dec_pulse = (cs == S_DEC);
assign flag_adjust = flag_too_high | flag_too_low;
assign inc_pulse = (cs == S_INC);
assign dec_pulse = (cs == S_DEC);
assign start_posedge = start & ~start_d1;
assign start_posedge = start & ~start_d1;
assign flag_mgc_done_pulse = power_measure_done_pulse;
// ******** Logic Block ********
hdl/enc_control.v
+14
View File
@@ -338,4 +338,18 @@ module enc_control #(
// ******** Debug ********
// ila_enc_control u_ila_enc_control (
// .clk (clk),
// .probe0(s_axis_fifo_tvalid), // width: 1
// .probe1(s_axis_fifo_tready), // width: 1
// .probe2(s_axis_fifo_tdata), // width: 32
// .probe3(data_src_count), // width: 32
// .probe4(cs), // width: 4
// .probe5(wc_data_in_ready), // width: 1
// .probe6(wc_data_in_valid), // width: 1
// .probe7(wc_data_out_valid), // width: 1
// .probe8(data_add_prefix_in_ready), // width: 1
// .probe9(data_add_prefix_out_valid) // width: 1
// );
endmodule
hdl/extract_mac_frame.v
+82
View File
@@ -0,0 +1,82 @@
module extract_mac_frame (
input clk,
input rst,
// ldpc out
input ldpc_dec_out_start,
input ldpc_dec_out_valid,
input ldpc_dec_out_data,
// axis
output wire m_axis_mac_frame_tvalid,
output wire [31:0] m_axis_mac_frame_tdata,
input m_axis_mac_frame_tready,
output reg m_axis_mac_frame_tlast
);
// NOTE: module 1bit --> 32bit
// transfer 1bit serial to 32bit and sent to axis fifo
//
localparam MAC_FRAME_LEN_BIT = 107520;
localparam MAC_FRAME_LEN_BYTE = 13440;
localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;
// ******** Wire & Reg ********
reg [15:0] cnt_axis_out;
wire flag_handshake;
// serial input
wire ser;
wire ser_valid;
wire [31:0] par;
wire par_valid;
// ******** Assingment ********
assign ser = ldpc_dec_out_data;
assign ser_valid = ldpc_dec_out_valid;
assign m_axis_mac_frame_tvalid = par_valid;
assign m_axis_mac_frame_tdata = par;
assign flag_handshake = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready;
// ******** Logic Block ********
always @(posedge clk) begin
if (rst) begin
cnt_axis_out <= 0;
end
else if (flag_handshake) begin
cnt_axis_out <= cnt_axis_out + 1;
end
end
always @(*) begin
if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin
m_axis_mac_frame_tlast = 1;
end
else begin
m_axis_mac_frame_tlast = 0;
end
end
// ******** Inst ********
// serial 1bit --> 32bit
ser2par u_ser2par (
.clk (clk),
.rst (rst),
.ser (ser),
.ser_valid(ser_valid),
.par (par),
.par_valid(par_valid)
);
// ******** Debug ********
endmodule
hdl/net_city.v
+417
View File
@@ -0,0 +1,417 @@
`timescale 1ns / 1ps
module net_city (
// basic
input clk,
input rst_initial,
input rst_manual, //manual
// tx signal
output reg tx_start = 1'b0, // pulse
output reg [63:0] trans_net_data = 64'd0,
output reg flag_video_send = 1'b0,
output reg [07:0] recv_id = 8'd0,
// rx signal
input frame_sync,
// input recv_net_data_nd,
// input [63:0] recv_net_data,
// net parameter
input [31:0] frame_sync_time,
input [07:0] id_num,
input [07:0] max_slot_num,
input [07:0] video_id01,
input [07:0] video_id02,
input [07:0] video_id03,
// net state
output reg is_net = 1'b0,
output reg flag_to_uc = 1'b0,
// intr 2 ps
output wire intr_ps,
output reg rx_rst,
input wire tx_done
);
//----------parameter----------
localparam SLOT_TIME = 750000; // 15ms
//----------rst----------
wire rst;
assign rst = rst_initial || rst_manual;
//----------counter_1s----------
reg [31:0] cnt_1s = 32'd0;
always @(posedge clk) begin
if (rst) begin
cnt_1s <= 32'd0;
end
else begin
if (cnt_1s == 32'd49999999) begin
cnt_1s <= 32'd0;
end
else begin
cnt_1s <= cnt_1s + 32'd1;
end
end
end
//----------flag_tx----------
//----------state_net----------
reg [07:0] state_net = 8'd0;
reg [31:0] cnt_trans_slot = 32'd0;
reg [31:0] cnt_inter_slot = 32'd0;
reg [07:0] cur_slot = 8'd0;
reg [07:0] cnt_video_slot = 8'd0;
reg [31:0] cnt_other = 32'd0;
reg [07:0] connect_node = 8'd0;
reg [63:0] trans_net_data_reg = 64'd0;
reg [07:0] recv_connect_node = 8'd0;
reg [07:0] recv_video_id01 = 8'd0;
reg [07:0] recv_video_id02 = 8'd0;
reg [07:0] recv_video_id03 = 8'd0;
// if u dont understand this code blew, plz contact NanzZ 😊
assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2)));
always @(posedge clk) begin
if (rst) begin
rx_rst <= 0;
end
else if (tx_start) begin
rx_rst <= 1;
end
else if (tx_done) begin
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
state_net <= 8'd0;
cnt_trans_slot <= 32'd0;
cnt_inter_slot <= 32'd0;
cnt_other <= 32'd0;
recv_id <= 8'd0;
recv_connect_node <= 8'd0;
recv_video_id01 <= 8'd0;
recv_video_id02 <= 8'd0;
recv_video_id03 <= 8'd0;
tx_start <= 1'b0;
trans_net_data <= 64'd0;
is_net <= 1'b0;
flag_video_send <= 1'b0;
end
else begin
case (state_net)
8'd0: begin
state_net <= 8'd1;
cnt_trans_slot <= 32'd0;
cnt_inter_slot <= 32'd0;
cnt_other <= 32'd0;
recv_id <= recv_id;
recv_connect_node <= 8'd0;
recv_video_id01 <= recv_video_id01;
recv_video_id02 <= recv_video_id02;
recv_video_id03 <= recv_video_id03;
tx_start <= 1'b0;
trans_net_data <= 64'd0;
is_net <= 1'b0;
flag_video_send <= 1'b0;
end
8'd1: begin
state_net <= 8'd2;
end
8'd2: begin
if (frame_sync) begin
state_net <= 8'd50;
cnt_other <= 32'd0;
cnt_trans_slot <= frame_sync_time;
cnt_inter_slot <= cnt_trans_slot + 32'd1;
end
else if (cnt_other == 32'd49999999) begin
cnt_other <= 32'd0;
state_net <= 8'd100;
is_net <= 1'b1;
end
else begin
cnt_other <= cnt_other + 32'd1;
end
end
8'd100: begin // _tx
state_net <= 8'd101;
tx_start <= 1'b1;
trans_net_data <= trans_net_data_reg;
cnt_trans_slot <= 32'd0;
cnt_inter_slot <= 32'd0;
end
8'd101: begin
state_net <= 8'd200;
tx_start <= 1'b0;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
end
8'd200: begin // wait
if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin
state_net <= 8'd100;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= 32'd0;
end
else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin
state_net <= 8'd100;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
cnt_inter_slot <= 32'd0;
end
else if (frame_sync) begin
state_net <= 8'd50;
cnt_trans_slot <= frame_sync_time;
cnt_inter_slot <= cnt_trans_slot + 32'd1;
end
else begin
if (cnt_trans_slot == SLOT_TIME - 1) begin
cnt_trans_slot <= 32'd0;
end
else begin
cnt_trans_slot <= cnt_trans_slot + 32'd1;
end
cnt_inter_slot <= 32'd0;
end
case (id_num)
recv_video_id01: begin
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin
flag_video_send <= 1'b1;
end
else begin
flag_video_send <= 1'b0;
end
end
recv_video_id02: begin
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin
flag_video_send <= 1'b1;
end
else begin
flag_video_send <= 1'b0;
end
end
recv_video_id03: begin
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin
flag_video_send <= 1'b1;
end
else begin
flag_video_send <= 1'b0;
end
end
default: begin
flag_video_send <= 1'b0;
end
endcase
end
8'd50: begin
// if (recv_net_data_nd) begin
// if (recv_net_data[23:00] == 24'h7e5a33) begin
state_net <= 8'd51;
is_net <= 1'b1;
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// recv_id <= recv_net_data[63:56];
// recv_video_id01 <= recv_net_data[55:48];
// recv_video_id02 <= recv_net_data[47:40];
// recv_video_id03 <= recv_net_data[39:32];
// recv_connect_node <= recv_net_data[31:24];
// end
// else begin
// state_net <= 8'd200;
// is_net <= 1'b0;
// cnt_trans_slot <= cnt_inter_slot + 32'd1;
// end
// end
// else begin
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
// end
end
8'd51: begin
state_net <= 8'd200;
cnt_trans_slot <= cnt_trans_slot + 32'd1;
end
default: begin
state_net <= 8'd0;
cnt_trans_slot <= 32'd0;
cnt_inter_slot <= 32'd0;
cnt_other <= 32'd0;
recv_id <= recv_id;
recv_connect_node <= 8'd0;
recv_video_id01 <= recv_video_id01;
recv_video_id02 <= recv_video_id02;
recv_video_id03 <= recv_video_id03;
tx_start <= 1'b0;
trans_net_data <= 64'd0;
is_net <= 1'b0;
flag_video_send <= 1'b0;
end
endcase
end
end
//----------connect_node----------
// always @(posedge clk) begin
// if (rst) begin
// connect_node <= 8'd0;
// end else begin
// if (state_net == 8'd51) begin
// case (recv_id)
// 8'd1: begin
// connect_node[07:06] <= 2'b11;
// end
// 8'd2: begin
// connect_node[05:04] <= 2'b11;
// end
// 8'd3: begin
// connect_node[03:02] <= 2'b11;
// end
// 8'd4: begin
// connect_node[01:00] <= 2'b11;
// end
// default: begin
// connect_node <= 8'd0;
// end
// endcase
// end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin
// connect_node <= 8'd0;
// end else begin
// connect_node <= connect_node;
// end
// end
// end
//----------trans_net_data_reg----------
reg [07:0] trans_video_id01;
reg [07:0] trans_video_id02;
reg [07:0] trans_video_id03;
always @(posedge clk) begin
if (rst) begin
trans_video_id01 <= 8'd0;
trans_video_id02 <= 8'd0;
trans_video_id03 <= 8'd0;
end
else begin
if (id_num == 8'd1) begin //主节点
trans_video_id01 <= video_id01;
trans_video_id02 <= video_id02;
trans_video_id03 <= video_id03;
end
else if (recv_id == 8'd1) begin //从节点只听从主节点命令
trans_video_id01 <= recv_video_id01;
trans_video_id02 <= recv_video_id02;
trans_video_id03 <= recv_video_id03;
end
else begin
trans_video_id01 <= trans_video_id01;
trans_video_id02 <= trans_video_id02;
trans_video_id03 <= trans_video_id03;
end
end
end
always @(posedge clk) begin
if (rst) begin
trans_net_data_reg <= 64'd0;
end
else begin
if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin
trans_net_data_reg[63:56] <= id_num;
trans_net_data_reg[55:48] <= trans_video_id01;
trans_net_data_reg[47:40] <= trans_video_id02;
trans_net_data_reg[39:32] <= trans_video_id03;
trans_net_data_reg[31:24] <= connect_node;
trans_net_data_reg[23:00] <= 24'h7e5a33;
end
else begin
trans_net_data_reg <= trans_net_data_reg;
end
end
end
//----------cur_slot----------
always @(posedge clk) begin
if (rst) begin
cur_slot <= 8'd0;
end
else begin
if (state_net == 8'd51) begin
if (recv_id <= max_slot_num) begin
cur_slot <= recv_id - 8'd1;
end
else begin
cur_slot <= cur_slot;
end
end
else if (cnt_trans_slot == SLOT_TIME - 1) begin
if (cur_slot == max_slot_num - 8'd1) begin
cur_slot <= 8'd0;
end
else begin
cur_slot <= cur_slot + 8'd1;
end
end
else begin
cur_slot <= cur_slot;
end
end
end
//----------cnt_video_slot----------
always @(posedge clk) begin
if (rst) begin
cnt_video_slot <= 8'd0;
end
else begin
if (cnt_trans_slot == SLOT_TIME - 1) begin
if (cnt_video_slot == 8'd2) begin
cnt_video_slot <= 8'd0;
end
else begin
cnt_video_slot <= cnt_video_slot + 8'd1;
end
end
else begin
cnt_video_slot <= cnt_video_slot;
end
end
end
always @(posedge clk) begin
if (rst) begin
flag_to_uc <= 1'b0;
end
else begin
if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin
flag_to_uc <= 1'b1;
end
else begin
flag_to_uc <= 1'b0;
end
end
end
ila_MAC ila_MAC (
.clk (clk),
.probe0 (tx_start),
.probe1 (connect_node),
.probe2 (cnt_trans_slot),
.probe3 (recv_net_data),
.probe4 (state_net),
.probe5 (recv_id),
.probe6 (cur_slot),
.probe7 (id_num),
.probe8 (frame_sync),
.probe9 (max_slot_num),
.probe10(recv_net_data_nd),
.probe11(trans_net_data)
);
endmodule
hdl/phy_control.v
+50 -6
View File
@@ -63,8 +63,20 @@ module phy_control #(
// resetn (should synchronised with "clk")
input rstn, // can be floating if ASYNC_CLK == 0
output wire phy_rst,
output wire phy_tx_test_flag
// control sigal
output wire phy_rst,
output wire phy_tx_test_flag,
output wire phy_tx_iq_reverse,
output wire phy_rx_iq_reverse,
// tdma parameters
output wire tdma_flag_is_master,
output wire [31:0] tdma_slot_len,
output wire [31:0] tdma_tic_2_ps,
output wire [31:0] tdma_id_cfg,
output wire tdma_recv_cur_slot_id_valid,
output wire [ 7:0] tdma_recv_cur_slot_id,
output wire [31:0] tdma_frame_sync_tic
//--- ADD YOUR OWN PORTS END
);
@@ -329,10 +341,20 @@ module phy_control #(
localparam integer PHY_CR = 'h00000000 >> 2; // RW
localparam integer PHY_SR = 'h00000004 >> 2; // RW
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
// Register definitions
reg [31:0] phy_cr_reg = 32'h0;
reg [31:0] phy_sr_reg = 32'h0;
reg [31:0] tdma_slot_len_reg = 32'h0;
reg [31:0] tdma_tic_2_ps_reg = 32'h0;
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
reg [31:0] tdma_recv_id_reg = 32'h0;
reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
// Register Reading
always @(posedge local_clk) begin
@@ -355,21 +377,43 @@ module phy_control #(
case (up_waddr_s)
PHY_CR: phy_cr_reg <= up_wdata_s;
PHY_SR: phy_sr_reg <= up_wdata_s;
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
endcase
end
else begin
// self logic
if (tdma_recv_id_reg[8] == 1) begin
tdma_recv_id_reg[8] <= 0;
end
end
end
end
// control reg definition
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_rst = ~phy_cr_reg[0];
assign phy_tx_test_flag = phy_cr_reg[1];
assign phy_tx_iq_reverse = phy_cr_reg[2];
assign phy_rx_iq_reverse = phy_cr_reg[3];
assign tdma_flag_is_master = phy_cr_reg[4];
// tdma
assign tdma_slot_len = tdma_slot_len_reg;
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
assign tdma_id_cfg = tdma_id_cfg_reg;
// received mac frame
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
// frame sync tic
assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg;
vio_phy_param u_vio_phy_param (
.clk (local_clk),
.probe_in0(phy_cr_reg)
);
//--- ADD YOUR OWN LOGIC END
hdl/power_measure.v
+1 -1
View File
@@ -30,7 +30,7 @@ module power_measure (
);
localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
localparam CNT_MEASURING_MAX = 512; // * 观察64个周期
localparam CNT_MEASURING_MAX = 256; // * 观察64个周期
localparam CNT_ADJUST_TIMES_MAX = 25;
localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
// ******** Wire & Reg ********
hdl/scrambler.v
+161
View File
@@ -0,0 +1,161 @@
// * Engineer:
// * *************************************************** *
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
// * *************************************************** *
// * Update Date:
// * NOTE :
module scrambler #(
parameter ILA_ON = 0
) (
input clk,
input rst_n,
// s_axis_stream
input [31:0] s_axis_tdata,
input s_axis_tvalid,
output reg s_axis_tready,
input s_axis_tlast,
input [31:0] s_axis_rd_data_count,
// m_axis_stream
output reg [31:0] m_axis_tdata,
output reg m_axis_tvalid,
input m_axis_tready,
output reg m_axis_tlast
);
// ******** Wire & Reg ********
wire rst;
reg [ 2:0] addr_scramble = 0;
reg [ 2:0] addr_scramble_d1 = 0;
reg [ 2:0] addr_scramble_d2 = 0;
wire [31:0] data_scramble_mask;
reg [ 3:0] cnt_in;
reg [31:0] s_axis_tdata_d1;
reg [31:0] s_axis_tdata_d2;
reg s_axis_tready_d1;
reg s_axis_tlast_d1;
// fsm
reg [ 1:0] cs = 0;
reg [ 1:0] ns = 0;
localparam S_IDLE = 0;
localparam S_WORKING = 1;
// ******** Assingment ********
assign rst = ~rst_n;
// ******** Logic Block ********
always @(posedge clk) begin
cs <= ns;
end
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin
ns = S_WORKING;
end
end
S_WORKING: begin
if (addr_scramble_d2 == 3'h7) begin
ns = S_IDLE;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
addr_scramble <= 0;
end
else begin
addr_scramble <= addr_scramble + 1;
end
addr_scramble_d1 <= addr_scramble;
addr_scramble_d2 <= addr_scramble_d1;
end
always @(posedge clk) begin
if (cs == S_WORKING) begin
m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
end
else begin
m_axis_tdata <= 0;
end
end
always @(posedge clk) begin
if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
s_axis_tready <= 1;
end
else begin
s_axis_tready <= 0;
end
end
always @(posedge clk) begin
s_axis_tdata_d1 <= s_axis_tdata;
s_axis_tready_d1 <= s_axis_tready;
m_axis_tvalid <= s_axis_tready_d1;
s_axis_tlast_d1 <= s_axis_tlast;
m_axis_tlast <= s_axis_tlast_d1;
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
cnt_in <= 0;
end
else if (cs == S_WORKING && cnt_in < 4'd8) begin
cnt_in <= cnt_in + 1;
end
end
// ******** Inst ********
bram_scramble u_bram_scramble (
.clka (clk), // input wire clka
.addra(addr_scramble), // input wire [2 : 0] addra
.douta(data_scramble_mask) // output wire [31 : 0] douta
);
// ******** Debug ********
generate
if (ILA_ON)
ila_scrambler u_ila_scrambler (
.clk (clk), // input wire clk
.probe0(s_axis_tvalid), // input wire [0:0] probe0
.probe1(s_axis_tready), // input wire [0:0] probe1
.probe2(s_axis_tdata), // input wire [31:0] probe2
.probe3(s_axis_tlast), // input wire [0:0] probe3
.probe4(m_axis_tvalid), // input wire [0:0] probe4
.probe5(m_axis_tready), // input wire [0:0] probe5
.probe6(m_axis_tdata), // input wire [31:0] probe6
.probe7(m_axis_tlast), // input wire [0:0] probe7
.probe8(data_scramble_mask) // input wire [31:0] probe8
);
endgenerate
endmodule
hdl/ser2par.v
+61
View File
@@ -0,0 +1,61 @@
module ser2par #(
parameter PAR_WIDTH = 32
) (
input clk,
input rst,
input wire ser,
input wire ser_valid,
output reg [PAR_WIDTH -1:0] par,
output reg par_valid
);
// ******** Wire & Reg ********
reg [$clog2(PAR_WIDTH):0] cnt_idx;
// ******** Assingment ********
// ******** Logic Block ********
always @(posedge clk) begin
if (rst) begin
cnt_idx <= 0;
end
else if (ser_valid) begin
if (cnt_idx == PAR_WIDTH - 1) begin // force it return to 0
cnt_idx <= 0;
end
else begin
cnt_idx <= cnt_idx + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
par <= 0;
end
else if (ser_valid) begin
par[cnt_idx] <= ser;
end
end
always @(posedge clk) begin
if (cnt_idx == PAR_WIDTH - 1) begin
par_valid <= 1;
end
else begin
par_valid <= 0;
end
end
// ******** Inst ********
// ******** Debug ********
endmodule
hdl/system_top.v
+243 -168
View File
@@ -89,6 +89,12 @@ module system_top (
wire tx_data_src_tvalid;
// tx signal
wire tx_test_flag;
wire flag_mgc_done_pulse;
// rx bus
wire [31:0] rx_data_src_fifo_tdata;
wire rx_data_src_fifo_tlast;
wire rx_data_src_fifo_tready;
wire rx_data_src_fifo_tvalid;
// baseband signal
wire [11:0] ad9361_rx_data_i;
@@ -98,31 +104,113 @@ module system_top (
wire [11:0] ad9361_tx_data_i;
wire [11:0] ad9361_tx_data_q;
wire [ 2:0] speed_mode;
// mux
wire bb_tx_iq_reverse;
wire bb_rx_iq_reverse;
wire [11:0] bb_tx_i;
wire [11:0] bb_tx_q;
wire [11:0] bb_rx_i;
wire [11:0] bb_rx_q;
// phy control signal
wire phy_rst_vio;
wire phy_rst_ps;
wire phy_rst;
wire phy_tx_test_flag_vio;
wire phy_tx_test_flag;
wire phy_tx_iq_reverse;
wire phy_rx_iq_reverse;
wire tdma_flag_is_master;
wire [31:0] tdma_slot_len;
wire [31:0] tdma_tic_2_ps;
wire [31:0] tdma_id_cfg;
wire tdma_recv_cur_slot_id_valid;
wire [ 7:0] tdma_recv_cur_slot_id;
wire [31:0] tdma_frame_sync_tic;
// tx signal
wire frame_sync_pulse;
wire rx_rst;
wire tx_done;
wire intr_2ps_vio;
reg intr_2ps_vio_d1;
wire intr_2ps_vio_pos;
wire tx_start_vio;
reg tx_start_vio_d1;
wire tx_start_vio_pos;
// rx
wire rx_err_flag_pos;
wire rf_io3_d1_12db;
wire rf_io4_d2_6db;
wire rf_io0_d3_18db;
wire rf_io1_d4_12db;
wire rf_io2_trx; // 1 for tx on, 0 for rx
// vio
wire rst_manual;
wire rx_rst_vio;
wire [ 7:0] node_id;
wire intr_2ps;
wire [ 7:0] max_slot_num;
reg [15:0] cnt_pulse_wider_tx_start = 0;
reg [15:0] cnt_pulse_wider_frame_sync = 0;
// ******** Assingment ********
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
assign ad9361_tx_clk = clk_1x;
assign rst_sys = ~poweron_locked;
// ad9361 control
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i;
assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
// gpio rf control
assign rf_gpio[0] = rf_io0_d3_18db;
assign rf_gpio[1] = rf_io1_d4_12db;
// assign rf_gpio[2] = rf_io2_trx;
// assign rf_gpio[3] = rf_io3_d1_12db;
assign rf_gpio[4] = rf_io4_d2_6db;
assign rf_gpio[5] = 0;
// temporary for test gpio
assign rf_gpio[2] = (cnt_pulse_wider_tx_start != 0);
assign rf_gpio[3] = (cnt_pulse_wider_frame_sync != 0);
// ******** Logic Block ********
always @(posedge clk_1x) begin
if (tx_start) begin
cnt_pulse_wider_tx_start <= 1;
end
else if (cnt_pulse_wider_tx_start > 0) begin
cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start + 1;
end
else begin
cnt_pulse_wider_tx_start <= cnt_pulse_wider_tx_start;
end
end
always @(posedge clk_2x) begin
if (rx_data_src_fifo_tlast) begin
cnt_pulse_wider_frame_sync <= 1;
end
else if (cnt_pulse_wider_frame_sync > 0) begin
cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync + 1;
end
else begin
cnt_pulse_wider_frame_sync <= cnt_pulse_wider_frame_sync;
end
end
// ******** Inst ********
clk_wiz_poweron u_clk_wiz_poweron (
@@ -147,128 +235,152 @@ module system_top (
);
MM7020_BD_wrapper u_MM7020_BD_wrapper (
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
.ad9361_spi_clk (ad9361_spi_clk),
.ad9361_spi_csn (ad9361_spi_csn),
.ad9361_spi_miso (ad9361_spi_miso),
.ad9361_spi_mosi (ad9361_spi_mosi),
.clk_ps (clk_poweron),
.rst_ps (rst_sys),
// ddr
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
// fixed io
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
// gpio ps
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
// intr pl to ps
.pl2ps_intr2 (intr_2ps),
.pl2ps_intr3 (pl2ps_intr3),
.pl_tx_intr (intr_2ps),
.pl_rx_intr (rx_data_src_fifo_tlast),
.pl_intr0 (rx_err_flag_pos),
// tx fifo
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready(tx_data_src_tready),
.tx_data_src_tvalid(tx_data_src_tvalid),
//phy control signal
.phy_rst (phy_rst_ps),
.phy_tx_test_flag (phy_tx_test_flag),
.tx_data_src_count (tx_data_src_count),
.tx_data_src_tdata (tx_data_src_tdata),
.tx_data_src_tready (tx_data_src_tready),
.tx_data_src_tvalid (tx_data_src_tvalid),
// rx fifo
.clk_rx_data_src_fifo (clk_2x),
.rst_rx_data_src_fifo (rx_rst),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
// phy clock and rst to ps
.clk_phy (clk_1x),
.rst_phy_n (~rst_sys),
// phy control signal , under clk_1x domain
.phy_rst (phy_rst),
.phy_tx_test_flag (phy_tx_test_flag),
.phy_tx_iq_reverse (phy_tx_iq_reverse),
.phy_rx_iq_reverse (phy_rx_iq_reverse),
.tdma_flag_is_master (tdma_flag_is_master),
.tdma_slot_len (tdma_slot_len),
.tdma_tic_2_ps (tdma_tic_2_ps),
.tdma_id_cfg (tdma_id_cfg),
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
.tdma_frame_sync_tic (tdma_frame_sync_tic),
// uart
.uart_rx (uart_rx),
.uart_tx (uart_tx)
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
tdma u_tdma (
.clk (clk_1x),
.rst (rst_sys),
.flag_frame_sync (frame_sync_pulse),
.tdma_slot_len (tdma_slot_len[23:0]),
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
.tdma_slot_num (tdma_id_cfg[15:8]),
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
.local_id (tdma_id_cfg[7:0]),
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
.intr_2ps (intr_2ps),
.tx_start (tx_start),
.rx_rst (rx_rst)
);
// ---- PHY layer logic start
// enc_control u_enc_control (
// .clk (clk_poweron),
// .rst (rst_sys | phy_rst_ps),
// .s_axis_fifo_tvalid (tx_data_src_tvalid),
// .s_axis_fifo_tready (tx_data_src_tready),
// .s_axis_fifo_tdata (tx_data_src_tdata),
// .data_src_count (tx_data_src_count),
// .fifo_enc_out_rd_clk (clk_1x),
// .fifo_enc_out_rd_en (enc_fifo_rd_en),
// .fifo_enc_out_dout_map(enc_fifo_dout_map),
// .fifo_enc_out_empty (enc_fifo_empty)
// );
// tdma #(
// .SLOT_LEN (1250000), // 50MHz--> 25ms
// .TIC_TO_PS_LEN (1200000),
// .TIC_FRAME_SYNC(42272)
// ) u_tdma (
// .clk (clk_1x),
// .rst (rst_sys),
// .flag_is_master (1'b0),
// .flag_frame_sync(frame_sync_pulse),
// .intr_2ps (intr_2ps),
// .tx_start (tx_start)
// );
// Transmitter u_Transmitter (
// .clk (clk_1x),
// .rst (rst_sys | phy_rst | phy_rst_vio),
// .speed_mode (speed_mode),
// .send_data_ready (send_data_ready),
// .send_start (send_start),
// .send_over (send_over),
// .clk_data_src (clk_data_src),
// .tx_data_src_tdata (enc_fifo_dout_map),
// .tx_data_src_tready(enc_fifo_rd_en),
// .tx_data_src_tvalid(~enc_fifo_empty),
// .hopping_freq (),
// .ad9361_tx_data_i (ad9361_tx_data_i),
// .ad9361_tx_data_q (ad9361_tx_data_q),
// .test (tx_test_flag | phy_tx_test_flag_vio),
// .hop_wait (100)
// );
// Receiver u_Receiver (
// .clk (clk_1x),
// .clk_2x (clk_2x),
// .clk_4x (clk_4x),
// .rst (rst_sys | phy_rst | phy_rst_vio),
// .speed_mode (speed_mode),
// .ad9361_rx_data_i(ad9361_rx_data_i),
// .ad9361_rx_data_q(ad9361_rx_data_q),
// .frame_sync_pulse(frame_sync_pulse)
// );
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
.clk (clk_1x),
.rst (rst_sys | phy_rst),
.rx_data_i (ad9361_rx_data_i),
.rx_data_q (ad9361_rx_data_q),
.ad9361_ctrl_in(ad9361_ctrl_in)
enc_control u_enc_control (
.clk (clk_poweron),
.rst (rst_sys | phy_rst),
.s_axis_fifo_tvalid (tx_data_src_tvalid),
.s_axis_fifo_tready (tx_data_src_tready),
.s_axis_fifo_tdata (tx_data_src_tdata),
.data_src_count (tx_data_src_count),
.fifo_enc_out_rd_clk (clk_1x),
.fifo_enc_out_rd_en (enc_fifo_rd_en),
.fifo_enc_out_dout_map(enc_fifo_dout_map),
.fifo_enc_out_empty (enc_fifo_empty)
);
Transmitter u_Transmitter (
.clk (clk_1x),
.rst (rst_sys | phy_rst),
.speed_mode (2),
.send_data_ready (send_data_ready),
.send_start (tx_start),
.send_over (tx_done),
.clk_data_src (clk_data_src),
.tx_data_src_tdata (enc_fifo_dout_map),
.tx_data_src_tready(enc_fifo_rd_en),
.tx_data_src_tvalid(~enc_fifo_empty),
.hopping_freq (),
.ad9361_tx_data_i (bb_tx_i),
.ad9361_tx_data_q (bb_tx_q),
.test (phy_tx_test_flag),
.hop_wait (100)
);
RecvTop u_RecvTop (
.clk (clk_1x),
.clk_2x (clk_2x),
.clk_4x (clk_4x),
.rst (rst_sys | rx_rst | phy_rst),
.rst2 (rst_sys | phy_rst),
.dini (bb_rx_i),
.dinq (bb_rx_q),
.ad9361_ctrl_in (ad9361_ctrl_in),
.flag_mgc_done_pulse (flag_mgc_done_pulse),
.frame_sync_pulse (frame_sync_pulse),
.vio_tsync_inter16 (1),
.EQUenable_vio (1),
.Zerozone_vio (8'd29),
.vio_stopbit (7'd60),
.flag_stop (flag_stop),
.addr_stop (addr_stop),
.recvNetData (recvNetData),
.recvNetDataNd (recvNetDataNd),
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
.err_flag_pos (rx_err_flag_pos)
);
// ---- PHY layer logic end
@@ -293,66 +405,29 @@ module system_top (
// ******** CDC ********
xpm_cdc_single #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
) xpm_cdc_single_tx_test_flag_ps_inst (
.dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
xpm_cdc_sync_rst #(
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
.INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
.SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) xpm_cdc_sync_rst_phy_rst_inst (
.dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered.
.dest_clk(clk_1x), // 1-bit input: Destination clock.
.src_rst (phy_rst_ps) // 1-bit input: Source reset signal.
);
// ******** Debug ********
ila_ad9361_rx u_ila_ad9361_rx (
.clk (ad9361_rx_clk),
.probe0(ad9361_rx_data_i),
.probe1(ad9361_rx_data_q),
.probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
);
ila_ad9361_tx u_ila_ad9361_tx (
.clk (ad9361_tx_clk), // input wire clk
.probe0(ad9361_tx_data_i), // input wire [11:0] probe0
.probe1(ad9361_tx_data_q) // input wire [11:0] probe1
);
vio_phy_control u_vio_phy_control (
.clk (clk_1x), // input wire clk
.probe_out0(phy_rst_vio), // output wire [0 : 0] probe_out0
.probe_out1(phy_tx_test_flag_vio), // output wire [0 : 0] probe_out1
.probe_out2(send_start) // output wire [0 : 0] probe_out2
);
vio_gpio u_vio_gpio (
.clk (clk_poweron),
.probe_out0(rf_gpio),
.probe_out1(led_red),
.probe_out2(led_yellow),
.probe_out3(led_blue)
);
vio_tx_speed_mode u_vio_tx_speed_mode (
.clk (clk_1x),
.probe_out0(speed_mode)
);
// ila_ad9361_rx u_ila_ad9361_rx (
// .clk (ad9361_rx_clk),
// .probe0(ad9361_rx_data_i),
// .probe1(ad9361_rx_data_q),
// .probe2(u_RecvTop.flag_mgc_done)
// );
// ila_ad9361_tx u_ila_ad9361_tx (
// .clk (ad9361_tx_clk), // input wire clk
// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
// );
// vio_rf u_vio_rf (
// .clk (clk_poweron),
// .probe_out0(rf_io2_trx),
// .probe_out1(rf_io3_d1_12db),
// .probe_out2(rf_io4_d2_6db),
// .probe_out3(rf_io0_d3_18db),
// .probe_out4(rf_io1_d4_12db)
// );
endmodule
hdl/tdma.v
+148 -79
View File
@@ -13,108 +13,177 @@
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
// ! WHEN U INSTANTIATE THIS MODULE
module tdma #(
parameter SLOT_LEN = 1250000,
parameter TIC_TO_PS_LEN = 1200000,
parameter TIC_FRAME_SYNC = 42272
) (
input clk,
input rst,
input flag_is_master,
input flag_frame_sync,
output intr_2ps,
// output tic_hop,
output tx_start
module tdma (
input clk,
input rst,
// PHY parameter
input flag_frame_sync,
// general parameter, update only once
input wire [23:0] tdma_slot_len,
input wire [23:0] tdma_tic_2_ps,
input wire [ 7:0] tdma_slot_num,
input wire [23:0] tdma_frame_sync_tic,
input wire [ 7:0] local_id, // ID number for this device
// update while received valid
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
input wire [ 7:0] recevied_cur_slot_id,
output intr_2ps,
output tx_start,
output reg rx_rst
);
// TODO: 需要检查综合后电路是否会被优化
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
// ******** Wire & Reg ********
reg flag_is_tx_slot;
reg flag_next_slot_is_tx_slot;
reg [23:0] cnt_tdma_slot_len;
reg [ 7:0] cur_slot_id;
wire flag_end_of_one_slot; // the last period of the slot
wire [23:0] tdma_tic_frame_sync_vio;
// fsm
localparam S_IDLE = 0;
localparam S_RX = 1;
localparam S_TX = 2;
reg [1:0] cs = 0;
reg [1:0] ns = 0;
// ******** Assingment ********
assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
// ******** Logic Block ********
generate
if (SLOT_LEN <= 65535) begin // slot len is small
reg [15:0] cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 16'd0;
// fsm
always @(posedge clk) begin
if (rst) begin
cs <= S_IDLE;
end
else begin
cs <= ns;
end
end
// conditional transition
always @(*) begin
ns = cs;
case (cs)
S_IDLE: begin
// if this device is master node, ps should first send one packet to the fifo
if (local_id == 1) begin
ns = S_TX;
end
else begin
if (!flag_is_master && flag_frame_sync) begin
// slave update cnt
cnt <= TIC_FRAME_SYNC;
end
else if (cnt >= SLOT_LEN - 1) begin
cnt <= 16'd0;
end
else begin
cnt <= cnt + 16'd1;
end
else if (recevied_cur_slot_id_valid) begin
ns = S_RX;
end
end
assign tx_start = flag_is_tx_slot & (cnt == 16'd10); // just a num for avoiding the zero,(cnt is also 0 in rst state)
assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
S_RX: begin
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_TX;
end
end
S_TX: begin
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
ns = S_RX;
end
end
default: begin
ns = S_IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
flag_is_tx_slot <= 0;
end
else if (!flag_is_master && flag_frame_sync) begin
flag_is_tx_slot <= 0;
end
else if (cnt == 16'd1) begin
flag_is_tx_slot <= ~flag_is_tx_slot;
end
always @(posedge clk) begin
if (rst) begin
cnt_tdma_slot_len <= 0;
end
else if (flag_frame_sync) begin
cnt_tdma_slot_len <= tdma_frame_sync_tic;
end
else begin
if (flag_end_of_one_slot) begin
cnt_tdma_slot_len <= 0;
end
else begin
cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
end
end
end
always @(*) begin
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
rx_rst <= 1;
end
else begin
rx_rst <= 0;
end
end
always @(posedge clk) begin
if (cs == S_IDLE) begin
if (ns == S_TX) begin // indicating master node
cur_slot_id <= 1;
end
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
cur_slot_id <= recevied_cur_slot_id;
end
else begin
cur_slot_id <= 0;
end
end
else begin
reg [15:0] cnt_l;
reg [ 7:0] cnt_h;
always @(posedge clk) begin
if (rst) begin
cnt_l <= 16'd0;
cnt_h <= 8'd0;
if (recevied_cur_slot_id_valid) begin // from ps update
cur_slot_id <= recevied_cur_slot_id;
end
else if (flag_end_of_one_slot) begin // at the changing moment
if (cur_slot_id == tdma_slot_num) begin
cur_slot_id <= 1;
end
else begin
if (!flag_is_master && flag_frame_sync) begin
// slave update cnt
{cnt_h, cnt_l} <= TIC_FRAME_SYNC;
end
else begin
// master
if ({cnt_h, cnt_l} >= SLOT_LEN) begin
cnt_h <= 8'd0;
cnt_l <= 16'd0;
end
else begin
{cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1;
end
end
end
end
assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10);
assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN);
always @(posedge clk) begin
if (rst) begin
flag_is_tx_slot <= 0;
end
else if (!flag_is_master && flag_frame_sync) begin
flag_is_tx_slot <= 0;
end
else if ({cnt_h, cnt_l} == 16'd1) begin
flag_is_tx_slot <= ~flag_is_tx_slot;
cur_slot_id <= cur_slot_id + 1;
end
end
end
endgenerate
end
always @(posedge clk) begin
if (local_id == 1) begin
flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
end
else begin
flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
end
end
// ******** Inst ********
// ******** Debug ********
vio_tdma u_vio_tdma (
.clk (clk),
.probe_in0(tdma_slot_len),
.probe_in1(tdma_tic_2_ps),
.probe_in2(tdma_slot_num),
.probe_in3(local_id),
.probe_in4(tdma_frame_sync_tic)
);
ila_mac_layer u_ila_mac_layer (
.clk (clk),
.probe0(cnt_tdma_slot_len), // width: 24
.probe1(tx_start), // width: 1
.probe2(rx_rst), // width: 1
.probe3(cur_slot_id), // width: 8
.probe4(intr_2ps), // width: 1
.probe5(flag_frame_sync), // width: 1
.probe6(recevied_cur_slot_id), // width: 8
.probe7(recevied_cur_slot_id_valid) // width: 1
);
endmodule
hdl/width_convert.v
+3 -3
View File
@@ -12,13 +12,13 @@
// * NOTE : this is the first version convert from wider bitwidth to narrower bitwidth
module width_convert #(
parameter INPUT_WIDTH = 16,
parameter OUTPUT_WIDTH = 2
parameter INPUT_WIDTH = 32,
parameter OUTPUT_WIDTH = 1
) (
input clk,
input rst,
input data_in_valid,
input wire data_in_ready,
output wire data_in_ready,
input wire [INPUT_WIDTH - 1 : 0] data_in,
output reg data_out_valid,
output reg [OUTPUT_WIDTH -1 : 0] data_out
sim/tb_extract_mac_frame.v
+82
View File
@@ -0,0 +1,82 @@
`timescale 1ns / 1ns
module tb_extract_mac_frame ();
reg clk = 0;
always #1 clk <= ~clk;
reg [ 3:0] cnt_startup = 0;
reg rst;
reg ldpc_in;
reg [31:0] cnt_in = 0;
reg [ 4:0] cnt_sleep = 0;
reg sleep = 0;
reg cnt_in_valid = 0;
wire m_axis_mac_frame_tvalid;
wire [31:0] m_axis_mac_frame_tdata;
wire m_axis_mac_frame_tlast;
always @(posedge clk) begin
if (m_axis_mac_frame_tlast == 1) begin
cnt_startup <= 0;
end
else if (cnt_startup < 4'hF) begin
cnt_startup <= cnt_startup + 1;
end
rst <= cnt_startup <= 4'hC;
end
always @(posedge clk) begin
if (rst) begin
cnt_in <= 0;
end
ldpc_in <= $random();
if (cnt_startup == 4'hF) begin
if (sleep) begin
cnt_in <= 0;
cnt_in_valid <= 0;
cnt_sleep <= cnt_sleep + 1;
if (cnt_sleep == 5'b11111) begin
sleep <= 0;
end
end
else begin
cnt_sleep <= 0;
if (cnt_in < 1024) begin
cnt_in <= cnt_in + 1;
end
if (cnt_in == 1023) begin
sleep <= 1;
end
cnt_in_valid <= 1;
end
end
end
extract_mac_frame u_extract_mac_frame (
.clk (clk),
.rst (rst),
.ldpc_dec_out_start (cnt_startup == 4'hD),
.ldpc_dec_out_valid (cnt_in_valid),
.ldpc_dec_out_data (ldpc_in),
.m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid),
.m_axis_mac_frame_tdata (m_axis_mac_frame_tdata),
.m_axis_mac_frame_tready(1),
.m_axis_mac_frame_tlast (m_axis_mac_frame_tlast)
);
endmodule
sim/tb_scrambler.v
+53
View File
@@ -0,0 +1,53 @@
`timescale 1ns / 1ns
module tb_scrambler ();
reg clk = 0;
always #1 clk <= ~clk;
reg [3:0] cnt_startup = 0;
reg rst;
always @(posedge clk) begin
if (cnt_startup < 4'hF) begin
cnt_startup <= cnt_startup + 1;
end
rst <= cnt_startup <= 4'hC;
end
reg [31:0] s_axis_tdata;
reg s_axis_tvalid;
wire s_axis_tready;
reg s_axis_tlast;
wire [31:0] m_axis_tdata;
wire m_axis_tvalid;
// wire m_axis_tvalid;
wire m_axis_tlast;
reg [31:0] cnt = 0;
always @(posedge clk) begin
s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
if (rst) begin
s_axis_tdata <= 0;
end
else if (s_axis_tready && cnt < 32) begin
s_axis_tdata <= cnt;
cnt <= cnt + 1;
end
end
scrambler u_scrambler (
.clk (clk),
.rst (rst),
.s_axis_tdata (s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast (s_axis_tlast),
.m_axis_tdata (m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(1),
.m_axis_tlast (m_axis_tlast)
);
endmodule
sim/tb_tdma.v
+66 -46
View File
@@ -22,60 +22,80 @@
module tb_tdma ();
reg clk = 1;
reg clk_tx = 1;
reg rst = 1;
always #1 clk <= ~clk;
initial begin
#1000 rst <= 1'b0;
#10 rst <= 1'b0;
end
wire flag_frame_sync_m;
reg flag_frame_sync_s = 0;
wire intr_2ps_m;
wire intr_2ps_s;
wire tic_hop_m;
wire tic_hop_s;
wire tx_start_m;
wire tx_start_s;
assign flag_frame_sync_m = 1'b0;
tdma #(
.SLOT_LEN (1250000),
.TIC_TO_PS_LEN (1200000),
.TIC_FRAME_SYNC(42272)
) u_tdma_master (
.clk (clk),
.rst (rst),
.flag_is_master (1'b1),
.flag_frame_sync(flag_frame_sync_m),
.intr_2ps (intr_2ps_m),
// .tic_hop (tic_hop_m),
.tx_start (tx_start_m)
);
tdma #(
.SLOT_LEN (20000),
.TIC_TO_PS_LEN (18000),
.TIC_FRAME_SYNC(2000)
) u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_is_master (1'b0),
.flag_frame_sync(flag_frame_sync_s),
.intr_2ps (intr_2ps_s),
// .tic_hop (tic_hop_s),
.tx_start (tx_start_s)
);
reg [7:0] local_id = 0;
initial begin
#12000 flag_frame_sync_s <= 1'b1;
#3 flag_frame_sync_s <= 1'b0;
#20 local_id <= 1;
end
reg flag_frame_sync = 0;
reg recevied_cur_slot_id_valid = 0;
reg [7:0] recevied_cur_slot_id = 0;
tdma u_tdma_master (
.clk (clk),
.rst (rst),
.flag_frame_sync (flag_frame_sync),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd4),
.local_id (local_id),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid),
.recevied_cur_slot_id (recevied_cur_slot_id),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
reg flag_frame_sync_slave = 0;
reg recevied_cur_slot_id_valid_slave = 0;
reg [7:0] recevied_cur_slot_id_slave = 7;
reg [7:0] local_id_slave = 10;
reg [7:0] cnt = 0;
always @(posedge clk) begin
if (cnt < 8'hFF) begin
cnt <= cnt + 1;
end
end
always @(posedge clk) begin
if (cnt == 8'hF3) begin
flag_frame_sync_slave <= 1;
end
else begin
flag_frame_sync_slave <= 0;
end
if (cnt == 8'hFE) begin
recevied_cur_slot_id_valid_slave <= 1;
end
else begin
recevied_cur_slot_id_valid_slave <= 0;
end
end
tdma u_tdma_slave (
.clk (clk),
.rst (rst),
.flag_frame_sync (flag_frame_sync_slave),
.tdma_slot_len (24'd7500),
.tdma_tic_2_ps (24'd6000),
.tdma_slot_num (8'd10),
.local_id (local_id_slave),
.recevied_cur_slot_id_valid(recevied_cur_slot_id_valid_slave),
.recevied_cur_slot_id (recevied_cur_slot_id_slave),
.intr_2ps (),
.tx_start (),
.rx_rst ()
);
endmodule
util.tcl
+38
View File
@@ -0,0 +1,38 @@
# this is a demo create ip using tcl script
# create a new ip ila named ila_rx2, if the ip already exists, skip create_ip step
create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_tdma
# set the ip property
set_property -dict [list \
CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_NUM_OF_PROBES {22} \
CONFIG.C_PROBE0_WIDTH {12} \
CONFIG.C_PROBE1_WIDTH {12} \
CONFIG.C_PROBE2_WIDTH {12} \
CONFIG.C_PROBE3_WIDTH {12} \
CONFIG.C_PROBE4_WIDTH {1} \
CONFIG.C_PROBE5_WIDTH {1} \
CONFIG.C_PROBE6_WIDTH {1} \
CONFIG.C_PROBE7_WIDTH {10} \
CONFIG.C_PROBE8_WIDTH {10} \
CONFIG.C_PROBE9_WIDTH {1} \
CONFIG.C_PROBE10_WIDTH {10} \
CONFIG.C_PROBE11_WIDTH {10} \
CONFIG.C_PROBE12_WIDTH {1} \
CONFIG.C_PROBE13_WIDTH {10} \
CONFIG.C_PROBE14_WIDTH {10} \
CONFIG.C_PROBE15_WIDTH {1} \
CONFIG.C_PROBE16_WIDTH {10} \
CONFIG.C_PROBE17_WIDTH {10} \
CONFIG.C_PROBE18_WIDTH {1} \
CONFIG.C_PROBE19_WIDTH {1} \
CONFIG.C_PROBE20_WIDTH {9} \
CONFIG.C_PROBE21_WIDTH {9} \
] [get_ips ila_recv_top]
set_property -dict [list \
CONFIG.C_NUM_OF_PROBES {6} \
CONFIG.C_PROBE0_WIDTH {24} \
] [get_ips ila_tdma]