Compare commits
17
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 ZoroGH
|
6ddf033548 | ||
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ZoroGH
|
26c24ae5b2 | ||
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ZoroGH
|
4b4f9dc671 | ||
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ZoroGH
|
3990e3081a | ||
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ZoroGH
|
5e8d69a0b0 | ||
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ZoroGH
|
a4eb609aae | ||
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ZoroGH
|
145e8c0930 | ||
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ZoroGH
|
92583b785c | ||
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ZoroGH
|
de8ca3db68 | ||
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ZoroGH
|
7751749856 | ||
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ZoroGH
|
0bedb6c2ef | ||
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ZoroGH
|
09fe5b3f8d | ||
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ZoroGH
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51eee95b60 | ||
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ZoroGH
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48c59b64ff | ||
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ZoroGH
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da1073f750 | ||
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ZoroGH
|
d210233e74 | ||
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ZoroGH
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e33875ef8f |
@@ -1,3 +1,5 @@
|
||||
adi_library
|
||||
c/**
|
||||
ip
|
||||
.tags
|
||||
sim/sim_data
|
||||
+2029
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+10589
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,11 @@
|
||||
memory_initialization_radix=2;
|
||||
memory_initialization_vector=
|
||||
01010101111100101000010011111111
|
||||
11111010011001101010001100000111
|
||||
00101001010100111011101100111101
|
||||
01100011110011100110001011010010
|
||||
01111101101111010111010001000011
|
||||
10010000010101101101011001011000
|
||||
00010010111000000110010010011011
|
||||
00000101111000110100000001000111
|
||||
;
|
||||
@@ -0,0 +1,2 @@
|
||||
memory_initialization_radix=16;
|
||||
memory_initialization_vector=00007FFF 01927FFD 06487FD8 0E1C7F37 18F97D89 26A87A05 36BA73B5 4869698B 5A825A82 6B4A45CD 78842B1F 7F860AFB 7D89E707 7022C248 55F5A129 2F878928 00008001 CD928A5B A129AA0B 8512DC5A 827718F9 9E105268 D4E17884 1A827D39 5A825A82 7DD5176E 73B5C946 3AF28E63 E7078277 9C12B005 80280648 A69C5B9C 00007FFF 5B9C5964 7FD8F9B8 4FFB9C12 E7078277 8E63C50E 8C4B36BA E8927DD5 5A825A82 7D39E57E 2B1F877C AD989E10 827718F9 DC5A7AEE 5ED755F5 75A5CD92 00008001 8928D079 AA0B5ED7 3DB87022 7D89E707 0AFB807A 877CD4E1 BA336B4A 5A825A82 698BB797 C9468C4B 85FB26A8 18F97D89 7F37F1E4 F9B88028 80030192 00007FFF 7FFDFE6E F9B88028 80C90E1C 18F97D89 7A05D958 C9468C4B 96754869 5A825A82 45CD94B6 877CD4E1 F5057F86 7D89E707 C2488FDE AA0B5ED7 76D82F87 00008001 8A5B326E 5ED755F5 23A68512 827718F9 526861F0 2B1F877C 82C71A82 5A825A82 176E822B 8C4B36BA 719D3AF2 E7078277 B00563EE 7FD8F9B8 A464A69C 00007FFF 5964A464 80280648 63EE4FFB E7078277 C50E719D 73B5C946 822BE892 5A825A82 E57E82C7 D4E17884 61F0AD98 827718F9 7AEE23A6 A129AA0B 326E75A5 00008001 D07976D8 55F5A129 8FDE3DB8 7D89E707 807AF505 78842B1F 94B6BA33 5A825A82 B7979675 36BA73B5 D95885FB 18F97D89 F1E480C9 06487FD8 FE6E8003 00007FFF FE6E8003 06487FD8 F1E480C9 18F97D89 D95885FB 36BA73B5 B7979675 5A825A82 94B6BA33 78842B1F 807AF505 7D89E707 8FDE3DB8 55F5A129 D07976D8 00008001 326E75A5 A129AA0B 7AEE23A6 827718F9 61F0AD98 D4E17884 E57E82C7 5A825A82 822BE892 73B5C946 C50E719D E7078277 63EE4FFB 80280648 5964A464 00007FFF A464A69C 7FD8F9B8 B00563EE E7078277 719D3AF2 8C4B36BA 176E822B 5A825A82 82C71A82 2B1F877C 526861F0 827718F9 23A68512 5ED755F5 8A5B326E 00008001 76D82F87 AA0B5ED7 C2488FDE 7D89E707 F5057F86 877CD4E1 45CD94B6 5A825A82 96754869 C9468C4B 7A05D958 18F97D89 80C90E1C F9B88028 7FFDFE6E 00007FFF 80030192 F9B88028 7F37F1E4 18F97D89 85FB26A8 C9468C4B 698BB797 5A825A82 BA336B4A 877CD4E1 0AFB807A 7D89E707 3DB87022 AA0B5ED7 8928D079 00008001 75A5CD92 5ED755F5 DC5A7AEE 827718F9 AD989E10 2B1F877C 7D39E57E 5A825A82 E8927DD5 8C4B36BA 8E63C50E E7078277 4FFB9C12 7FD8F9B8 5B9C5964 00007FFF A69C5B9C 80280648 9C12B005 E7078277 3AF28E63 73B5C946 7DD5176E 5A825A82 1A827D39 D4E17884 9E105268 827718F9 8512DC5A A129AA0B CD928A5B 00008001 2F878928 55F5A129 7022C248 7D89E707 7F860AFB 78842B1F 6B4A45CD 5A825A82 4869698B 36BA73B5 26A87A05 18F97D89 0E1C7F37 06487FD8 01927FFD;
|
||||
@@ -0,0 +1,258 @@
|
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memory_initialization_radix=10;
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|
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memory_initialization_radix=10;
|
||||
memory_initialization_vector=
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78;
|
||||
+24
-24
@@ -1,28 +1,28 @@
|
||||
radix=10;
|
||||
coefdata=
|
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-1053
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|
||||
-1263
|
||||
8366
|
||||
19870
|
||||
29190
|
||||
-761
|
||||
-441
|
||||
766
|
||||
1954
|
||||
1708
|
||||
-660
|
||||
-4042
|
||||
-5641
|
||||
-2532
|
||||
6186
|
||||
18176
|
||||
28624
|
||||
32767
|
||||
29190
|
||||
19870
|
||||
8366
|
||||
-1263
|
||||
-6256
|
||||
-6185
|
||||
-2791
|
||||
1180
|
||||
3453
|
||||
3216
|
||||
1199
|
||||
-1053
|
||||
28624
|
||||
18176
|
||||
6186
|
||||
-2532
|
||||
-5641
|
||||
-4042
|
||||
-660
|
||||
1708
|
||||
1954
|
||||
766
|
||||
-441
|
||||
-761
|
||||
;
|
||||
@@ -0,0 +1,28 @@
|
||||
radix=10;
|
||||
coefdata=
|
||||
-1053
|
||||
1199
|
||||
3216
|
||||
3453
|
||||
1180
|
||||
-2791
|
||||
-6185
|
||||
-6256
|
||||
-1263
|
||||
8366
|
||||
19870
|
||||
29190
|
||||
32767
|
||||
29190
|
||||
19870
|
||||
8366
|
||||
-1263
|
||||
-6256
|
||||
-6185
|
||||
-2791
|
||||
1180
|
||||
3453
|
||||
3216
|
||||
1199
|
||||
-1053
|
||||
;
|
||||
@@ -1,3 +1,21 @@
|
||||
set_property MAX_FANOUT 512 [get_nets *u_Receiver/mag*]
|
||||
set_property MAX_FANOUT 512 [get_nets *u_RecvTop/mag*]
|
||||
# set_property MAX_FANOUT 512 [get_nets u_Receiver/mag_valid]
|
||||
set_false_path -through [get_nets u_Receiver/rst]
|
||||
# set_false_path -through [get_nets u_Receiver/rst]
|
||||
# set_false_path -through [get_nets u_RecvTop/SR[0]]
|
||||
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rst]
|
||||
set_false_path -through [get_nets phy_tx_test_flag]
|
||||
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_tx_iq_reverse]
|
||||
set_false_path -through [get_nets u_MM7020_BD_wrapper/phy_rx_iq_reverse]
|
||||
set_false_path -through [get_nets tdma_flag_is_master]
|
||||
set_false_path -through [get_nets tdma_slot_len*]
|
||||
set_false_path -through [get_nets tdma_tic_2_ps*]
|
||||
set_false_path -through [get_nets u_tdma/tdma_tic_frame_sync_vio*]
|
||||
set_false_path -through [get_nets rx_rst]
|
||||
set_false_path -through [get_nets rst_sys]
|
||||
set_false_path -through [get_nets rst20]
|
||||
|
||||
set_false_path -through [get_nets u_RecvTop/flag_mgc_done]
|
||||
set_false_path -through [get_nets u_RecvTop/flag_frame_sync]
|
||||
set_false_path -through [get_nets u_RecvTop/mgc_start_quarter]
|
||||
set_false_path -through [get_nets u_RecvTop/rst_frame_sync]
|
||||
set_false_path -through [get_nets u_RecvTop/err_flag]
|
||||
|
||||
@@ -0,0 +1,133 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/14 18:02:13
|
||||
// Design Name:
|
||||
// Module Name: ApproxAbs_12bit
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ApproxAbs_18bit(
|
||||
input clk,
|
||||
input ND,
|
||||
input [17:0] Din_I,
|
||||
input [17:0] Din_Q,
|
||||
|
||||
output reg [18:0] Dout,
|
||||
output reg Rdy
|
||||
);
|
||||
|
||||
|
||||
|
||||
// 第一级延迟：把输入变负值：
|
||||
reg [17:0] Din_I_neg;
|
||||
always @ (posedge clk) begin
|
||||
if (Din_I[17:0]==18'b10_0000_0000_0000_0000)
|
||||
Din_I_neg[17:0] <= 18'b01_1111_1111_1111_1111;
|
||||
else
|
||||
Din_I_neg[17:0] <= -Din_I[17:0];
|
||||
end
|
||||
|
||||
reg [17:0] Din_Q_neg;
|
||||
always @ (posedge clk) begin
|
||||
if (Din_Q[17:0]==18'b10_0000_0000_0000_0000)
|
||||
Din_Q_neg[17:0] <= 18'b01_1111_1111_1111_1111;
|
||||
else
|
||||
Din_Q_neg[17:0] <= -Din_Q[17:0];
|
||||
end
|
||||
|
||||
|
||||
// 第二级延迟：求绝对值：
|
||||
reg [17:0] Din_I_D1;
|
||||
reg [17:0] Din_Q_D1;
|
||||
always @ (posedge clk) begin
|
||||
Din_I_D1[17:0] <= Din_I[17:0];
|
||||
Din_Q_D1[17:0] <= Din_Q[17:0];
|
||||
end
|
||||
|
||||
reg [17:0] Abs_Din_I;
|
||||
reg [17:0] Abs_Din_Q;
|
||||
always @ (posedge clk) begin
|
||||
if(Din_I_D1[17]==1'b1)
|
||||
Abs_Din_I[17:0] <= Din_I_neg[17:0];
|
||||
else
|
||||
Abs_Din_I[17:0] <= Din_I_D1[17:0];
|
||||
if(Din_Q_D1[17]==1'b1)
|
||||
Abs_Din_Q[17:0] <= Din_Q_neg[17:0];
|
||||
else
|
||||
Abs_Din_Q[17:0] <= Din_Q_D1[17:0];
|
||||
end
|
||||
|
||||
|
||||
// 第三级延迟：确定I/Q两路绝对值的大小关系：
|
||||
reg [17:0] AbsIQ_max;
|
||||
reg [17:0] AbsIQ_min;
|
||||
always @ (posedge clk) begin
|
||||
if (Abs_Din_I[17:0]>=Abs_Din_Q[17:0]) begin
|
||||
AbsIQ_max[17:0] <= Abs_Din_I[17:0];
|
||||
AbsIQ_min[17:0] <= Abs_Din_Q[17:0];
|
||||
end
|
||||
else begin
|
||||
AbsIQ_max[17:0] <= Abs_Din_Q[17:0];
|
||||
AbsIQ_min[17:0] <= Abs_Din_I[17:0];
|
||||
end
|
||||
end
|
||||
|
||||
// 第四级延迟：MXQ选择的系数：7/8和1/2：
|
||||
reg [17:0] AbsIQ_max_7by8;
|
||||
reg [17:0] AbsIQ_min_1by2;
|
||||
always @ (posedge clk) begin
|
||||
AbsIQ_max_7by8[17:0] <= AbsIQ_max[17:0]-{3'b000,AbsIQ_max[17:3]};
|
||||
AbsIQ_min_1by2[17:0] <= {AbsIQ_min[17],AbsIQ_min[17:1]};
|
||||
end
|
||||
|
||||
// 第五级延迟：1bit位扩展求和：
|
||||
// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
|
||||
reg [18:0] Dout_Temp;
|
||||
reg [18:0] Dout_Temp1;
|
||||
reg [18:0] Dout_Temp2;
|
||||
always @ (posedge clk) begin
|
||||
Dout_Temp[18:0] <= {1'b0,AbsIQ_max_7by8[17:0]} + {1'b0,AbsIQ_min_1by2[17:0]};
|
||||
Dout_Temp1[18:0] <= {1'b0,AbsIQ_max[17:0]};
|
||||
Dout_Temp2[18:0] <= Dout_Temp1[18:0];
|
||||
end
|
||||
|
||||
// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if(Dout_Temp[18:0]>=Dout_Temp2[17:0])
|
||||
Dout[18:0] <= Dout_Temp[18:0];
|
||||
else
|
||||
Dout[18:0] <= Dout_Temp2[18:0];
|
||||
end
|
||||
|
||||
// 产生Rdy，与ND有六级延迟：
|
||||
reg Rdy_b5 = 1'b0;
|
||||
reg Rdy_b4 = 1'b0;
|
||||
reg Rdy_b3 = 1'b0;
|
||||
reg Rdy_b2 = 1'b0;
|
||||
reg Rdy_b1 = 1'b0;
|
||||
|
||||
always@(posedge clk) begin//(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
|
||||
Rdy_b5 <= ND;
|
||||
Rdy_b4 <= Rdy_b5;
|
||||
Rdy_b3 <= Rdy_b4;
|
||||
Rdy_b2 <= Rdy_b3;
|
||||
Rdy_b1 <= Rdy_b2;
|
||||
Rdy <= Rdy_b1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,125 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 18:12 11/14/2019
|
||||
// Design Name:
|
||||
// Module Name: ApproxAbs_v1
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
// 1. 在ApproxAbs基础上，由MXQ仿真、修改得到。
|
||||
// 2. 主要修改有两处：A.如果Max比(7/8*max+1/2*min)更大，就输出max。这样更准确。
|
||||
// B.原版在生成Dout_valid的逻辑中，犯了always后面没有“@ (posedge clk)”的错误。
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// v2（2015/11/07）：
|
||||
// 1. 更改输入为17bits，输出为18bits。
|
||||
// 2. 取消Din_valid和Dout_valid。改为ND和Rdy。
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module ApproxAbs_v2 (
|
||||
input clk,
|
||||
input ND,
|
||||
input [9:0] Din_I,
|
||||
input [9:0] Din_Q,
|
||||
output reg [10:0] Dout = 11'd0,
|
||||
output reg Rdy = 1'b0
|
||||
);
|
||||
|
||||
|
||||
|
||||
// 第一级延迟：把输入变负值：
|
||||
reg [9:0] Din_I_neg;
|
||||
always @(posedge clk) begin
|
||||
if (Din_I[9:0] == 10'b1000_0000_00) Din_I_neg[9:0] <= 10'b0111_1111_11;
|
||||
else Din_I_neg[9:0] <= -Din_I[9:0];
|
||||
end
|
||||
|
||||
reg [9:0] Din_Q_neg;
|
||||
always @(posedge clk) begin
|
||||
if (Din_Q[9:0] == 10'b1000_0000_00) Din_Q_neg[9:0] <= 10'b0111_1111_11;
|
||||
else Din_Q_neg[9:0] <= -Din_Q[9:0];
|
||||
end
|
||||
|
||||
|
||||
// 第二级延迟：求绝对值：
|
||||
reg [9:0] Din_I_D1;
|
||||
reg [9:0] Din_Q_D1;
|
||||
always @(posedge clk) begin
|
||||
Din_I_D1[9:0] <= Din_I[9:0];
|
||||
Din_Q_D1[9:0] <= Din_Q[9:0];
|
||||
end
|
||||
|
||||
reg [9:0] Abs_Din_I;
|
||||
reg [9:0] Abs_Din_Q;
|
||||
always @(posedge clk) begin
|
||||
if (Din_I_D1[9] == 1'b1) Abs_Din_I[9:0] <= Din_I_neg[9:0];
|
||||
else Abs_Din_I[9:0] <= Din_I_D1[9:0];
|
||||
if (Din_Q_D1[9] == 1'b1) Abs_Din_Q[9:0] <= Din_Q_neg[9:0];
|
||||
else Abs_Din_Q[9:0] <= Din_Q_D1[9:0];
|
||||
end
|
||||
|
||||
|
||||
// 第三级延迟：确定I/Q两路绝对值的大小关系：
|
||||
reg [9:0] AbsIQ_max;
|
||||
reg [9:0] AbsIQ_min;
|
||||
always @(posedge clk) begin
|
||||
if (Abs_Din_I[9:0] >= Abs_Din_Q[9:0]) begin
|
||||
AbsIQ_max[9:0] <= Abs_Din_I[9:0];
|
||||
AbsIQ_min[9:0] <= Abs_Din_Q[9:0];
|
||||
end
|
||||
else begin
|
||||
AbsIQ_max[9:0] <= Abs_Din_Q[9:0];
|
||||
AbsIQ_min[9:0] <= Abs_Din_I[9:0];
|
||||
end
|
||||
end
|
||||
|
||||
// 第四级延迟：MXQ选择的系数：7/8和1/2：
|
||||
reg [9:0] AbsIQ_max_7by8;
|
||||
reg [9:0] AbsIQ_min_1by2;
|
||||
always @(posedge clk) begin
|
||||
AbsIQ_max_7by8[9:0] <= AbsIQ_max[9:0] - {3'b000, AbsIQ_max[9:3]};
|
||||
AbsIQ_min_1by2[9:0] <= {AbsIQ_min[9], AbsIQ_min[9:1]};
|
||||
end
|
||||
|
||||
// 第五级延迟：1bit位扩展求和：
|
||||
// (MXQ)中间将最大延迟一个clk赋给 Dout_Temp2,使 Dout_Temp2与 Dout_Temp在同一个clk下进行比较。
|
||||
reg [10:0] Dout_Temp;
|
||||
reg [10:0] Dout_Temp1;
|
||||
reg [10:0] Dout_Temp2;
|
||||
always @(posedge clk) begin
|
||||
Dout_Temp[10:0] <= {1'b0, AbsIQ_max_7by8[9:0]} + {1'b0, AbsIQ_min_1by2[9:0]};
|
||||
Dout_Temp1[10:0] <= {1'b0, AbsIQ_max[9:0]};
|
||||
Dout_Temp2[10:0] <= Dout_Temp1[10:0];
|
||||
end
|
||||
|
||||
// (MXQ)第六级延迟：输出求和值与I/Q两路绝对值最大值比较之后的最大值：
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (Dout_Temp[10:0] >= Dout_Temp2[9:0]) Dout[10:0] <= Dout_Temp[10:0];
|
||||
else Dout[10:0] <= Dout_Temp2[10:0];
|
||||
end
|
||||
|
||||
// 产生Rdy，与ND有六级延迟：
|
||||
reg Rdy_b5 = 1'b0;
|
||||
reg Rdy_b4 = 1'b0;
|
||||
reg Rdy_b3 = 1'b0;
|
||||
reg Rdy_b2 = 1'b0;
|
||||
reg Rdy_b1 = 1'b0;
|
||||
|
||||
always @(posedge clk) begin //(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
|
||||
Rdy_b5 <= ND;
|
||||
Rdy_b4 <= Rdy_b5;
|
||||
Rdy_b3 <= Rdy_b4;
|
||||
Rdy_b2 <= Rdy_b3;
|
||||
Rdy_b1 <= Rdy_b2;
|
||||
Rdy <= Rdy_b1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,145 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CCSDS_LDPC_DEC_K1024_R12
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CCSDS_LDPC_DEC_K1024_R12 #(
|
||||
parameter WIDTH = 4'd8,
|
||||
parameter MAX_ITER_NUM = 6'd14,
|
||||
parameter OUT_ONLY_INFORMATION = 1'b0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
|
||||
) (
|
||||
input clk, //工作时钟,100MHz
|
||||
input Rst, //同步复位信号,高有效
|
||||
input FrameSync, //帧同步标志,高脉冲
|
||||
input Nd, //译码输入数据有效标志,高有效
|
||||
input [WIDTH-1:0] Din, //译码输入数据,软信息,数据速率约为12.5Mbps
|
||||
|
||||
output reg LDPC_SyncOut = 1'b0, //LDPC模块帧同步输出信号,高脉冲,指示帧起点
|
||||
output reg Rdy = 1'b0, //译码输出信号有效标志,高有效
|
||||
output reg [0:0] LDPC_Dout = 1'b0, //译码输出信号
|
||||
output reg [8:0] good_frames = 9'd0, //译码好帧计数
|
||||
output reg [8:0] bad_frames = 9'd0, //译码坏帧计数
|
||||
output reg [8:0] total_frames = 9'd0 //译码总帧计数
|
||||
);
|
||||
|
||||
reg rst_MS = 1'd0;
|
||||
reg framesync_MS = 1'd0;
|
||||
reg nd_MS = 1'd0;
|
||||
reg [WIDTH-1:0] din_MS = 8'd0;
|
||||
reg oe_MS = 1'd0;
|
||||
wire deal_end_MS;
|
||||
wire [WIDTH-1:0] dout01_MS;
|
||||
wire [WIDTH-1:0] dout02_MS;
|
||||
wire [WIDTH-1:0] dout03_MS;
|
||||
wire [WIDTH-1:0] dout04_MS;
|
||||
|
||||
always @(posedge clk) begin
|
||||
rst_MS <= Rst;
|
||||
framesync_MS <= FrameSync;
|
||||
nd_MS <= Nd;
|
||||
din_MS <= Din;
|
||||
end
|
||||
//******输入数据的缓存模块
|
||||
Message_Store #(
|
||||
.WIDTH(WIDTH)
|
||||
) MS (
|
||||
.clk (clk),
|
||||
.rst_MS (rst_MS),
|
||||
.framesync_MS(framesync_MS),
|
||||
.nd_MS (nd_MS),
|
||||
.din_MS (din_MS),
|
||||
.oe_MS (oe_MS),
|
||||
.deal_end_MS (deal_end_MS),
|
||||
.syncout_MS (syncout_MS),
|
||||
.rdy_MS (rdy_MS),
|
||||
.dout01_MS (dout01_MS),
|
||||
.dout02_MS (dout02_MS),
|
||||
.dout03_MS (dout03_MS),
|
||||
.dout04_MS (dout04_MS)
|
||||
);
|
||||
|
||||
reg rst = 1'd0;
|
||||
reg start = 1'd0;
|
||||
reg framesync = 1'd0;
|
||||
reg nd = 1'd0;
|
||||
|
||||
reg [WIDTH-1:0] din01 = 8'd0;
|
||||
reg [WIDTH-1:0] din02 = 8'd0;
|
||||
reg [WIDTH-1:0] din03 = 8'd0;
|
||||
reg [WIDTH-1:0] din04 = 8'd0;
|
||||
|
||||
wire ask_din;
|
||||
wire [ 8:0] gd_frames;
|
||||
wire [ 8:0] bd_frames;
|
||||
wire [ 8:0] tl_frames;
|
||||
|
||||
wire ldpc_syncout;
|
||||
wire rdy;
|
||||
wire [ 0:0] ldpc_dout;
|
||||
|
||||
always @(posedge clk) begin
|
||||
rst <= Rst;
|
||||
start <= deal_end_MS;
|
||||
framesync <= syncout_MS;
|
||||
nd <= rdy_MS;
|
||||
|
||||
din01 <= dout01_MS;
|
||||
din02 <= dout02_MS;
|
||||
din03 <= dout03_MS;
|
||||
din04 <= dout04_MS;
|
||||
|
||||
oe_MS <= ask_din;
|
||||
end
|
||||
// TOP层译码器输出
|
||||
always @(posedge clk) begin
|
||||
LDPC_SyncOut <= ldpc_syncout;
|
||||
Rdy <= rdy;
|
||||
LDPC_Dout <= ldpc_dout;
|
||||
good_frames <= gd_frames;
|
||||
bad_frames <= bd_frames;
|
||||
total_frames <= tl_frames;
|
||||
end
|
||||
LDPC_DEC_PRO //译码器的吞吐量=(信息比特数/(一次迭代所需的时钟数*迭代次数))*FPGA工作主频
|
||||
#(
|
||||
.MAX_ITER_NUM(MAX_ITER_NUM),
|
||||
.WIDTH(WIDTH),
|
||||
.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
|
||||
) LDPC_DEC (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (start),
|
||||
.framesync (framesync),
|
||||
.nd (nd),
|
||||
.din01 (din01),
|
||||
.din02 (din02),
|
||||
.din03 (din03),
|
||||
.din04 (din04),
|
||||
.ask_din (ask_din),
|
||||
.gd_frames (gd_frames),
|
||||
.bd_frames (bd_frames),
|
||||
.tl_frames (tl_frames),
|
||||
.ldpc_syncout(ldpc_syncout),
|
||||
.rdy (rdy),
|
||||
.ldpc_dout (ldpc_dout)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/14 17:44:48
|
||||
// Design Name:
|
||||
// Module Name: CCSDS_LDPC_DEC_K1024_R12_TOPP
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CCSDS_LDPC_DEC_K1024_R12_TOPP #(
|
||||
parameter MAX_ITER_NUM = 6'd14, //最大迭代次数常量
|
||||
parameter WIDTH = 4'd8, //量化比特
|
||||
parameter OUT_ONLY_INFORMATION = 1'b1 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
|
||||
) (
|
||||
input clk, //工作时钟,100MHz
|
||||
input Rst, //同步复位信号,高有效
|
||||
input FrameSync, //帧同步标志,高脉冲
|
||||
input Nd, //译码输入数据有效标志,高有效
|
||||
input [WIDTH-1:0] Din, //译码输入数据,软信息
|
||||
|
||||
|
||||
output LDPC_SyncOut, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
output Rdy, //译码输出信号有效标志,高有效
|
||||
output [0:0] LDPC_Dout, //译码输出信号,MSB输出
|
||||
|
||||
output [8:0] good_frames, //译码好帧计数
|
||||
output [8:0] bad_frames, //译码坏帧计数
|
||||
output [8:0] total_frames //译码总帧数计数
|
||||
);
|
||||
|
||||
wire FrameSync_A_TM;
|
||||
wire Nd_A_TM;
|
||||
wire [WIDTH-1:0] Din_A_TM;
|
||||
|
||||
wire FrameSync_B_TM;
|
||||
wire Nd_B_TM;
|
||||
wire [WIDTH-1:0] Din_B_TM;
|
||||
|
||||
wire LDPC_SyncOut_A;
|
||||
wire Rdy_A;
|
||||
wire [ 0:0] LDPC_Dout_A;
|
||||
wire [ 8:0] good_frames_A;
|
||||
wire [ 8:0] bad_frames_A;
|
||||
wire [ 8:0] total_frames_A;
|
||||
|
||||
wire LDPC_SyncOut_B;
|
||||
wire Rdy_B;
|
||||
wire [ 0:0] LDPC_Dout_B;
|
||||
wire [ 8:0] good_frames_B;
|
||||
wire [ 8:0] bad_frames_B;
|
||||
wire [ 8:0] total_frames_B;
|
||||
|
||||
|
||||
LDPC_TopManage_2 #(
|
||||
.WIDTH(WIDTH)
|
||||
) TM (
|
||||
.clk (clk),
|
||||
.Rst (Rst),
|
||||
.FrameSync_TM (FrameSync),
|
||||
.Nd_TM (Nd),
|
||||
.Din_TM (Din),
|
||||
.FrameSync_A_TM (FrameSync_A_TM),
|
||||
.Nd_A_TM (Nd_A_TM),
|
||||
.Din_A_TM (Din_A_TM),
|
||||
.FrameSync_B_TM (FrameSync_B_TM),
|
||||
.Nd_B_TM (Nd_B_TM),
|
||||
.Din_B_TM (Din_B_TM),
|
||||
.LDPC_SyncOut_A_TM(LDPC_SyncOut_A),
|
||||
.Rdy_A_TM (Rdy_A),
|
||||
.LDPC_Dout_A_TM (LDPC_Dout_A),
|
||||
.good_frames_A_TM (good_frames_A),
|
||||
.bad_frames_A_TM (bad_frames_A),
|
||||
.total_frames_A_TM(total_frames_A),
|
||||
.LDPC_SyncOut_B_TM(LDPC_SyncOut_B),
|
||||
.Rdy_B_TM (Rdy_B),
|
||||
.LDPC_Dout_B_TM (LDPC_Dout_B),
|
||||
.good_frames_B_TM (good_frames_B),
|
||||
.bad_frames_B_TM (bad_frames_B),
|
||||
.total_frames_B_TM(total_frames_B),
|
||||
.LDPC_SyncOut_TM (LDPC_SyncOut),
|
||||
.Rdy_TM (Rdy),
|
||||
.LDPC_Dout_TM (LDPC_Dout),
|
||||
.good_frames_TM (good_frames),
|
||||
.bad_frames_TM (bad_frames),
|
||||
.total_frames_TM (total_frames)
|
||||
);
|
||||
|
||||
CCSDS_LDPC_DEC_K1024_R12 #(
|
||||
.MAX_ITER_NUM(MAX_ITER_NUM),
|
||||
.WIDTH(WIDTH),
|
||||
.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
|
||||
) inst_DEC_A (
|
||||
.clk (clk),
|
||||
.Rst (Rst),
|
||||
.FrameSync (FrameSync_A_TM),
|
||||
.Nd (Nd_A_TM),
|
||||
.Din (Din_A_TM),
|
||||
.LDPC_SyncOut(LDPC_SyncOut_A),
|
||||
.Rdy (Rdy_A),
|
||||
.LDPC_Dout (LDPC_Dout_A),
|
||||
.good_frames (good_frames_A),
|
||||
.bad_frames (bad_frames_A),
|
||||
.total_frames(total_frames_A)
|
||||
);
|
||||
|
||||
CCSDS_LDPC_DEC_K1024_R12 #(
|
||||
.MAX_ITER_NUM(MAX_ITER_NUM),
|
||||
.WIDTH(WIDTH),
|
||||
.OUT_ONLY_INFORMATION(OUT_ONLY_INFORMATION)
|
||||
) inst_DEC_B (
|
||||
.clk (clk),
|
||||
.Rst (Rst),
|
||||
.FrameSync (FrameSync_B_TM),
|
||||
.Nd (Nd_B_TM),
|
||||
.Din (Din_B_TM),
|
||||
.LDPC_SyncOut(LDPC_SyncOut_B),
|
||||
.Rdy (Rdy_B),
|
||||
.LDPC_Dout (LDPC_Dout_B),
|
||||
.good_frames (good_frames_B),
|
||||
.bad_frames (bad_frames_B),
|
||||
.total_frames(total_frames_B)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+386
@@ -0,0 +1,386 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CK_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CK_PRO
|
||||
#(
|
||||
parameter Index_p1_row_01_dec_01_01=0, Index_p1_row_01_dec_02_01=0,
|
||||
parameter Index_p1_row_02_dec_02_01=0, Index_p1_row_02_dec_03_01=0,
|
||||
parameter Index_p1_row_03_dec_03_01=0, Index_p1_row_03_dec_04_01=0,
|
||||
parameter Index_p1_row_04_dec_04_01=0, Index_p1_row_04_dec_01_01=112,
|
||||
|
||||
parameter Index_p2_row_01_dec_05_01=0, Index_p2_row_01_dec_05_02=25, Index_p2_row_01_dec_08_01=31,Index_p2_row_01_dec_07_01=39,
|
||||
parameter Index_p2_row_02_dec_06_01=0, Index_p2_row_02_dec_06_02=75, Index_p2_row_02_dec_05_01=23,Index_p2_row_02_dec_08_01=16,
|
||||
parameter Index_p2_row_03_dec_07_01=0, Index_p2_row_03_dec_07_02=120,Index_p2_row_03_dec_06_01=54,Index_p2_row_03_dec_05_01=0,
|
||||
parameter Index_p2_row_04_dec_08_01=0, Index_p2_row_04_dec_08_02=93, Index_p2_row_04_dec_07_01=9, Index_p2_row_04_dec_06_01=83,
|
||||
|
||||
parameter Index_p3_row_01_dec_09_01=0, Index_p3_row_01_dec_09_02=13, Index_p3_row_01_dec_11_01=97, Index_p3_row_01_dec_10_01=0, Index_p3_row_01_dec_12_01=34,
|
||||
parameter Index_p3_row_02_dec_10_01=0, Index_p3_row_02_dec_10_02=69, Index_p3_row_02_dec_12_01=64, Index_p3_row_02_dec_11_01=6, Index_p3_row_02_dec_09_01=98,
|
||||
parameter Index_p3_row_03_dec_11_01=0, Index_p3_row_03_dec_11_02=127,Index_p3_row_03_dec_09_01=78, Index_p3_row_03_dec_12_01=35, Index_p3_row_03_dec_10_01=26,
|
||||
parameter Index_p3_row_04_dec_12_01=0, Index_p3_row_04_dec_12_02=29, Index_p3_row_04_dec_10_01=81, Index_p3_row_04_dec_09_01=99, Index_p3_row_04_dec_11_01=59
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_OUTCK,
|
||||
input start_OUTCK,
|
||||
input nd_OUTCK,
|
||||
input [0:0] DR_din_01,
|
||||
input [0:0] DR_din_02,
|
||||
input [0:0] DR_din_03,
|
||||
input [0:0] DR_din_04,
|
||||
input [0:0] DR_din_05,
|
||||
|
||||
output reg [8:0] gd_frames=9'd0,//译码好帧计数
|
||||
output reg [8:0] bd_frames=9'd0,//译码坏帧计数
|
||||
output reg [8:0] tl_frames=9'd0 //译码总帧数计数
|
||||
);
|
||||
|
||||
reg [127:0] dec_01 = 128'd0, dec_02 = 128'd0, dec_03 = 128'd0, dec_04 = 128'd0;
|
||||
reg [127:0] dec_05 = 128'd0, dec_06 = 128'd0, dec_07 = 128'd0, dec_08 = 128'd0;
|
||||
reg [127:0] dec_09 = 128'd0, dec_10 = 128'd0, dec_11 = 128'd0, dec_12 = 128'd0;
|
||||
reg [127:0] dec_01_d1 = 128'd0, dec_02_d1 = 128'd0, dec_03_d1 = 128'd0, dec_04_d1 = 128'd0;
|
||||
reg [127:0] dec_05_d1 = 128'd0, dec_06_d1 = 128'd0, dec_07_d1 = 128'd0, dec_08_d1 = 128'd0;
|
||||
reg [127:0] dec_09_d1 = 128'd0, dec_10_d1 = 128'd0, dec_11_d1 = 128'd0, dec_12_d1 = 128'd0;
|
||||
|
||||
reg [10:0] cnt_CK=11'd0;
|
||||
reg deal_end=1'd0,deal_end_d1=1'd0,deal_end_d2=1'd0,deal_end_d3=1'd0,deal_end_d4=1'd0,deal_end_d5=1'd0,dec_proc=1'd0;
|
||||
// 产生本模块的计数器
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUTCK) begin
|
||||
dec_proc <= 1'd0;
|
||||
cnt_CK <= 11'd0;
|
||||
end else begin
|
||||
if (start_OUTCK) begin
|
||||
dec_proc <= 1'd1;
|
||||
cnt_CK <= 11'd0;
|
||||
end else begin
|
||||
if (dec_proc) begin
|
||||
if (cnt_CK < 11'd560) begin
|
||||
cnt_CK <= cnt_CK + 11'd1;
|
||||
dec_proc <= dec_proc;
|
||||
end else begin
|
||||
cnt_CK <= cnt_CK;
|
||||
dec_proc <= 1'd0;
|
||||
end
|
||||
end else begin
|
||||
cnt_CK <= cnt_CK;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
parameter DELAY_DIN = 11'd0;
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUTCK || start_OUTCK) begin
|
||||
dec_01 <= 128'd0; dec_01_d1 <= 128'd0;
|
||||
dec_02 <= 128'd0; dec_02_d1 <= 128'd0;
|
||||
dec_03 <= 128'd0; dec_03_d1 <= 128'd0;
|
||||
dec_04 <= 128'd0; dec_04_d1 <= 128'd0;
|
||||
|
||||
dec_05 <= 128'd0; dec_05_d1 <= 128'd0;
|
||||
dec_06 <= 128'd0; dec_06_d1 <= 128'd0;
|
||||
dec_07 <= 128'd0; dec_07_d1 <= 128'd0;
|
||||
dec_08 <= 128'd0; dec_08_d1 <= 128'd0;
|
||||
|
||||
dec_09 <= 128'd0; dec_09_d1 <= 128'd0;
|
||||
dec_10 <= 128'd0; dec_10_d1 <= 128'd0;
|
||||
dec_11 <= 128'd0; dec_11_d1 <= 128'd0;
|
||||
dec_12 <= 128'd0; dec_12_d1 <= 128'd0;
|
||||
|
||||
deal_end <= 1'd0;
|
||||
end else begin
|
||||
// 本来3行5列的H矩阵转置后变成5行3列
|
||||
// 第1列（4*128=512）个校验子求解过程
|
||||
if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
|
||||
dec_01[Index_p1_row_01_dec_01_01] <= DR_din_03 ^ DR_din_05;
|
||||
dec_02[Index_p1_row_01_dec_02_01] <= DR_din_05;
|
||||
end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
|
||||
dec_01[Index_p1_row_01_dec_01_01] <= 1'd0;
|
||||
dec_02[Index_p1_row_02_dec_02_01] <= DR_din_03 ^ DR_din_05;
|
||||
dec_03[Index_p1_row_02_dec_03_01] <= DR_din_05;
|
||||
end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
|
||||
dec_03[Index_p1_row_03_dec_03_01] <= DR_din_03 ^ DR_din_05;
|
||||
dec_04[Index_p1_row_03_dec_04_01] <= DR_din_05;
|
||||
end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
|
||||
dec_04[Index_p1_row_04_dec_04_01] <= DR_din_03 ^ DR_din_05;
|
||||
dec_01[Index_p1_row_04_dec_01_01] <= DR_din_05;
|
||||
end else begin
|
||||
dec_01 <= dec_01;
|
||||
dec_02 <= dec_02;
|
||||
dec_03 <= dec_03;
|
||||
dec_04 <= dec_04;
|
||||
end
|
||||
|
||||
if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
|
||||
dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
|
||||
dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
|
||||
end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
|
||||
dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]} ^ dec_02;
|
||||
dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
|
||||
end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
|
||||
dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]} ^ dec_03;
|
||||
dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
|
||||
end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
|
||||
dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]} ^ dec_04;
|
||||
dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]} ^ dec_01;
|
||||
end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
|
||||
dec_01_d1 <= {dec_01_d1[0],dec_01_d1[127:1]};
|
||||
dec_02_d1 <= {dec_02_d1[0],dec_02_d1[127:1]};
|
||||
dec_03_d1 <= {dec_03_d1[0],dec_03_d1[127:1]};
|
||||
dec_04_d1 <= {dec_04_d1[0],dec_04_d1[127:1]};
|
||||
end else begin
|
||||
dec_01_d1 <= dec_01_d1;
|
||||
dec_02_d1 <= dec_02_d1;
|
||||
dec_03_d1 <= dec_03_d1;
|
||||
dec_04_d1 <= dec_04_d1;
|
||||
deal_end <= 1'd0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
// 第2列（4*128=512）个校验子求解过程
|
||||
if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
|
||||
dec_05[Index_p2_row_01_dec_05_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
|
||||
dec_05[Index_p2_row_01_dec_05_02] <= DR_din_05;
|
||||
dec_08[Index_p2_row_01_dec_08_01] <= DR_din_05;
|
||||
dec_07[Index_p2_row_01_dec_07_01] <= DR_din_05;
|
||||
end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
|
||||
dec_06[Index_p2_row_02_dec_06_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
|
||||
dec_06[Index_p2_row_02_dec_06_02] <= DR_din_05;
|
||||
dec_05[Index_p2_row_02_dec_05_01] <= DR_din_05;
|
||||
dec_05[Index_p2_row_01_dec_05_01] <= 1'd0;
|
||||
dec_05[Index_p2_row_01_dec_05_02] <= 1'd0;
|
||||
dec_08[Index_p2_row_02_dec_08_01] <= DR_din_05;
|
||||
dec_08[Index_p2_row_01_dec_08_01] <= 1'd0;
|
||||
dec_07[Index_p2_row_01_dec_07_01] <= 1'd0; //xhx
|
||||
end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
|
||||
dec_07[Index_p2_row_03_dec_07_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
|
||||
dec_07[Index_p2_row_03_dec_07_02] <= DR_din_05;
|
||||
dec_06[Index_p2_row_03_dec_06_01] <= DR_din_05;
|
||||
dec_06[Index_p2_row_02_dec_06_01] <= 1'd0;
|
||||
dec_06[Index_p2_row_02_dec_06_02] <= 1'd0;
|
||||
dec_05[Index_p2_row_03_dec_05_01] <= DR_din_05;
|
||||
dec_05[Index_p2_row_02_dec_05_01] <= 1'd0;
|
||||
dec_08[Index_p2_row_02_dec_08_01] <= 1'd0; //xhx
|
||||
end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
|
||||
dec_08[Index_p2_row_04_dec_08_01] <= DR_din_01 ^ DR_din_02 ^ DR_din_04;
|
||||
dec_08[Index_p2_row_04_dec_08_02] <= DR_din_05;
|
||||
dec_07[Index_p2_row_04_dec_07_01] <= DR_din_05;
|
||||
dec_07[Index_p2_row_03_dec_07_01] <= 1'd0;
|
||||
dec_07[Index_p2_row_03_dec_07_02] <= 1'd0;
|
||||
dec_06[Index_p2_row_04_dec_06_01] <= DR_din_05;
|
||||
dec_06[Index_p2_row_03_dec_06_01] <= 1'd0;
|
||||
dec_05[Index_p2_row_03_dec_05_01] <= 1'd0; //xhx
|
||||
end else begin
|
||||
dec_05 <= dec_05;
|
||||
dec_06 <= dec_06;
|
||||
dec_07 <= dec_07;
|
||||
dec_08 <= dec_08;
|
||||
end
|
||||
|
||||
if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]} ^ dec_05;
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]} ^ dec_06;
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]} ^ dec_07;
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]} ^ dec_08;
|
||||
end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
|
||||
dec_05_d1 <= {dec_05_d1[0],dec_05_d1[127:1]};
|
||||
dec_06_d1 <= {dec_06_d1[0],dec_06_d1[127:1]};
|
||||
dec_07_d1 <= {dec_07_d1[0],dec_07_d1[127:1]};
|
||||
dec_08_d1 <= {dec_08_d1[0],dec_08_d1[127:1]};
|
||||
end else begin
|
||||
dec_05_d1 <= dec_05_d1;
|
||||
dec_06_d1 <= dec_06_d1;
|
||||
dec_07_d1 <= dec_07_d1;
|
||||
dec_08_d1 <= dec_08_d1;
|
||||
end
|
||||
|
||||
|
||||
// 第3列（4*128=512）个校验子求解过程
|
||||
if (cnt_CK >= 11'd1 + DELAY_DIN && cnt_CK < 11'd129 + DELAY_DIN) begin
|
||||
dec_09[Index_p3_row_01_dec_09_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_09[Index_p3_row_01_dec_09_02] <= DR_din_04;
|
||||
dec_11[Index_p3_row_01_dec_11_01] <= DR_din_02;
|
||||
dec_10[Index_p3_row_01_dec_10_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_01_dec_12_01] <= DR_din_04;
|
||||
end else if (cnt_CK >= 11'd129 + DELAY_DIN && cnt_CK < 11'd257 + DELAY_DIN) begin
|
||||
dec_10[Index_p3_row_02_dec_10_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_10[Index_p3_row_02_dec_10_02] <= DR_din_04;
|
||||
dec_12[Index_p3_row_02_dec_12_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_01_dec_12_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_02_dec_11_01] <= DR_din_02;
|
||||
dec_11[Index_p3_row_01_dec_11_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_02_dec_09_01] <= DR_din_04;
|
||||
dec_09[Index_p3_row_01_dec_09_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_01_dec_09_02] <= 1'd0;
|
||||
end else if (cnt_CK >= 11'd257 + DELAY_DIN && cnt_CK < 11'd385 + DELAY_DIN) begin
|
||||
dec_11[Index_p3_row_03_dec_11_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_11[Index_p3_row_03_dec_11_02] <= DR_din_04;
|
||||
dec_11[Index_p3_row_02_dec_11_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_03_dec_09_01] <= DR_din_02;
|
||||
dec_09[Index_p3_row_02_dec_09_01] <= 1'd0;
|
||||
dec_12[Index_p3_row_03_dec_12_01] <= DR_din_02;
|
||||
dec_12[Index_p3_row_02_dec_12_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_03_dec_10_01] <= DR_din_04;
|
||||
dec_10[Index_p3_row_02_dec_10_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_02_dec_10_02] <= 1'd0;
|
||||
end else if (cnt_CK >= 11'd385 + DELAY_DIN && cnt_CK < 11'd513 + DELAY_DIN) begin
|
||||
dec_12[Index_p3_row_04_dec_12_01] <= DR_din_01 ^ DR_din_05;
|
||||
dec_12[Index_p3_row_04_dec_12_02] <= DR_din_04;
|
||||
dec_12[Index_p3_row_03_dec_12_01] <= 1'd0;
|
||||
dec_10[Index_p3_row_04_dec_10_01] <= DR_din_02;
|
||||
dec_10[Index_p3_row_03_dec_10_01] <= 1'd0;
|
||||
dec_09[Index_p3_row_04_dec_09_01] <= DR_din_02;
|
||||
dec_09[Index_p3_row_03_dec_09_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_04_dec_11_01] <= DR_din_04;
|
||||
dec_11[Index_p3_row_03_dec_11_01] <= 1'd0;
|
||||
dec_11[Index_p3_row_03_dec_11_02] <= 1'd0;
|
||||
end else begin
|
||||
dec_09 <= dec_09;
|
||||
dec_10 <= dec_10;
|
||||
dec_11 <= dec_11;
|
||||
dec_12 <= dec_12;
|
||||
end
|
||||
|
||||
if (cnt_CK >= 11'd2 + DELAY_DIN && cnt_CK < 11'd130 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd130 + DELAY_DIN && cnt_CK < 11'd258 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd258 + DELAY_DIN && cnt_CK < 11'd386 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK >= 11'd386 + DELAY_DIN && cnt_CK < 11'd514 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]} ^ dec_09;
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]} ^ dec_10;
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]} ^ dec_11;
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]} ^ dec_12;
|
||||
end else if (cnt_CK == 11'd514 + DELAY_DIN) begin
|
||||
dec_09_d1 <= {dec_09_d1[0],dec_09_d1[127:1]};
|
||||
dec_10_d1 <= {dec_10_d1[0],dec_10_d1[127:1]};
|
||||
dec_11_d1 <= {dec_11_d1[0],dec_11_d1[127:1]};
|
||||
dec_12_d1 <= {dec_12_d1[0],dec_12_d1[127:1]};
|
||||
end else begin
|
||||
dec_09_d1 <= dec_09_d1;
|
||||
dec_10_d1 <= dec_10_d1;
|
||||
dec_11_d1 <= dec_11_d1;
|
||||
dec_12_d1 <= dec_12_d1;
|
||||
end
|
||||
|
||||
// 产生标志位
|
||||
if (cnt_CK == 11'd514 + DELAY_DIN)
|
||||
deal_end <= 1'd1;
|
||||
else
|
||||
deal_end <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
//2019.02.28添加：打一拍，尝试避免时序问题
|
||||
reg deal_end_d6 = 1'd0;
|
||||
reg flag_judge1 = 1'd0;
|
||||
reg flag_judge2 = 1'd0;
|
||||
reg flag_judge3 = 1'd0;
|
||||
always@(posedge clk) begin
|
||||
if(rst_OUTCK) begin
|
||||
flag_judge1 <= 1'd0;
|
||||
flag_judge2 <= 1'd0;
|
||||
flag_judge3 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(deal_end_d5) begin
|
||||
if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 ) flag_judge1 <= 1'd0;
|
||||
else flag_judge1 <= 1'd1;
|
||||
if(dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 ) flag_judge2 <= 1'd0;
|
||||
else flag_judge2 <= 1'd1;
|
||||
if(dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) flag_judge3 <= 1'd0;
|
||||
else flag_judge3 <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
flag_judge1 <= flag_judge1;
|
||||
flag_judge2 <= flag_judge2;
|
||||
flag_judge3 <= flag_judge3;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge clk) begin
|
||||
if(rst_OUTCK) begin
|
||||
gd_frames <= 9'd0;
|
||||
bd_frames <= 9'd0;
|
||||
tl_frames <= 9'd0;
|
||||
deal_end_d1 <= 1'd0;
|
||||
deal_end_d2 <= 1'd0;
|
||||
deal_end_d3 <= 1'd0;
|
||||
deal_end_d4 <= 1'd0;
|
||||
deal_end_d5 <= 1'd0;
|
||||
deal_end_d6 <= 1'd0; //2019.02.28添加
|
||||
end else begin
|
||||
deal_end_d1 <= deal_end;
|
||||
deal_end_d2 <= deal_end_d1;
|
||||
deal_end_d3 <= deal_end_d2;
|
||||
deal_end_d4 <= deal_end_d3;
|
||||
deal_end_d5 <= deal_end_d4;
|
||||
deal_end_d6 <= deal_end_d5; //2019.02.28添加
|
||||
if(deal_end_d6) begin
|
||||
if(flag_judge1 == 1'd0 && flag_judge2 == 1'd0 && flag_judge3 == 1'd0 ) begin
|
||||
// if(dec_01_d1 == 128'd0 && dec_02_d1 == 128'd0 && dec_03_d1 == 128'd0 && dec_04_d1 == 128'd0 &&
|
||||
// dec_05_d1 == 128'd0 && dec_06_d1 == 128'd0 && dec_07_d1 == 128'd0 && dec_08_d1 == 128'd0 &&
|
||||
// dec_09_d1 == 128'd0 && dec_10_d1 == 128'd0 && dec_11_d1 == 128'd0 && dec_12_d1 == 128'd0 ) begin
|
||||
gd_frames <= gd_frames + 9'd1;
|
||||
bd_frames <= bd_frames;
|
||||
tl_frames <= tl_frames + 9'd1;
|
||||
end else begin
|
||||
gd_frames <= gd_frames;
|
||||
bd_frames <= bd_frames + 9'd1;
|
||||
tl_frames <= tl_frames + 9'd1;
|
||||
end
|
||||
end else begin
|
||||
gd_frames <= gd_frames;
|
||||
bd_frames <= bd_frames;
|
||||
tl_frames <= tl_frames;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CNU_3din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CNU_3din
|
||||
#(parameter WIDTH = 4'd8)(
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din02_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din03_VN_RU, //变量节点信息输入
|
||||
|
||||
output reg [WIDTH-1:0] dout01_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout02_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout03_RU=8'd0 //更新输出
|
||||
);//输出相对输入延时9个clk
|
||||
|
||||
reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0;
|
||||
reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0;
|
||||
reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//求输入数据的绝对值过程
|
||||
if(din01_VN_RU[WIDTH-1]) abs01 <= ~din01_VN_RU + 8'd1;else abs01 <= din01_VN_RU;
|
||||
if(din02_VN_RU[WIDTH-1]) abs02 <= ~din02_VN_RU + 8'd1;else abs02 <= din02_VN_RU;
|
||||
if(din03_VN_RU[WIDTH-1]) abs03 <= ~din03_VN_RU + 8'd1;else abs03 <= din03_VN_RU;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
abs01_reg0 <= abs01; abs01_reg1 <= abs01_reg0;
|
||||
abs02_reg0 <= abs02; abs02_reg1 <= abs02_reg0;
|
||||
abs03_reg0 <= abs03; abs03_reg1 <= abs03_reg0;
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] min_level_1_01=8'd0,min_level_1_02=8'd0;
|
||||
reg [WIDTH-1:0] min_level_2_01=8'd0,min_level_2_02=8'd0;
|
||||
always @ (posedge clk) begin//第1级分类，两两一组将最小及次小值分开
|
||||
min_level_1_01 <= (abs01 < abs02) ? abs01:abs02;
|
||||
min_level_1_02 <= (abs01 < abs02) ? abs02:abs01;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
min_level_2_01 <= (abs03_reg0<min_level_1_01) ? abs03_reg0:min_level_1_01;
|
||||
min_level_2_02 <= (abs03_reg0<min_level_1_01) ? min_level_1_01:((abs03_reg0<min_level_1_02)? abs03_reg0 : min_level_1_02);
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] abs01_update=8'd0,abs02_update=8'd0,abs03_update=8'd0;
|
||||
always @ (posedge clk) begin//各绝对值的最小值及次小值更新
|
||||
abs01_update <= (abs01_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
abs02_update <= (abs02_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
abs03_update <= (abs03_reg1==min_level_2_01) ? min_level_2_02 : min_level_2_01;
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] dout_abs_NF01,dout_abs_NF02,dout_abs_NF03;
|
||||
//*****对更新后的非负数修正，系数为0.8125
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(dout_abs_NF01));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(dout_abs_NF02));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(dout_abs_NF03));
|
||||
|
||||
|
||||
reg [2:0] sgn=3'd0,sgn_reg0=3'd0;
|
||||
always @ (posedge clk) begin//求输入数据的符号位及其流水延时过程
|
||||
sgn[2:0] <= {din01_VN_RU[WIDTH-1],din02_VN_RU[WIDTH-1],din03_VN_RU[WIDTH-1]};
|
||||
sgn_reg0 <= sgn;
|
||||
end
|
||||
|
||||
reg xor_level_1_01=1'd0;
|
||||
always @ (posedge clk) begin//求所有符号位异或和的过程
|
||||
xor_level_1_01 <= sgn[0] ^ sgn[1] ^ sgn[2];
|
||||
end
|
||||
|
||||
reg [2:0] sgn_update=3'd0,sgn_update_reg0=3'd0,sgn_update_reg1=3'd0,sgn_update_reg2=3'd0,sgn_update_reg3=3'd0;
|
||||
always @ (posedge clk) begin //更新所有符号位及结果流水延时过程
|
||||
sgn_update[2:0] <= sgn_reg0^{3{xor_level_1_01}};
|
||||
sgn_update_reg0 <= sgn_update;
|
||||
sgn_update_reg1 <= sgn_update_reg0;
|
||||
sgn_update_reg2 <= sgn_update_reg1;
|
||||
sgn_update_reg3 <= sgn_update_reg2;
|
||||
end
|
||||
reg [WIDTH-1:0] dout01_RU_temp=8'd0,dout02_RU_temp=8'd0,dout03_RU_temp=8'd0;
|
||||
always @ (posedge clk) begin //计算最终更新结果的过程（符号位+绝对值）
|
||||
dout01_RU_temp <= (sgn_update_reg3[2]) ? {sgn_update_reg3[2],~dout_abs_NF01[WIDTH-2:0]+8'd1} : {sgn_update_reg3[2],dout_abs_NF01[WIDTH-2:0]};
|
||||
dout02_RU_temp <= (sgn_update_reg3[1]) ? {sgn_update_reg3[1],~dout_abs_NF02[WIDTH-2:0]+8'd1} : {sgn_update_reg3[1],dout_abs_NF02[WIDTH-2:0]};
|
||||
dout03_RU_temp <= (sgn_update_reg3[0]) ? {sgn_update_reg3[0],~dout_abs_NF03[WIDTH-2:0]+8'd1} : {sgn_update_reg3[0],dout_abs_NF03[WIDTH-2:0]};
|
||||
|
||||
dout01_RU <= dout01_RU_temp;
|
||||
dout02_RU <= dout02_RU_temp;
|
||||
dout03_RU <= dout03_RU_temp;
|
||||
end
|
||||
endmodule
|
||||
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CNU_6din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
module CNU_6din
|
||||
#(parameter WIDTH = 4'd8)
|
||||
(//输入数据个数为10的行更新模块，包括符号更新
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din02_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din03_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din04_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din05_VN_RU, //变量节点信息输入
|
||||
input [WIDTH-1:0] din06_VN_RU, //变量节点信息输入
|
||||
|
||||
output reg [WIDTH-1:0] dout01_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout02_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout03_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout04_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout05_RU=8'd0, //更新输出
|
||||
output reg [WIDTH-1:0] dout06_RU=8'd0 //更新输出
|
||||
); //输出相对输入延时9个clk
|
||||
reg [WIDTH-1:0] abs01=8'd0,abs01_reg0=8'd0,abs01_reg1=8'd0,abs01_reg2=8'd0,min_level_1_01=8'd0;
|
||||
reg [WIDTH-1:0] abs02=8'd0,abs02_reg0=8'd0,abs02_reg1=8'd0,abs02_reg2=8'd0,min_level_1_02=8'd0;
|
||||
reg [WIDTH-1:0] abs03=8'd0,abs03_reg0=8'd0,abs03_reg1=8'd0,abs03_reg2=8'd0,min_level_1_03=8'd0;
|
||||
reg [WIDTH-1:0] abs04=8'd0,abs04_reg0=8'd0,abs04_reg1=8'd0,abs04_reg2=8'd0,min_level_1_04=8'd0;
|
||||
reg [WIDTH-1:0] abs05=8'd0,abs05_reg0=8'd0,abs05_reg1=8'd0,abs05_reg2=8'd0,min_level_1_05=8'd0;
|
||||
reg [WIDTH-1:0] abs06=8'd0,abs06_reg0=8'd0,abs06_reg1=8'd0,abs06_reg2=8'd0,min_level_1_06=8'd0;
|
||||
|
||||
wire [WIDTH-1:0] min_level_2_01,min_level_2_02,min_level_3_01,min_level_3_02;
|
||||
|
||||
always @ (posedge clk) begin//求输入数据的绝对值过程
|
||||
if(din01_VN_RU[WIDTH-1]) abs01 <= ~din01_VN_RU + 8'd1;else abs01 <= din01_VN_RU;
|
||||
if(din02_VN_RU[WIDTH-1]) abs02 <= ~din02_VN_RU + 8'd1;else abs02 <= din02_VN_RU;
|
||||
if(din03_VN_RU[WIDTH-1]) abs03 <= ~din03_VN_RU + 8'd1;else abs03 <= din03_VN_RU;
|
||||
if(din04_VN_RU[WIDTH-1]) abs04 <= ~din04_VN_RU + 8'd1;else abs04 <= din04_VN_RU;
|
||||
if(din05_VN_RU[WIDTH-1]) abs05 <= ~din05_VN_RU + 8'd1;else abs05 <= din05_VN_RU;
|
||||
if(din06_VN_RU[WIDTH-1]) abs06 <= ~din06_VN_RU + 8'd1;else abs06 <= din06_VN_RU;
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk) begin//对绝对值流水延时
|
||||
abs01_reg0 <= abs01; abs01_reg1 <= abs01_reg0; abs01_reg2 <= abs01_reg1;
|
||||
abs02_reg0 <= abs02; abs02_reg1 <= abs02_reg0; abs02_reg2 <= abs02_reg1;
|
||||
abs03_reg0 <= abs03; abs03_reg1 <= abs03_reg0; abs03_reg2 <= abs03_reg1;
|
||||
abs04_reg0 <= abs04; abs04_reg1 <= abs04_reg0; abs04_reg2 <= abs04_reg1;
|
||||
abs05_reg0 <= abs05; abs05_reg1 <= abs05_reg0; abs05_reg2 <= abs05_reg1;
|
||||
abs06_reg0 <= abs06; abs06_reg1 <= abs06_reg0; abs06_reg2 <= abs06_reg1;
|
||||
|
||||
end
|
||||
|
||||
reg [WIDTH-1:0] min_level_1_05_reg0=8'd0,min_level_1_06_reg0=8'd0;
|
||||
always @ (posedge clk) begin
|
||||
min_level_1_05_reg0 <= min_level_1_05;
|
||||
min_level_1_06_reg0 <= min_level_1_06;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//第1级分类，两两一组将最小及次小值分开
|
||||
min_level_1_01 <= (abs01<abs02) ? abs01 : abs02; min_level_1_02 <= (abs01<abs02) ? abs02 : abs01;
|
||||
min_level_1_03 <= (abs03<abs04) ? abs03 : abs04; min_level_1_04 <= (abs03<abs04) ? abs04 : abs03;
|
||||
min_level_1_05 <= (abs05<abs06) ? abs05 : abs06; min_level_1_06 <= (abs05<abs06) ? abs06 : abs05;
|
||||
end
|
||||
abs_min_4din #(.WIDTH(WIDTH))inst_4din_level_1_01 (.clk(clk),.din01(min_level_1_01),.din02(min_level_1_02),.din03(min_level_1_03),.din04(min_level_1_04),.dout_min(min_level_2_01),.dout_sec(min_level_2_02));
|
||||
abs_min_4din #(.WIDTH(WIDTH))inst_4din_level_2_01 (.clk(clk),.din01(min_level_1_05_reg0),.din02(min_level_1_06_reg0),.din03(min_level_2_01),.din04(min_level_2_02),.dout_min(min_level_3_01),.dout_sec(min_level_3_02));
|
||||
|
||||
reg [WIDTH-1:0] abs01_update=8'd0;
|
||||
reg [WIDTH-1:0] abs02_update=8'd0;
|
||||
reg [WIDTH-1:0] abs03_update=8'd0;
|
||||
reg [WIDTH-1:0] abs04_update=8'd0;
|
||||
reg [WIDTH-1:0] abs05_update=8'd0;
|
||||
reg [WIDTH-1:0] abs06_update=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//各绝对值的最小值及次小值更新
|
||||
abs01_update <= (abs01_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs02_update <= (abs02_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs03_update <= (abs03_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs04_update <= (abs04_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs05_update <= (abs05_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
abs06_update <= (abs06_reg2==min_level_3_01) ? min_level_3_02 : min_level_3_01;
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] dout_abs_NF01;
|
||||
wire [WIDTH-1:0] dout_abs_NF02;
|
||||
wire [WIDTH-1:0] dout_abs_NF03;
|
||||
wire [WIDTH-1:0] dout_abs_NF04;
|
||||
wire [WIDTH-1:0] dout_abs_NF05;
|
||||
wire [WIDTH-1:0] dout_abs_NF06;
|
||||
|
||||
//*****对更新后的非负数修正，系数为0.8125
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF01 (.clk(clk),.din_NF(abs01_update),.dout_NF(dout_abs_NF01));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF02 (.clk(clk),.din_NF(abs02_update),.dout_NF(dout_abs_NF02));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF03 (.clk(clk),.din_NF(abs03_update),.dout_NF(dout_abs_NF03));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF04 (.clk(clk),.din_NF(abs04_update),.dout_NF(dout_abs_NF04));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF05 (.clk(clk),.din_NF(abs05_update),.dout_NF(dout_abs_NF05));
|
||||
Normalization_Factor_0_8125 #(.WIDTH(WIDTH)) NF06 (.clk(clk),.din_NF(abs06_update),.dout_NF(dout_abs_NF06));
|
||||
|
||||
reg [5:0] sgn=6'd0,sgn_reg0=6'd0,sgn_reg1=6'd0;
|
||||
always @ (posedge clk) begin//求输入数据的符号位及其流水延时过程
|
||||
sgn[5:0] <= {din01_VN_RU[WIDTH-1],din02_VN_RU[WIDTH-1],din03_VN_RU[WIDTH-1],din04_VN_RU[WIDTH-1],din05_VN_RU[WIDTH-1],din06_VN_RU[WIDTH-1]};
|
||||
sgn_reg0 <= sgn;
|
||||
sgn_reg1 <= sgn_reg0;
|
||||
end
|
||||
|
||||
reg xor_level_1_01=1'd0,xor_level_1_02=1'd0,xor_level_2_01=1'd0;
|
||||
always @ (posedge clk) begin//求所有符号位异或和的过程
|
||||
xor_level_1_01 <= sgn[0] ^ sgn[1] ^ sgn[2];
|
||||
xor_level_1_02 <= sgn[3] ^ sgn[4] ^ sgn[5];
|
||||
xor_level_2_01 <= xor_level_1_01 ^ xor_level_1_02;
|
||||
end
|
||||
|
||||
reg [5:0] sgn_update=6'd0,sgn_update_reg0=6'd0,sgn_update_reg1=6'd0,sgn_update_reg2=6'd0,sgn_update_reg3=6'd0;
|
||||
always @ (posedge clk) begin //更新所有符号位及结果流水延时过程
|
||||
sgn_update[5:0] <= sgn_reg1^{6{xor_level_2_01}};
|
||||
sgn_update_reg0 <= sgn_update;
|
||||
sgn_update_reg1 <= sgn_update_reg0;
|
||||
sgn_update_reg2 <= sgn_update_reg1;
|
||||
sgn_update_reg3 <= sgn_update_reg2;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin //计算最终更新结果的过程（符号位+绝对值）
|
||||
dout01_RU <= (sgn_update_reg3[5]) ? {sgn_update_reg3[5],~dout_abs_NF01[WIDTH-2:0]+8'd1} : {sgn_update_reg3[5],dout_abs_NF01[WIDTH-2:0]};
|
||||
dout02_RU <= (sgn_update_reg3[4]) ? {sgn_update_reg3[4],~dout_abs_NF02[WIDTH-2:0]+8'd1} : {sgn_update_reg3[4],dout_abs_NF02[WIDTH-2:0]};
|
||||
dout03_RU <= (sgn_update_reg3[3]) ? {sgn_update_reg3[3],~dout_abs_NF03[WIDTH-2:0]+8'd1} : {sgn_update_reg3[3],dout_abs_NF03[WIDTH-2:0]};
|
||||
dout04_RU <= (sgn_update_reg3[2]) ? {sgn_update_reg3[2],~dout_abs_NF04[WIDTH-2:0]+8'd1} : {sgn_update_reg3[2],dout_abs_NF04[WIDTH-2:0]};
|
||||
dout05_RU <= (sgn_update_reg3[1]) ? {sgn_update_reg3[1],~dout_abs_NF05[WIDTH-2:0]+8'd1} : {sgn_update_reg3[1],dout_abs_NF05[WIDTH-2:0]};
|
||||
dout06_RU <= (sgn_update_reg3[0]) ? {sgn_update_reg3[0],~dout_abs_NF06[WIDTH-2:0]+8'd1} : {sgn_update_reg3[0],dout_abs_NF06[WIDTH-2:0]};
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
+426
@@ -0,0 +1,426 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: CN_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module CN_PRO
|
||||
#(
|
||||
parameter WIDTH = 4'd8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_CN,
|
||||
input start_CN, //模块启动信号，高脉冲
|
||||
|
||||
//VN数据输出，H阵第１行
|
||||
input [WIDTH-1:0] VN1_dout_01_00,
|
||||
input [WIDTH-1:0] VN1_dout_02_00, //后面的00代表H阵原模图的IM
|
||||
input [WIDTH-1:0] VN1_dout_02_01, //后面的01代表H阵原模图的II1
|
||||
//VN数据输出，H阵第２行
|
||||
input [WIDTH-1:0] VN2_dout_01_00,
|
||||
input [WIDTH-1:0] VN2_dout_02_00,
|
||||
input [WIDTH-1:0] VN2_dout_03_00,
|
||||
input [WIDTH-1:0] VN2_dout_04_02, //后面的02代表H阵原模图的II2
|
||||
input [WIDTH-1:0] VN2_dout_04_03, //后面的03代表H阵原模图的II3
|
||||
input [WIDTH-1:0] VN2_dout_04_04, //后面的04代表H阵原模图的II4
|
||||
//VN数据输出，H阵第３行
|
||||
input [WIDTH-1:0] VN3_dout_01_00,
|
||||
input [WIDTH-1:0] VN3_dout_02_05, //后面的05代表H阵原模图的II5
|
||||
input [WIDTH-1:0] VN3_dout_02_06, //后面的06代表H阵原模图的II6
|
||||
input [WIDTH-1:0] VN3_dout_03_07, //后面的07代表H阵原模图的II7
|
||||
input [WIDTH-1:0] VN3_dout_03_08, //后面的08代表H阵原模图的II8
|
||||
input [WIDTH-1:0] VN3_dout_04_00,
|
||||
|
||||
//VN读地址，H阵第１行
|
||||
output reg [8:0] VN1_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] VN1_addr_rd_02_00=10'd1023,
|
||||
output reg [9:0] VN1_addr_rd_02_01=10'd511,
|
||||
//VN读地址，H阵第２行
|
||||
output reg [8:0] VN2_addr_rd_01_00=9'd511,
|
||||
output reg [8:0] VN2_addr_rd_02_00=9'd511,
|
||||
output reg [8:0] VN2_addr_rd_03_00=9'd511,
|
||||
output reg [9:0] VN2_addr_rd_04_02=10'd1023,
|
||||
output reg [9:0] VN2_addr_rd_04_03=10'd511,
|
||||
output reg [8:0] VN2_addr_rd_04_04=9'd511,
|
||||
//VN读地址，H阵第３行
|
||||
output reg [8:0] VN3_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] VN3_addr_rd_02_05=10'd1023,
|
||||
output reg [9:0] VN3_addr_rd_02_06=10'd511,
|
||||
output reg [9:0] VN3_addr_rd_03_07=10'd1023,
|
||||
output reg [9:0] VN3_addr_rd_03_08=10'd511,
|
||||
output reg [8:0] VN3_addr_rd_04_00=9'd511,
|
||||
|
||||
//CN写使能
|
||||
output reg [0:0] CN_wea=1'd0,
|
||||
|
||||
//CN写地址，H阵第１行
|
||||
output reg [8:0] CN1_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] CN1_addr_wr_02_00=10'd1023,
|
||||
output reg [9:0] CN1_addr_wr_02_01=10'd511,
|
||||
|
||||
//CN写地址，H阵第２行
|
||||
output reg [8:0] CN2_addr_wr_01_00=9'd511,
|
||||
output reg [8:0] CN2_addr_wr_02_00=9'd511,
|
||||
output reg [8:0] CN2_addr_wr_03_00=9'd511,
|
||||
output reg [9:0] CN2_addr_wr_04_02=10'd1023,
|
||||
output reg [9:0] CN2_addr_wr_04_03=10'd511,
|
||||
output reg [8:0] CN2_addr_wr_04_04=9'd511,
|
||||
|
||||
//CN写地址，H阵第３行
|
||||
output reg [8:0] CN3_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] CN3_addr_wr_02_05=10'd1023,
|
||||
output reg [9:0] CN3_addr_wr_02_06=10'd511,
|
||||
output reg [9:0] CN3_addr_wr_03_07=10'd1023,
|
||||
output reg [9:0] CN3_addr_wr_03_08=10'd511,
|
||||
output reg [8:0] CN3_addr_wr_04_00=9'd511,
|
||||
|
||||
|
||||
//CN写数据，H阵第１行
|
||||
output reg [WIDTH-1:0] CN1_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN1_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN1_din_02_01=8'd0,
|
||||
|
||||
//CN写数据，H阵第２行
|
||||
output reg [WIDTH-1:0] CN2_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_03_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_02=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_03=8'd0,
|
||||
output reg [WIDTH-1:0] CN2_din_04_04=8'd0,
|
||||
|
||||
//CN写数据，H阵第３行
|
||||
output reg [WIDTH-1:0] CN3_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_02_05=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_02_06=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_03_07=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_03_08=8'd0,
|
||||
output reg [WIDTH-1:0] CN3_din_04_00=8'd0,
|
||||
|
||||
output end_CN //模块结束标志，高脉冲
|
||||
);
|
||||
|
||||
reg [10:0] cnt_CN=11'd0;
|
||||
reg flag_CN=1'd0;
|
||||
// 产生该模块的计数基准
|
||||
always @ (posedge clk) begin
|
||||
if(rst_CN) begin
|
||||
cnt_CN <= 11'd0;
|
||||
flag_CN <= 1'b0;
|
||||
end else begin
|
||||
if(start_CN) begin
|
||||
flag_CN <= 1'b1;
|
||||
cnt_CN <= 11'd0;
|
||||
end else begin
|
||||
if(flag_CN) begin
|
||||
if(cnt_CN<11'd560)begin
|
||||
flag_CN <= flag_CN;
|
||||
cnt_CN <= cnt_CN + 11'd1;
|
||||
end else begin
|
||||
cnt_CN <= cnt_CN;
|
||||
flag_CN<= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_CN <= cnt_CN;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 对VN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
VN1_addr_rd_01_00 <= 9'd511;
|
||||
VN1_addr_rd_02_00 <= 10'd1023;
|
||||
VN2_addr_rd_01_00 <= 9'd511;
|
||||
VN2_addr_rd_02_00 <= 9'd511;
|
||||
VN2_addr_rd_03_00 <= 9'd511;
|
||||
VN3_addr_rd_01_00 <= 9'd511;
|
||||
VN3_addr_rd_04_00 <= 9'd511;
|
||||
|
||||
VN1_addr_rd_02_01 <= 10'd511;
|
||||
VN2_addr_rd_04_02 <= 10'd1023;
|
||||
VN2_addr_rd_04_03 <= 10'd511;
|
||||
VN2_addr_rd_04_04 <= 9'd511;
|
||||
VN3_addr_rd_02_05 <= 10'd1023;
|
||||
VN3_addr_rd_02_06 <= 10'd511;
|
||||
VN3_addr_rd_03_07 <= 10'd1023;
|
||||
VN3_addr_rd_03_08 <= 10'd511;
|
||||
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 && cnt_CN <= 11'd512) begin
|
||||
VN1_addr_rd_01_00 <= VN1_addr_rd_01_00 + 9'd1;
|
||||
VN1_addr_rd_02_00 <= VN1_addr_rd_02_00 + 9'd1;
|
||||
VN2_addr_rd_01_00 <= VN2_addr_rd_01_00 + 9'd1;
|
||||
VN2_addr_rd_02_00 <= VN2_addr_rd_02_00 + 9'd1;
|
||||
VN2_addr_rd_03_00 <= VN2_addr_rd_03_00 + 9'd1;
|
||||
VN3_addr_rd_01_00 <= VN3_addr_rd_01_00 + 9'd1;
|
||||
VN3_addr_rd_04_00 <= VN3_addr_rd_04_00 + 9'd1;
|
||||
VN1_addr_rd_02_01 <= VN1_addr_rd_02_01 + 10'd1;
|
||||
VN2_addr_rd_04_02 <= VN2_addr_rd_04_02 + 10'd1;
|
||||
VN2_addr_rd_04_03 <= VN2_addr_rd_04_03 + 10'd1;
|
||||
VN2_addr_rd_04_04 <= VN2_addr_rd_04_04 + 9'd1;
|
||||
VN3_addr_rd_02_05 <= VN3_addr_rd_02_05 + 10'd1;
|
||||
VN3_addr_rd_02_06 <= VN3_addr_rd_02_06 + 10'd1;
|
||||
VN3_addr_rd_03_07 <= VN3_addr_rd_03_07 + 10'd1;
|
||||
VN3_addr_rd_03_08 <= VN3_addr_rd_03_08 + 10'd1;
|
||||
end else begin
|
||||
VN1_addr_rd_01_00 <= 9'd511;
|
||||
VN1_addr_rd_02_00 <= 10'd1023;
|
||||
VN2_addr_rd_01_00 <= 9'd511;
|
||||
VN2_addr_rd_02_00 <= 9'd511;
|
||||
VN2_addr_rd_03_00 <= 9'd511;
|
||||
VN3_addr_rd_01_00 <= 9'd511;
|
||||
VN3_addr_rd_04_00 <= 9'd511;
|
||||
VN1_addr_rd_02_01 <= 10'd511;
|
||||
VN2_addr_rd_04_02 <= 10'd1023;
|
||||
VN2_addr_rd_04_03 <= 10'd511;
|
||||
VN2_addr_rd_04_04 <= 9'd511;
|
||||
VN3_addr_rd_02_05 <= 10'd1023;
|
||||
VN3_addr_rd_02_06 <= 10'd511;
|
||||
VN3_addr_rd_03_07 <= 10'd1023;
|
||||
VN3_addr_rd_03_08 <= 10'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] din01_VN_RU01;
|
||||
wire [WIDTH-1:0] din02_VN_RU01;
|
||||
wire [WIDTH-1:0] din03_VN_RU01;
|
||||
wire [WIDTH-1:0] dout01_RU01 ;
|
||||
wire [WIDTH-1:0] dout02_RU01 ;
|
||||
wire [WIDTH-1:0] dout03_RU01 ;
|
||||
wire [WIDTH-1:0] din01_VN_RU02;
|
||||
wire [WIDTH-1:0] din02_VN_RU02;
|
||||
wire [WIDTH-1:0] din03_VN_RU02;
|
||||
wire [WIDTH-1:0] din04_VN_RU02;
|
||||
wire [WIDTH-1:0] din05_VN_RU02;
|
||||
wire [WIDTH-1:0] din06_VN_RU02;
|
||||
wire [WIDTH-1:0] dout01_RU02 ;
|
||||
wire [WIDTH-1:0] dout02_RU02 ;
|
||||
wire [WIDTH-1:0] dout03_RU02 ;
|
||||
wire [WIDTH-1:0] dout04_RU02 ;
|
||||
wire [WIDTH-1:0] dout05_RU02 ;
|
||||
wire [WIDTH-1:0] dout06_RU02 ;
|
||||
wire [WIDTH-1:0] din01_VN_RU03;
|
||||
wire [WIDTH-1:0] din02_VN_RU03;
|
||||
wire [WIDTH-1:0] din03_VN_RU03;
|
||||
wire [WIDTH-1:0] din04_VN_RU03;
|
||||
wire [WIDTH-1:0] din05_VN_RU03;
|
||||
wire [WIDTH-1:0] din06_VN_RU03;
|
||||
wire [WIDTH-1:0] dout01_RU03 ;
|
||||
wire [WIDTH-1:0] dout02_RU03 ;
|
||||
wire [WIDTH-1:0] dout03_RU03 ;
|
||||
wire [WIDTH-1:0] dout04_RU03 ;
|
||||
wire [WIDTH-1:0] dout05_RU03 ;
|
||||
wire [WIDTH-1:0] dout06_RU03 ;
|
||||
|
||||
|
||||
|
||||
CNU_3din #(.WIDTH(WIDTH)) RU_01 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU01),
|
||||
.din02_VN_RU(din02_VN_RU01),
|
||||
.din03_VN_RU(din03_VN_RU01),
|
||||
.dout01_RU(dout01_RU01),
|
||||
.dout02_RU(dout02_RU01),
|
||||
.dout03_RU(dout03_RU01)
|
||||
);
|
||||
|
||||
CNU_6din #(.WIDTH(WIDTH)) RU_02 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU02),
|
||||
.din02_VN_RU(din02_VN_RU02),
|
||||
.din03_VN_RU(din03_VN_RU02),
|
||||
.din04_VN_RU(din04_VN_RU02),
|
||||
.din05_VN_RU(din05_VN_RU02),
|
||||
.din06_VN_RU(din06_VN_RU02),
|
||||
.dout01_RU(dout01_RU02),
|
||||
.dout02_RU(dout02_RU02),
|
||||
.dout03_RU(dout03_RU02),
|
||||
.dout04_RU(dout04_RU02),
|
||||
.dout05_RU(dout05_RU02),
|
||||
.dout06_RU(dout06_RU02)
|
||||
);
|
||||
|
||||
CNU_6din #(.WIDTH(WIDTH)) RU_03 (
|
||||
.clk(clk),
|
||||
.din01_VN_RU(din01_VN_RU03),
|
||||
.din02_VN_RU(din02_VN_RU03),
|
||||
.din03_VN_RU(din03_VN_RU03),
|
||||
.din04_VN_RU(din04_VN_RU03),
|
||||
.din05_VN_RU(din05_VN_RU03),
|
||||
.din06_VN_RU(din06_VN_RU03),
|
||||
.dout01_RU(dout01_RU03),
|
||||
.dout02_RU(dout02_RU03),
|
||||
.dout03_RU(dout03_RU03),
|
||||
.dout04_RU(dout04_RU03),
|
||||
.dout05_RU(dout05_RU03),
|
||||
.dout06_RU(dout06_RU03)
|
||||
);
|
||||
// 设置读操作的时延
|
||||
parameter DELAY_RD = 11'd6;
|
||||
// RU模块的输入
|
||||
assign din01_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_00 : 8'd0;
|
||||
assign din03_VN_RU01 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN1_dout_02_01 : 8'd0;
|
||||
assign din01_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_02_00 : 8'd0;
|
||||
assign din03_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_03_00 : 8'd0;
|
||||
assign din04_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_02 : 8'd0;
|
||||
assign din05_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_03 : 8'd0;
|
||||
assign din06_VN_RU02 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN2_dout_04_04 : 8'd0;
|
||||
assign din01_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_01_00 : 8'd0;
|
||||
assign din02_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_05 : 8'd0;
|
||||
assign din03_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_02_06 : 8'd0;
|
||||
assign din04_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_07 : 8'd0;
|
||||
assign din05_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_03_08 : 8'd0;
|
||||
assign din06_VN_RU03 = (cnt_CN >= 11'd1+DELAY_RD && cnt_CN<=11'd512+DELAY_RD) ? VN3_dout_04_00 : 8'd0;
|
||||
|
||||
// 设置写操作的时延
|
||||
parameter DELAY_WR = 11'd15;
|
||||
|
||||
// 控制CN的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_CN) begin
|
||||
CN_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR)
|
||||
CN_wea <= 1'd1;
|
||||
else
|
||||
CN_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制CN存储的写地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
CN1_addr_wr_01_00 <= 9'd511;
|
||||
CN1_addr_wr_02_00 <= 10'd1023;
|
||||
CN2_addr_wr_01_00 <= 9'd511;
|
||||
CN2_addr_wr_02_00 <= 9'd511;
|
||||
CN2_addr_wr_03_00 <= 9'd511;
|
||||
CN3_addr_wr_01_00 <= 9'd511;
|
||||
CN3_addr_wr_04_00 <= 9'd511;
|
||||
|
||||
CN1_addr_wr_02_01 <= 10'd511;
|
||||
CN2_addr_wr_04_02 <= 10'd1023;
|
||||
CN2_addr_wr_04_03 <= 10'd511;
|
||||
CN2_addr_wr_04_04 <= 9'd511;
|
||||
CN3_addr_wr_02_05 <= 10'd1023;
|
||||
CN3_addr_wr_02_06 <= 10'd511;
|
||||
CN3_addr_wr_03_07 <= 10'd1023;
|
||||
CN3_addr_wr_03_08 <= 10'd511;
|
||||
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
|
||||
CN1_addr_wr_01_00 <= CN1_addr_wr_01_00 + 9'd1;
|
||||
CN1_addr_wr_02_00 <= CN1_addr_wr_02_00 + 9'd1;
|
||||
CN2_addr_wr_01_00 <= CN2_addr_wr_01_00 + 9'd1;
|
||||
CN2_addr_wr_02_00 <= CN2_addr_wr_02_00 + 9'd1;
|
||||
CN2_addr_wr_03_00 <= CN2_addr_wr_03_00 + 9'd1;
|
||||
CN3_addr_wr_01_00 <= CN3_addr_wr_01_00 + 9'd1;
|
||||
CN3_addr_wr_04_00 <= CN3_addr_wr_04_00 + 9'd1;
|
||||
CN1_addr_wr_02_01 <= CN1_addr_wr_02_01 + 10'd1;
|
||||
CN2_addr_wr_04_02 <= CN2_addr_wr_04_02 + 10'd1;
|
||||
CN2_addr_wr_04_03 <= CN2_addr_wr_04_03 + 10'd1;
|
||||
CN2_addr_wr_04_04 <= CN2_addr_wr_04_04 + 9'd1;
|
||||
CN3_addr_wr_02_05 <= CN3_addr_wr_02_05 + 10'd1;
|
||||
CN3_addr_wr_02_06 <= CN3_addr_wr_02_06 + 10'd1;
|
||||
CN3_addr_wr_03_07 <= CN3_addr_wr_03_07 + 10'd1;
|
||||
CN3_addr_wr_03_08 <= CN3_addr_wr_03_08 + 10'd1;
|
||||
end else begin
|
||||
CN1_addr_wr_01_00 <= 9'd511;
|
||||
CN1_addr_wr_02_00 <= 10'd1023;
|
||||
CN2_addr_wr_01_00 <= 9'd511;
|
||||
CN2_addr_wr_02_00 <= 9'd511;
|
||||
CN2_addr_wr_03_00 <= 9'd511;
|
||||
CN3_addr_wr_01_00 <= 9'd511;
|
||||
CN3_addr_wr_04_00 <= 9'd511;
|
||||
CN1_addr_wr_02_01 <= 10'd511;
|
||||
CN2_addr_wr_04_02 <= 10'd1023;
|
||||
CN2_addr_wr_04_03 <= 10'd511;
|
||||
CN2_addr_wr_04_04 <= 9'd511;
|
||||
CN3_addr_wr_02_05 <= 10'd1023;
|
||||
CN3_addr_wr_02_06 <= 10'd511;
|
||||
CN3_addr_wr_03_07 <= 10'd1023;
|
||||
CN3_addr_wr_03_08 <= 10'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制CN的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_CN) begin
|
||||
CN1_din_01_00 <= 8'd0;
|
||||
CN1_din_02_00 <= 8'd0;
|
||||
CN2_din_01_00 <= 8'd0;
|
||||
CN2_din_02_00 <= 8'd0;
|
||||
CN2_din_03_00 <= 8'd0;
|
||||
CN3_din_01_00 <= 8'd0;
|
||||
CN3_din_04_00 <= 8'd0;
|
||||
CN1_din_02_01 <= 8'd0;
|
||||
CN2_din_04_02 <= 8'd0;
|
||||
CN2_din_04_03 <= 8'd0;
|
||||
CN2_din_04_04 <= 8'd0;
|
||||
CN3_din_02_05 <= 8'd0;
|
||||
CN3_din_02_06 <= 8'd0;
|
||||
CN3_din_03_07 <= 8'd0;
|
||||
CN3_din_03_08 <= 8'd0;
|
||||
end else begin
|
||||
if (cnt_CN >= 11'd1 + DELAY_WR && cnt_CN <= 11'd512 + DELAY_WR) begin
|
||||
CN1_din_01_00 <= dout01_RU01;
|
||||
CN1_din_02_00 <= dout02_RU01;
|
||||
CN2_din_01_00 <= dout01_RU02;
|
||||
CN2_din_02_00 <= dout02_RU02;
|
||||
CN2_din_03_00 <= dout03_RU02;
|
||||
CN3_din_01_00 <= dout01_RU03;
|
||||
CN3_din_04_00 <= dout06_RU03;
|
||||
CN1_din_02_01 <= dout03_RU01;
|
||||
CN2_din_04_02 <= dout04_RU02;
|
||||
CN2_din_04_03 <= dout05_RU02;
|
||||
CN2_din_04_04 <= dout06_RU02;
|
||||
CN3_din_02_05 <= dout02_RU03;
|
||||
CN3_din_02_06 <= dout03_RU03;
|
||||
CN3_din_03_07 <= dout04_RU03;
|
||||
CN3_din_03_08 <= dout05_RU03;
|
||||
end else begin
|
||||
CN1_din_01_00 <= 8'd0;
|
||||
CN1_din_02_00 <= 8'd0;
|
||||
CN2_din_01_00 <= 8'd0;
|
||||
CN2_din_02_00 <= 8'd0;
|
||||
CN2_din_03_00 <= 8'd0;
|
||||
CN3_din_01_00 <= 8'd0;
|
||||
CN3_din_04_00 <= 8'd0;
|
||||
CN1_din_02_01 <= 8'd0;
|
||||
CN2_din_04_02 <= 8'd0;
|
||||
CN2_din_04_03 <= 8'd0;
|
||||
CN2_din_04_04 <= 8'd0;
|
||||
CN3_din_02_05 <= 8'd0;
|
||||
CN3_din_02_06 <= 8'd0;
|
||||
CN3_din_03_07 <= 8'd0;
|
||||
CN3_din_03_08 <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//状态指示
|
||||
assign end_CN = (cnt_CN == 11'd512 + DELAY_WR + 11'd2) ? 1'd1 : 1'd0;
|
||||
endmodule
|
||||
|
||||
+1192
File diff suppressed because it is too large
Load Diff
+552
@@ -0,0 +1,552 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/08/18 16:40:38
|
||||
// Design Name:
|
||||
// Module Name: DAGC_v2
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module DAGC_v2 (
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input mgc1_rdy,
|
||||
input framesync_d0,
|
||||
|
||||
input [1:0] vio_powertest_h,
|
||||
input [1:0] vio_powertest_l,
|
||||
|
||||
input [9:0] matchfilterout_i,
|
||||
input [9:0] matchfilterout_q,
|
||||
|
||||
output reg [9:0] DAGC_out_i = 10'd0,
|
||||
output reg [9:0] DAGC_out_q = 10'd0,
|
||||
|
||||
//检测用
|
||||
output reg flag_agch = 1'd0,
|
||||
output reg flag_agcl = 1'd0,
|
||||
output reg flag_agc_power = 1'd0,
|
||||
output reg [12:0] agc_ref = 13'd0,
|
||||
output reg [12:0] agc_check = 13'd0,
|
||||
output reg dagc_rdy,
|
||||
output reg mgc_rdy,
|
||||
output reg rst_dagc
|
||||
);
|
||||
|
||||
|
||||
//近似求模值方法，做4096累积平均
|
||||
|
||||
//-------------------------------------数据缓存----------------------------//
|
||||
reg wea_1 = 1'd0;
|
||||
reg [11:0] addrin_1 = 12'd0;
|
||||
reg [ 9:0] din_1i = 10'd0;
|
||||
reg [11:0] addrout_1 = 12'd0;
|
||||
wire [ 9:0] dout_1i;
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------给数据、打缓存的状态机-------------------------------------//
|
||||
reg ND = 1'd0;
|
||||
reg [ 9:0] Din_I = 10'd0;
|
||||
reg [ 9:0] Din_Q = 10'd0;
|
||||
reg [ 5:0] cnt_50 = 6'd0;
|
||||
reg [ 2:0] state_storage = 3'd0;
|
||||
|
||||
|
||||
wire [ 9:0] mf_i;
|
||||
wire [ 9:0] mf_q;
|
||||
wire empty;
|
||||
wire full;
|
||||
reg rd_en = 1'b0;
|
||||
wire [13:0] data_count;
|
||||
fifo_dagc fifo_dagc (
|
||||
.clk (clk),
|
||||
.srst (rst),
|
||||
.din ({matchfilterout_q, matchfilterout_i}),
|
||||
.wr_en (mgc1_rdy),
|
||||
.full (empty),
|
||||
.rd_en (rd_en),
|
||||
.empty (full),
|
||||
.dout ({mf_q, mf_i}),
|
||||
.data_count(data_count)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
//-------------------------------------求近似模值的模块----------------------------//
|
||||
wire [10:0] Dout;
|
||||
wire [ 0:0] Rdy_abs;
|
||||
ApproxAbs_v2 ApproxAbs_v2_djy (
|
||||
.clk (clk),
|
||||
.ND (mgc1_rdy),
|
||||
.Din_I(matchfilterout_i),
|
||||
.Din_Q(matchfilterout_q),
|
||||
.Dout (Dout),
|
||||
.Rdy (Rdy_abs)
|
||||
);
|
||||
|
||||
reg framesync_d1;
|
||||
reg framesync_d2;
|
||||
reg framesync_d3;
|
||||
reg framesync_d4;
|
||||
reg framesync_d5;
|
||||
reg framesync;
|
||||
|
||||
always @(posedge clk) begin //(MXQ)必须加 posedge clk ,否则仿真有问题，内存溢出
|
||||
framesync_d1 <= framesync_d0; //与ApproxAbs_v2_djy同步
|
||||
framesync_d2 <= framesync_d1;
|
||||
framesync_d3 <= framesync_d2;
|
||||
framesync_d4 <= framesync_d3;
|
||||
framesync_d5 <= framesync_d4;
|
||||
framesync <= framesync_d5;
|
||||
end
|
||||
|
||||
|
||||
//-------------------------------------LUT----------------------------//
|
||||
reg [10:0] addr_lut = 11'd0;
|
||||
wire [13:0] dout_lut;
|
||||
DAGC_LUT_rom DAGC_LUT_rom (
|
||||
.clka (clk), // input clka
|
||||
.addra(addr_lut), // input [10 : 0] addra
|
||||
.douta(dout_lut) // output [13 : 0] douta
|
||||
);
|
||||
|
||||
reg dagc_rdy_d0;
|
||||
reg dagc_rdy_d1;
|
||||
reg dagc_rdy_d2;
|
||||
reg dagc_rdy_d3;
|
||||
reg dagc_rdy_d4;
|
||||
reg mgc_rdy_d0;
|
||||
reg mgc_rdy_d1;
|
||||
reg mgc_rdy_d2;
|
||||
reg mgc_rdy_d3;
|
||||
reg mgc_rdy_d4;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
dagc_rdy_d1 <= 1'b0;
|
||||
dagc_rdy_d2 <= 1'b0;
|
||||
dagc_rdy_d3 <= 1'b0;
|
||||
dagc_rdy_d4 <= 1'b0;
|
||||
dagc_rdy <= 1'b0;
|
||||
mgc_rdy_d1 <= 1'b0;
|
||||
mgc_rdy_d2 <= 1'b0;
|
||||
mgc_rdy_d3 <= 1'b0;
|
||||
mgc_rdy_d4 <= 1'b0;
|
||||
mgc_rdy <= 1'b0;
|
||||
|
||||
end
|
||||
else begin
|
||||
dagc_rdy_d1 <= dagc_rdy_d0;
|
||||
dagc_rdy_d2 <= dagc_rdy_d1;
|
||||
dagc_rdy_d3 <= dagc_rdy_d2;
|
||||
dagc_rdy_d4 <= dagc_rdy_d3;
|
||||
dagc_rdy <= dagc_rdy_d4;
|
||||
mgc_rdy_d1 <= mgc_rdy_d0;
|
||||
mgc_rdy_d2 <= mgc_rdy_d1;
|
||||
mgc_rdy_d3 <= mgc_rdy_d2;
|
||||
mgc_rdy_d4 <= mgc_rdy_d3;
|
||||
mgc_rdy <= mgc_rdy_d4;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
//-------------------------------------求均值、查表、给补偿指令的状态机----------------------------//
|
||||
reg [ 3:0] state_agc = 4'd0;
|
||||
reg [11:0] cnt_4096_3 = 12'd0;
|
||||
reg [22:0] agc_ref_temp = 23'd0;
|
||||
reg [14:0] agc_ref_h = 15'd0;
|
||||
reg [12:0] agc_ref_l = 13'd0;
|
||||
|
||||
reg flag_ram_1 = 1'd0;
|
||||
reg flag_ram_2 = 1'd0;
|
||||
reg [14:0] cnt_databag = 15'd0;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_agc <= 4'd0;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd0;
|
||||
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
flag_agc_power <= 1'd0;
|
||||
|
||||
agc_ref <= agc_ref;
|
||||
agc_ref_temp <= 23'd0;
|
||||
agc_check <= agc_check;
|
||||
agc_ref_h <= 15'd0;
|
||||
agc_ref_l <= 13'd0;
|
||||
|
||||
addr_lut <= 11'd0;
|
||||
flag_ram_1 <= 1'd0;
|
||||
flag_ram_2 <= 1'd0;
|
||||
dagc_rdy_d0 <= 1'b0;
|
||||
rd_en <= 1'b0;
|
||||
mgc_rdy_d0 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case (state_agc)
|
||||
4'd0: begin
|
||||
if (Rdy_abs) begin //状态0进入第一次估计
|
||||
state_agc <= 4'd1;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
cnt_4096_3 <= 12'd1;
|
||||
cnt_databag <= 15'd1;
|
||||
end
|
||||
else begin
|
||||
state_agc <= state_agc;
|
||||
agc_ref_temp <= 23'd0;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd0;
|
||||
end
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
flag_agc_power <= 1'd0;
|
||||
|
||||
agc_ref <= 13'd0;
|
||||
agc_check <= 13'd0;
|
||||
agc_ref_h <= 15'd0;
|
||||
agc_ref_l <= 13'd0;
|
||||
|
||||
addr_lut <= 11'd0;
|
||||
flag_ram_1 <= 1'd0;
|
||||
flag_ram_2 <= 1'd0;
|
||||
|
||||
end
|
||||
|
||||
4'd1: begin
|
||||
if (cnt_4096_3 == 12'd4095) begin
|
||||
state_agc <= 4'd2;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
else begin
|
||||
state_agc <= state_agc;
|
||||
cnt_4096_3 <= 12'd01 + cnt_4096_3;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
agc_ref_temp <= agc_ref_temp + {12'd0, Dout};
|
||||
flag_agc_power <= 1'd0;
|
||||
end
|
||||
|
||||
4'd2: begin
|
||||
if (framesync == 1'b1) begin //判断是否有帧同步如果有进入有效数据计算段
|
||||
state_agc <= 4'd3;
|
||||
end
|
||||
else begin
|
||||
state_agc <= 4'd10;
|
||||
end
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
agc_ref <= agc_ref_temp[22:10];
|
||||
agc_check <= agc_ref_temp[22:10];
|
||||
flag_agc_power <= 1'd1;
|
||||
|
||||
end
|
||||
|
||||
4'd3: begin
|
||||
if (cnt_databag == 15'd13695) begin
|
||||
cnt_databag <= 15'd0;
|
||||
state_agc <= 4'd4;
|
||||
cnt_4096_3 <= 12'd1;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
end
|
||||
else begin
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
state_agc <= state_agc;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
end
|
||||
flag_agc_power <= 1'd0;
|
||||
case (vio_powertest_h)
|
||||
2'd0: agc_ref_h <= {2'd0, agc_ref} + {4'd0, agc_ref[12:2]};
|
||||
2'd1: agc_ref_h <= {2'd0, agc_ref} + {3'd0, agc_ref[12:1]};
|
||||
2'd2: agc_ref_h <= {1'd0, agc_ref, 1'd0};
|
||||
2'd3: agc_ref_h <= {agc_ref, 2'd0};
|
||||
endcase
|
||||
case (vio_powertest_l)
|
||||
2'd0: agc_ref_l <= agc_ref - {3'd0, agc_ref[12:3]};
|
||||
2'd1: agc_ref_l <= agc_ref - {2'd0, agc_ref[12:2]};
|
||||
2'd2: agc_ref_l <= {1'd0, agc_ref[12:1]};
|
||||
2'd3: agc_ref_l <= {2'd0, agc_ref[12:2]};
|
||||
endcase
|
||||
|
||||
//查表地址
|
||||
if (agc_check <= 13'd11) addr_lut <= 11'd0;
|
||||
else begin
|
||||
if (agc_check >= 13'd2037) addr_lut <= 11'd2026;
|
||||
else addr_lut <= agc_check[10:0] - 11'd11;
|
||||
end
|
||||
flag_ram_1 <= 1'd1;
|
||||
flag_ram_2 <= 1'd0;
|
||||
rd_en <= 1'b1;
|
||||
dagc_rdy_d0 <= 1'b1;
|
||||
end
|
||||
|
||||
4'd4: begin
|
||||
if (cnt_4096_3 == 12'd4095) begin
|
||||
state_agc <= 4'd5;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
else begin
|
||||
state_agc <= state_agc;
|
||||
cnt_4096_3 <= 12'd01 + cnt_4096_3;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
agc_ref_temp <= agc_ref_temp + {12'd0, Dout};
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
flag_agc_power <= 1'd0;
|
||||
|
||||
flag_ram_1 <= 1'd0;
|
||||
flag_ram_2 <= 1'd0;
|
||||
end
|
||||
|
||||
4'd5: begin
|
||||
state_agc <= 4'd6;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
agc_check <= agc_ref_temp[22:10];
|
||||
flag_agc_power <= 1'd1;
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
|
||||
4'd6: begin
|
||||
if (cnt_databag == 15'd13823) begin
|
||||
cnt_databag <= 15'd0;
|
||||
state_agc <= 4'd7;
|
||||
cnt_4096_3 <= 12'd1;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
end
|
||||
else begin
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
state_agc <= state_agc;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
end
|
||||
flag_agc_power <= 1'd0;
|
||||
if ({2'd0, agc_check} > agc_ref_h) begin
|
||||
flag_agch <= 1'd1;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if (agc_check < agc_ref_l) begin
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
end
|
||||
//查表地址
|
||||
if (agc_check <= 13'd11) addr_lut <= 11'd0;
|
||||
else begin
|
||||
if (agc_check >= 13'd2037) addr_lut <= 11'd2026;
|
||||
else addr_lut <= agc_check[10:0] - 11'd11;
|
||||
end
|
||||
flag_ram_1 <= 1'd0;
|
||||
flag_ram_2 <= 1'd1;
|
||||
end
|
||||
|
||||
4'd7: begin
|
||||
if (cnt_4096_3 == 12'd4095) begin
|
||||
state_agc <= 4'd8;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
else begin
|
||||
state_agc <= state_agc;
|
||||
cnt_4096_3 <= 12'd01 + cnt_4096_3;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
end
|
||||
agc_ref_temp <= agc_ref_temp + {12'd0, Dout};
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
flag_agc_power <= 1'd0;
|
||||
|
||||
flag_ram_1 <= 1'd0;
|
||||
flag_ram_2 <= 1'd0;
|
||||
end
|
||||
|
||||
4'd8: begin
|
||||
state_agc <= 4'd9;
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
agc_check <= agc_ref_temp[22:10];
|
||||
flag_agc_power <= 1'd1;
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
|
||||
4'd9: begin
|
||||
if (cnt_databag == 15'd13823) begin
|
||||
cnt_databag <= 15'd0;
|
||||
state_agc <= 4'd4;
|
||||
cnt_4096_3 <= 12'd1;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
end
|
||||
else begin
|
||||
cnt_databag <= 15'd1 + cnt_databag;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
state_agc <= state_agc;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
end
|
||||
flag_agc_power <= 1'd0;
|
||||
if ({2'd0, agc_check} > agc_ref_h) begin
|
||||
flag_agch <= 1'd1;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if (agc_check < agc_ref_l) begin
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
flag_agch <= 1'd0;
|
||||
flag_agcl <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
//查表地址
|
||||
if (agc_check <= 13'd11) addr_lut <= 11'd0;
|
||||
else begin
|
||||
if (agc_check >= 13'd2037) addr_lut <= 11'd2026;
|
||||
else addr_lut <= agc_check[10:0] - 11'd11;
|
||||
end
|
||||
flag_ram_1 <= 1'd1;
|
||||
flag_ram_2 <= 1'd0;
|
||||
end
|
||||
4'd10: begin
|
||||
if (framesync == 1'b1) begin
|
||||
state_agc <= 4'd1;
|
||||
agc_ref_temp <= {12'd0, Dout};
|
||||
cnt_4096_3 <= 12'd1;
|
||||
cnt_databag <= 15'd1;
|
||||
end
|
||||
else begin
|
||||
state_agc <= state_agc;
|
||||
cnt_databag <= 15'd0;
|
||||
cnt_4096_3 <= 12'd0;
|
||||
flag_agc_power <= 1'd0;
|
||||
agc_ref_temp <= agc_ref_temp;
|
||||
case (vio_powertest_h)
|
||||
2'd0: agc_ref_h <= {2'd0, agc_ref} + {4'd0, agc_ref[12:2]};
|
||||
2'd1: agc_ref_h <= {2'd0, agc_ref} + {3'd0, agc_ref[12:1]};
|
||||
2'd2: agc_ref_h <= {1'd0, agc_ref, 1'd0};
|
||||
2'd3: agc_ref_h <= {agc_ref, 2'd0};
|
||||
endcase
|
||||
case (vio_powertest_l)
|
||||
2'd0: agc_ref_l <= agc_ref - {3'd0, agc_ref[12:3]};
|
||||
2'd1: agc_ref_l <= agc_ref - {2'd0, agc_ref[12:2]};
|
||||
2'd2: agc_ref_l <= {1'd0, agc_ref[12:1]};
|
||||
2'd3: agc_ref_l <= {2'd0, agc_ref[12:2]};
|
||||
endcase
|
||||
|
||||
//查表地址
|
||||
if (agc_check <= 13'd11) addr_lut <= 11'd0;
|
||||
else begin
|
||||
if (agc_check >= 13'd2037) addr_lut <= 11'd2026;
|
||||
else addr_lut <= agc_check[10:0] - 11'd11;
|
||||
end
|
||||
flag_ram_1 <= 1'd1;
|
||||
flag_ram_2 <= 1'd0;
|
||||
rd_en <= 1'b1;
|
||||
mgc_rdy_d0 <= 1'b1;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg [13:0] agcdata0 = 14'd0;
|
||||
reg [13:0] agcdata1 = 14'd0;
|
||||
always @(posedge clk) begin
|
||||
agcdata0 <= dout_lut;
|
||||
agcdata1 <= agcdata0;
|
||||
end
|
||||
//-------------------------------------补偿用的乘法器----------------------------//
|
||||
wire [23:0] mulout_i;
|
||||
DAGC_mul_10bit12 DAGC_mul_10bit12_i (
|
||||
.CLK(clk), // input clk
|
||||
.A (mf_i), // input [9 : 0] a
|
||||
.B (agcdata0), // input [13 : 0] b
|
||||
.P (mulout_i) // output [23 : 0] p
|
||||
);
|
||||
|
||||
wire [23:0] mulout_q;
|
||||
DAGC_mul_10bit12 DAGC_mul_10bit12_q (
|
||||
.CLK(clk), // input clk
|
||||
.A (mf_q), // input [9 : 0] a
|
||||
.B (agcdata0), // input [13 : 0] b
|
||||
.P (mulout_q) // output [23 : 0] p
|
||||
);
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (mulout_i[23:17] == 7'b111_1111 || mulout_i[23:17] == 7'b000_0000) DAGC_out_i <= mulout_i[17:8];
|
||||
else DAGC_out_i <= (mulout_i[23]) ? 10'b1000_0000_01 : 10'b0111_1111_11;
|
||||
|
||||
if (mulout_q[23:17] == 7'b111_1111 || mulout_q[23:17] == 7'b000_0000) DAGC_out_q <= mulout_q[17:8];
|
||||
else DAGC_out_q <= (mulout_q[23]) ? 10'b1000_0000_01 : 10'b0111_1111_11;
|
||||
end
|
||||
|
||||
/*ila_dagc ila_dagc(
|
||||
.clk(clk),
|
||||
.probe0(mgc1_rdy),
|
||||
.probe1(empty),
|
||||
.probe2(full),
|
||||
.probe3(rd_en),
|
||||
.probe4(DAGC_out_i),
|
||||
.probe5(DAGC_out_q),
|
||||
.probe6(state_agc),
|
||||
.probe7(dagc_rdy),
|
||||
.probe8(mgc_rdy),
|
||||
.probe9(data_count)
|
||||
|
||||
);*/
|
||||
|
||||
reg [19:0] cnt_rst = 20'd0;
|
||||
always @(posedge clk) begin
|
||||
if (dagc_rdy_d0 && !dagc_rdy_d1) begin
|
||||
cnt_rst <= 20'd0;
|
||||
rst_dagc <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_rst == 20'd580620) begin
|
||||
rst_dagc <= 1'b1;
|
||||
cnt_rst <= cnt_rst + 20'd1;
|
||||
end
|
||||
else if (cnt_rst == 20'd580621) begin
|
||||
rst_dagc <= 1'b0;
|
||||
cnt_rst <= cnt_rst;
|
||||
end
|
||||
else begin
|
||||
cnt_rst <= cnt_rst + 20'd1;
|
||||
rst_dagc <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,211 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/08/03 14:12:18
|
||||
// Design Name:
|
||||
// Module Name: DDS_compensate
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module DDS_compensate(
|
||||
clk,
|
||||
rst,
|
||||
din_nd, // 输入数据
|
||||
din_i,
|
||||
din_q,
|
||||
acq_nd, // 捕获信息
|
||||
dfreq_word_nd, // 频偏NCO信息
|
||||
dfreq_word,
|
||||
framesync_success, // 帧同步标志，用于切码
|
||||
// rs_idx_nd, //数据段信息速率，在帧同步标志后、勤务段最后一个数据前给出，！但并不表示从rs_idx_nd有效起输入就是数据段的数据了
|
||||
// rs_idx,
|
||||
|
||||
demod_trunc_i,
|
||||
demod_trunc_q,
|
||||
demod_trunc_nd,
|
||||
Demod_ovrflw
|
||||
|
||||
);
|
||||
input clk;
|
||||
input rst;
|
||||
input din_nd;
|
||||
input [11:0] din_i,din_q;
|
||||
input acq_nd;
|
||||
|
||||
input dfreq_word_nd;
|
||||
input [13:0] dfreq_word; //-- 解调频偏
|
||||
input framesync_success;
|
||||
|
||||
//-- 8个可变数据速率，从0~7分别代表30k~3840k
|
||||
wire rs_idx_nd =1'b0;
|
||||
wire [2:0] rs_idx;
|
||||
assign rs_idx =3'b000;
|
||||
output [11:0] demod_trunc_i,demod_trunc_q;
|
||||
output demod_trunc_nd ;
|
||||
output Demod_ovrflw;
|
||||
wire [4:0] acq_freindex; //-- 捕获频偏
|
||||
assign acq_freindex =5'd0;
|
||||
//----------------------------- DDS For FreqShift --------------------------------
|
||||
//-- 注意这里DDS产生的是偏移频率，下面补偿的时候要与DDS输出的【共轭】相复乘
|
||||
localparam DDS_width = 24; //25bits in fact
|
||||
|
||||
reg dds_rst = 0; // DDS starts after acquisition
|
||||
reg [DDS_width:0] dds_start_freq = 0;
|
||||
reg dds_update = 0; // identifier of updated deltafrequency & its rate
|
||||
reg [DDS_width:0] dds_update_df = 0;
|
||||
reg [DDS_width:0] dds_phase = 0;
|
||||
reg [DDS_width:0] dds_freq = 0; // 相位累积量，残余频偏和变化率控制
|
||||
/*wire [13:0] freq_abs;
|
||||
reg freq_plus;
|
||||
assign freq_abs=(dfreq_word[13]==1'd1)? -dfreq_word:dfreq_word;
|
||||
always @ (posedge clk) begin
|
||||
if(rst) begin
|
||||
freq_plus <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if(dfreq_word_nd) begin
|
||||
freq_plus <= dfreq_word[13];
|
||||
end
|
||||
else begin
|
||||
freq_plus <= freq_plus;
|
||||
end
|
||||
end
|
||||
end
|
||||
*/
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst || acq_nd)
|
||||
dds_rst <= 1;
|
||||
else
|
||||
dds_rst <= 0;
|
||||
|
||||
always @(posedge clk)
|
||||
if (!rst && acq_nd)
|
||||
dds_start_freq <= {{8{acq_freindex[4]}},acq_freindex[4:0],{(DDS_width-12){1'b0}}};
|
||||
else
|
||||
dds_start_freq <= dds_start_freq;
|
||||
always @(posedge clk)
|
||||
if (!rst && dfreq_word_nd) begin
|
||||
dds_update <= 1;
|
||||
dds_update_df <= {{(DDS_width-13){dfreq_word[13]}},dfreq_word[13:0]};
|
||||
end
|
||||
else
|
||||
dds_update <= 0;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rst || dds_rst)
|
||||
dds_phase <= 0;
|
||||
else if (din_nd)
|
||||
dds_phase <= dds_phase + dds_freq;
|
||||
else
|
||||
dds_phase <= dds_phase;
|
||||
|
||||
wire [DDS_width:0] updata_s;
|
||||
AdderSigned_25_25_2dly DDS_DFreq_Update1 (
|
||||
//.A(dds_freq), // input wire [24 : 0] A
|
||||
.A(25'd0),
|
||||
.B(dds_update_df), // input wire [24 : 0] B
|
||||
.CLK(clk), // input wire CLK
|
||||
.S(updata_s) // output wire [24 : 0] S
|
||||
);
|
||||
|
||||
//--- delay ---
|
||||
reg dds_update_d1 = 0,dds_update_d2 = 0;
|
||||
reg din_nd_d1 = 0,din_nd_d2 = 0;
|
||||
always @(posedge clk)
|
||||
if (rst) begin
|
||||
dds_update_d1 <= 0;
|
||||
dds_update_d2 <= 0;
|
||||
din_nd_d1 <= 0;
|
||||
din_nd_d2 <= 0;
|
||||
end
|
||||
else begin
|
||||
dds_update_d1 <= dds_update;
|
||||
dds_update_d2 <= dds_update_d1;
|
||||
din_nd_d1 <= din_nd;
|
||||
din_nd_d2 <= din_nd_d1;
|
||||
end
|
||||
always @(posedge clk)
|
||||
if (rst)
|
||||
dds_freq <= 0;
|
||||
else if (dds_rst)
|
||||
dds_freq <= dds_start_freq;
|
||||
else if (dds_update_d2)
|
||||
dds_freq <= updata_s;
|
||||
else
|
||||
dds_freq <= dds_freq;
|
||||
|
||||
reg [12:0] cos_addr = 0,sin_addr = -13'd2048;
|
||||
wire [11:0] cos_dout,sin_dout;
|
||||
always @(posedge clk)
|
||||
if (rst) begin
|
||||
cos_addr <= 0;
|
||||
sin_addr <= -13'd2048;
|
||||
end
|
||||
else begin
|
||||
cos_addr <= dds_phase[DDS_width:DDS_width-12];
|
||||
sin_addr <= dds_phase[DDS_width:DDS_width-12] - 13'd2048;
|
||||
end
|
||||
COSLUT_8192 DDS_12bit_8192 (
|
||||
.clka(clk), // input wire clka
|
||||
.addra(cos_addr), // input wire [12 : 0] addra
|
||||
.douta(cos_dout), // output wire [11 : 0] douta
|
||||
.clkb(clk), // input wire clkb
|
||||
.addrb(sin_addr), // input wire [12 : 0] addrb
|
||||
.doutb(sin_dout) // output wire [11 : 0] doutb
|
||||
);
|
||||
|
||||
//------------------------------- Compensate ------------------------------
|
||||
wire [24:0] demod_i,demod_q;
|
||||
wire [13:0] DemodMult_pad;
|
||||
//wire [11:0] demod_trunc_i,demod_trunc_q;
|
||||
wire demod_nd; //排除第一个，这两个信号和din_nd是同步的
|
||||
//wire demod_trunc_nd;
|
||||
wire Demod_ovrflw_i,Demod_ovrflw_q;
|
||||
//wire Demod_ovrflw ;
|
||||
assign Demod_ovrflw = Demod_ovrflw_i || Demod_ovrflw_q;
|
||||
/*wire [11:0] sin_din;
|
||||
wire [11:0] cos_din;
|
||||
assign sin_din=(freq_plus==1'd1)? sin_dout:-sin_dout;
|
||||
assign cos_din = cos_dout;*/
|
||||
ComplexMult12x12_4dly MultFreq (
|
||||
.aclk(clk), // input wire aclk
|
||||
.s_axis_a_tvalid(din_nd), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata({4'd0,din_q,4'd0,din_i}), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid(din_nd), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata({4'd0,-sin_dout,4'd0,cos_dout}), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid(demod_nd), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata({DemodMult_pad[13:7],demod_q,DemodMult_pad[6:0],demod_i}) // output wire [47 : 0] m_axis_dout_tdata
|
||||
);
|
||||
trunc_25to12_2dly Trunc_demod_i (
|
||||
.clk(clk),
|
||||
.din_nd(demod_nd),
|
||||
.din(demod_i),
|
||||
.ctrl(),
|
||||
.dout_nd(demod_trunc_nd),
|
||||
.dout(demod_trunc_i),
|
||||
.ovrflw(Demod_ovrflw_i)
|
||||
);
|
||||
trunc_25to12_2dly Trunc_demod_q (
|
||||
.clk(clk),
|
||||
.din_nd(demod_nd),
|
||||
.din(demod_q),
|
||||
.ctrl(),
|
||||
.dout_nd(),
|
||||
.dout(demod_trunc_q),
|
||||
.ovrflw(Demod_ovrflw_q)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,973 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/14 17:44:48
|
||||
// Design Name:
|
||||
// Module Name: FrameMerge
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module FrameMerge(
|
||||
input clk,
|
||||
input rst,
|
||||
input rst2,
|
||||
input sync,
|
||||
input nd,
|
||||
input din,
|
||||
|
||||
input [6:0] vio_stopbit,
|
||||
|
||||
input frameIDnd,
|
||||
input clk2,
|
||||
output reg framerdy = 1'b0,
|
||||
// output reg flag_recvram = 1'b0,
|
||||
// input [12:0] recv_addr1,
|
||||
// input [12:0] recv_addr2,
|
||||
// output [7:0] recv_data1,
|
||||
// output [7:0] recv_data2,
|
||||
input [13:0] recv_addr_new_0,
|
||||
input [13:0] recv_addr_new_1,
|
||||
input [13:0] recv_addr_new_2,
|
||||
input [13:0] recv_addr_new_3,
|
||||
output [7:0] recv_data_new_0,
|
||||
output [7:0] recv_data_new_1,
|
||||
output [7:0] recv_data_new_2,
|
||||
output [7:0] recv_data_new_3,
|
||||
output reg [16:0] RAMaddra_write_0 = 17'd0,
|
||||
output reg [16:0] RAMaddra_write_1 = 17'd0,
|
||||
output reg [16:0] RAMaddra_write_2 = 17'd0,
|
||||
output reg [16:0] RAMaddra_write_3 = 17'd0,
|
||||
output reg [16:0] RAMaddra_new_0 = 17'd0,
|
||||
output reg [16:0] RAMaddra_new_1 = 17'd0,
|
||||
output reg [16:0] RAMaddra_new_2 = 17'd0,
|
||||
output reg [16:0] RAMaddra_new_3 = 17'd0,
|
||||
output reg flag_notbyte = 1'd0,
|
||||
output reg [1:0] state_ram = 2'd0,
|
||||
|
||||
output reg flag_stop = 1'd0, //给shx，拉高一个clk表示当前时帧有效数据接收完毕
|
||||
output reg [16:0] addr_stop = 17'd0, //给shx，拉高一个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
||||
|
||||
//debug
|
||||
output reg berstart_1d = 1'b0,
|
||||
output reg bercompare = 1'b0,
|
||||
output reg [16:0] bercount = 17'd0,
|
||||
output reg [16:0] bercount_max = 17'd0,
|
||||
output reg [16:0] ROMaddra_d2 = 17'd0,
|
||||
output reg RAMdout_d1 = 1'd0,
|
||||
|
||||
// output reg validnd_1_1d = 1'b0,
|
||||
// output reg validnd_2_1d = 1'b0,
|
||||
output reg validnd_new_new = 1'b0,
|
||||
// output reg [63:0] stop_temp_1 = 64'd0,
|
||||
// output reg [63:0] stop_temp_2 = 64'd0,
|
||||
output reg [63:0] stop_temp_new = 64'd0,
|
||||
|
||||
output flag_stop_0, //给shx，拉高1个clk表示当前时帧有效数据接收完毕
|
||||
output [16:0] addr_stop_0,
|
||||
output reg [2:0] cnt_8 = 3'b0,
|
||||
output reg state_8 = 1'd0,
|
||||
|
||||
output rdy_scramble,
|
||||
output dout_scramble,
|
||||
|
||||
output reg [16:0] RAMaddra = 17'd0, //比较误码率
|
||||
output reg [16:0] ROMaddra = 17'd0, //比较误码率
|
||||
output reg [0:0] nd_ber = 1'd0, //比较误码率
|
||||
output reg [63:0] recvNetData,
|
||||
output reg recvNetDataNd
|
||||
// input [7:0] video_id01,
|
||||
// input [7:0] video_id02,
|
||||
// input [7:0] video_id03,
|
||||
// input [7:0] MAC_idNum
|
||||
);
|
||||
|
||||
reg frameIDnd_d1 = 1'd0;
|
||||
reg frameIDnd_d2 = 1'd0;
|
||||
always @(posedge clk)begin
|
||||
frameIDnd_d1 <= frameIDnd;
|
||||
frameIDnd_d2 <= frameIDnd_d1;
|
||||
end
|
||||
|
||||
// always @(posedge clk)begin
|
||||
// if(frameIDnd && !frameIDnd_d1) flag_recvram <= ~flag_recvram;
|
||||
// else flag_recvram <= flag_recvram;
|
||||
// end
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------//
|
||||
|
||||
// reg validnd_1 = 1'b0;
|
||||
// reg validnd_2 = 1'b0;
|
||||
reg validnd_new = 1'b0;
|
||||
reg [9:0] validlength = 10'd0;
|
||||
reg [6:0] cnt_net;
|
||||
reg [1:0] state_recv;
|
||||
reg nd_recvnet_dout;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
// validnd_1 <= 1'b0;
|
||||
// validnd_2 <= 1'b0;
|
||||
state_recv <= 2'd0;
|
||||
validnd_new <= 1'b0;
|
||||
validlength <= 10'd0;
|
||||
cnt_net <= 6'd0;
|
||||
nd_recvnet_dout <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_recv)
|
||||
2'd0:begin
|
||||
if(!validnd_new)begin
|
||||
if(sync)begin
|
||||
validnd_new <= 1'b1;
|
||||
nd_recvnet_dout <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
validnd_new <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if(cnt_net == 6'd63) begin
|
||||
validlength <= validlength + 10'd1;
|
||||
if(validlength == 10'd1023)begin
|
||||
validnd_new <= 1'b0;
|
||||
state_recv <= 2'd1;
|
||||
end else begin
|
||||
validnd_new <= 1'b1;
|
||||
state_recv <= state_recv;
|
||||
end
|
||||
nd_recvnet_dout <= 1'b0;
|
||||
cnt_net <= 6'd63;
|
||||
end
|
||||
else begin
|
||||
state_recv <= state_recv;
|
||||
nd_recvnet_dout <= 1'b1;
|
||||
cnt_net <= cnt_net +6'd1;
|
||||
validlength <= validlength + 10'd1;
|
||||
if(validlength == 10'd1023)begin
|
||||
validnd_new <= 1'b0;
|
||||
end else begin
|
||||
validnd_new <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
2'd1:begin
|
||||
if(!validnd_new)begin
|
||||
if(sync)begin
|
||||
validnd_new <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
validnd_new <= 1'b0;
|
||||
end
|
||||
state_recv <= state_recv;
|
||||
end
|
||||
else begin
|
||||
state_recv <= state_recv;
|
||||
nd_recvnet_dout <= 1'b0;
|
||||
cnt_net <= 6'd0;
|
||||
validlength <= validlength + 10'd1;
|
||||
if(validlength == 10'd1023)begin
|
||||
validnd_new <= 1'b0;
|
||||
end else begin
|
||||
validnd_new <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
default:begin
|
||||
|
||||
if(!validnd_new)begin
|
||||
if(sync)begin
|
||||
|
||||
validnd_new <= 1'b1;
|
||||
|
||||
nd_recvnet_dout <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
validnd_new <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if(cnt_net == 6'd63) begin
|
||||
validlength <= validlength + 10'd1;
|
||||
if(validlength == 10'd1023)begin
|
||||
validnd_new <= 1'b0;
|
||||
state_recv <= 2'd1;
|
||||
end else begin
|
||||
validnd_new <= 1'b1;
|
||||
state_recv <= state_recv;
|
||||
end
|
||||
nd_recvnet_dout <= 1'b0;
|
||||
cnt_net <= 6'd63;
|
||||
end
|
||||
else begin
|
||||
state_recv <= state_recv;
|
||||
nd_recvnet_dout <= 1'b1;
|
||||
cnt_net <= cnt_net +6'd1;
|
||||
validlength <= validlength + 10'd1;
|
||||
if(validlength == 10'd1023)begin
|
||||
validnd_new <= 1'b0;
|
||||
end else begin
|
||||
validnd_new <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// reg [15:0] RAMaddra_1 = 16'd0;
|
||||
// reg [15:0] RAMaddra_2 = 16'd0;
|
||||
// reg [16:0] RAMaddra_new = 17'd0;
|
||||
// reg [15:0] RAMaddra = 16'd0; //比较误码率
|
||||
reg [0:0] dout_scramble_d1 = 1'd0; //比较误码率
|
||||
// reg [0:0] nd_ber = 1'd0; //比较误码率
|
||||
// reg validnd_1_1d = 1'b0;
|
||||
// reg validnd_2_1d = 1'b0;
|
||||
reg validnd_new_1d = 1'b0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
// RAMaddra_1 <= 16'd0;
|
||||
// RAMaddra_2 <= 16'd0;
|
||||
// RAMaddra_new <= RAMaddra_new;
|
||||
RAMaddra <= 17'd0; //比较误码率
|
||||
ROMaddra <= 17'd0; //比较误码率
|
||||
dout_scramble_d1 <= 1'd0; //比较误码率
|
||||
nd_ber <= 1'd0; //比较误码率
|
||||
// validnd_1_1d <= 1'b0;
|
||||
// validnd_2_1d <= 1'b0;
|
||||
validnd_new_1d <= 1'b0;
|
||||
end else begin
|
||||
// validnd_1_1d <= validnd_1;
|
||||
// if(validnd_1_1d) begin
|
||||
// RAMaddra_1 <= RAMaddra_1 + 16'd1;
|
||||
// end else begin
|
||||
// RAMaddra_1 <= RAMaddra_1;
|
||||
// end
|
||||
|
||||
// validnd_2_1d <= validnd_2;
|
||||
// if(validnd_2_1d) begin
|
||||
// RAMaddra_2 <= RAMaddra_2 + 16'd1;
|
||||
// end else begin
|
||||
// RAMaddra_2 <= RAMaddra_2;
|
||||
// end
|
||||
|
||||
validnd_new_1d <= validnd_new;
|
||||
// if(validnd_new_1d) begin
|
||||
// RAMaddra_new <= RAMaddra_new + 16'd1;
|
||||
// end else begin
|
||||
// RAMaddra_new <= RAMaddra_new;
|
||||
// end
|
||||
|
||||
//比较误码率
|
||||
// if(validnd_1_1d||validnd_2_1d) begin
|
||||
if(validnd_new_1d) begin
|
||||
RAMaddra <= RAMaddra + 17'd1;
|
||||
ROMaddra <= ROMaddra + 17'd1;
|
||||
dout_scramble_d1 <= dout_scramble;
|
||||
nd_ber <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
RAMaddra <= RAMaddra;
|
||||
ROMaddra <= ROMaddra;
|
||||
dout_scramble_d1 <= dout_scramble_d1;
|
||||
nd_ber <= 1'd0;
|
||||
end
|
||||
//比较误码率
|
||||
end
|
||||
end
|
||||
|
||||
reg nd_recvnet_dout_d1;
|
||||
reg nd_recvnet_dout_d2;
|
||||
reg nd_recvnet_dout_d3;
|
||||
reg nd_recvnet_dout_d4;
|
||||
|
||||
reg wr_en_232;
|
||||
reg rs232_send;
|
||||
reg [4:0] cnt_422_wait;
|
||||
wire validnd_new_delay;
|
||||
reg validnd_new_delay_d1;
|
||||
wire framedata;
|
||||
reg framedata_d1;
|
||||
reg [7:0] data_net_byte [87:0];
|
||||
reg [7:0] clk_net_byte;
|
||||
reg [9:0] clk_net_bit;
|
||||
//shiftram_scramble shiftram_scramble(.CLK(clk),.D({dout_scramble,validnd_new}),.Q({framedata,validnd_new_delay}));
|
||||
reg [7:0] cnt_422_net;
|
||||
always @(posedge clk)begin
|
||||
if(rst2)begin
|
||||
state_ram <= 2'd0;
|
||||
RAMaddra_new_0 <= 17'd0;
|
||||
RAMaddra_new_1 <= 17'd0;
|
||||
RAMaddra_new_2 <= 17'd0;
|
||||
RAMaddra_new_3 <= 17'd0;
|
||||
flag_notbyte <= 1'd0;
|
||||
nd_recvnet_dout_d1 <= 1'd0;
|
||||
nd_recvnet_dout_d2 <= 1'd0;
|
||||
nd_recvnet_dout_d3 <= 1'd0;
|
||||
nd_recvnet_dout_d4 <= 1'd0;
|
||||
recvNetDataNd <= 1'd0;
|
||||
recvNetData <= 64'd0;
|
||||
wr_en_232 <= 1'b0;
|
||||
rs232_send <= 1'b0;
|
||||
cnt_422_wait <= 5'd0;
|
||||
cnt_422_net <= 8'd0;
|
||||
clk_net_bit <= 10'd0;
|
||||
clk_net_byte <= 8'd0;
|
||||
validnd_new_delay_d1 <= 1'b0;
|
||||
framedata_d1 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
framedata_d1 <= framedata;
|
||||
validnd_new_delay_d1 <= validnd_new_delay;
|
||||
nd_recvnet_dout_d1 <= nd_recvnet_dout;
|
||||
nd_recvnet_dout_d2 <= nd_recvnet_dout_d1;
|
||||
nd_recvnet_dout_d3 <= nd_recvnet_dout_d2;
|
||||
nd_recvnet_dout_d4 <= nd_recvnet_dout_d3;
|
||||
if(!nd_recvnet_dout_d1 && nd_recvnet_dout_d2) begin//检测到网络层数据传输完毕拉高2个clk recvNetDataNd
|
||||
recvNetDataNd <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if(!nd_recvnet_dout_d3 && nd_recvnet_dout_d4) begin//延迟2个clk确保50MHz采到recvNetDataNd再拉低
|
||||
recvNetDataNd <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
recvNetDataNd <= recvNetDataNd;
|
||||
end
|
||||
end
|
||||
case(state_ram)
|
||||
//有了新的一帧，准备开始存储
|
||||
2'd0:begin
|
||||
if(frameIDnd_d2) begin
|
||||
state_ram <= 2'd1;
|
||||
RAMaddra_new_0<= RAMaddra_new_0;
|
||||
RAMaddra_new_1<= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
else begin
|
||||
state_ram <= state_ram;
|
||||
RAMaddra_new_0<= RAMaddra_new_0;
|
||||
RAMaddra_new_1<= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
validnd_new_new <= 1'd0;
|
||||
flag_notbyte <= 1'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
if(flag_stop_0) begin
|
||||
if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_0 <= addr_stop_0 +17'd1;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_1 <= addr_stop_0 +17'd1;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_2 <= addr_stop_0 +17'd1;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_3 <= addr_stop_0 +17'd1;
|
||||
end
|
||||
else begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
validnd_new_new <= 1'd0;
|
||||
state_ram <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
state_ram <= state_ram;
|
||||
validnd_new_new <= validnd_new;
|
||||
if(validnd_new_new) begin
|
||||
if(nd_recvnet_dout_d1) begin
|
||||
recvNetData[63:0] <= {dout_scramble,recvNetData[63:1]};
|
||||
end
|
||||
else begin
|
||||
if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0 + 17'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1 + 17'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2 + 17'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3 + 17'd1;
|
||||
end
|
||||
else begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
end
|
||||
flag_notbyte <= 1'd0;
|
||||
end
|
||||
2'd2:begin
|
||||
// rs232_send <= 1'b0;
|
||||
state_ram <= 2'd0;
|
||||
if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
case(RAMaddra_new_0[2:0])
|
||||
3'b000:begin
|
||||
flag_notbyte <= 1'd0;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
end
|
||||
3'b001:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd7;
|
||||
end
|
||||
3'b010:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd6;
|
||||
end
|
||||
3'b011:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd5;
|
||||
end
|
||||
3'b100:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd4;
|
||||
end
|
||||
3'b101:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd3;
|
||||
end
|
||||
3'b110:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd2;
|
||||
end
|
||||
3'b111:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0+17'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
case(RAMaddra_new_1[2:0])
|
||||
3'b000:begin
|
||||
flag_notbyte <= 1'd0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
end
|
||||
3'b001:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd7;
|
||||
end
|
||||
3'b010:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd6;
|
||||
end
|
||||
3'b011:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd5;
|
||||
end
|
||||
3'b100:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd4;
|
||||
end
|
||||
3'b101:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd3;
|
||||
end
|
||||
3'b110:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd2;
|
||||
end
|
||||
3'b111:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1+17'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
case(RAMaddra_new_2[2:0])
|
||||
3'b000:begin
|
||||
flag_notbyte <= 1'd0;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
end
|
||||
3'b001:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd7;
|
||||
end
|
||||
3'b010:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd6;
|
||||
end
|
||||
3'b011:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd5;
|
||||
end
|
||||
3'b100:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd4;
|
||||
end
|
||||
3'b101:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd3;
|
||||
end
|
||||
3'b110:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd2;
|
||||
end
|
||||
3'b111:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2+17'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'hff&& recvNetData[23:0]==24'h7E5A33) begin
|
||||
case(RAMaddra_new_3[2:0])
|
||||
3'b000:begin
|
||||
flag_notbyte <= 1'd0;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
3'b001:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd7;
|
||||
end
|
||||
3'b010:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd6;
|
||||
end
|
||||
3'b011:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd5;
|
||||
end
|
||||
3'b100:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd4;
|
||||
end
|
||||
3'b101:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd3;
|
||||
end
|
||||
3'b110:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd2;
|
||||
end
|
||||
3'b111:begin
|
||||
flag_notbyte <= 1'd1;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3+17'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
flag_notbyte <= 1'b0;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
|
||||
end
|
||||
default:begin
|
||||
if(frameIDnd_d2) begin
|
||||
state_ram <= 2'd1;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
else begin
|
||||
state_ram <= state_ram;
|
||||
RAMaddra_new_0 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3 <= RAMaddra_new_3;
|
||||
end
|
||||
validnd_new_new <= 1'd0;
|
||||
flag_notbyte <= 1'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [8:0] bagcnt = 9'd0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
bagcnt <= 9'd0;
|
||||
end else begin
|
||||
if(sync)begin
|
||||
bagcnt <= bagcnt + 9'd1;
|
||||
end else begin
|
||||
bagcnt <= bagcnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire scramblestart;
|
||||
assign scramblestart = (bagcnt == 9'd0)? sync : 1'b0;
|
||||
|
||||
// wire rdy_scramble;
|
||||
// wire dout_scramble;
|
||||
Scramble Scramble (
|
||||
.clk(clk),
|
||||
.rst(rst2 || framerdy),
|
||||
.start(scramblestart),
|
||||
// .nd(validnd_1||validnd_2),
|
||||
.nd(validnd_new),
|
||||
.din(din),
|
||||
.rdy(rdy_scramble),
|
||||
.dout(dout_scramble)
|
||||
);
|
||||
|
||||
|
||||
|
||||
//------------------------------------------比较误码率---------------------------//
|
||||
reg [16:0] RAMaddrb = 17'd0;
|
||||
wire RAMdout;
|
||||
RAM_merge RAM_merge_0 (
|
||||
.clka(clk), // input clka
|
||||
// .wea(validnd_1_1d||validnd_2_1d), // input [0 : 0] wea
|
||||
.wea(validnd_new_1d), // input [0 : 0] wea
|
||||
.addra(RAMaddra), // input [16 : 0] addra
|
||||
.dina(dout_scramble), // input [0 : 0] dina
|
||||
.clkb(clk), // input clkb
|
||||
.addrb(RAMaddrb), // input [16 : 0] addrb
|
||||
.doutb(RAMdout) // output [0 : 0] doutb
|
||||
);
|
||||
|
||||
// reg [15:0] ROMaddra = 16'd0;
|
||||
wire ROMdout;
|
||||
ROM_ber ROM_ber (
|
||||
.clka(clk), // input clka
|
||||
.addra(ROMaddra), // input [16 : 0] addra
|
||||
.douta(ROMdout) // output [0 : 0] douta
|
||||
);
|
||||
|
||||
reg berstart = 1'b0;
|
||||
always @(posedge clk)begin
|
||||
if(rst2)begin
|
||||
RAMaddrb <= 17'd0;
|
||||
berstart <= 1'b0;
|
||||
end else begin
|
||||
if(!berstart)begin
|
||||
RAMaddrb <= 17'd0;
|
||||
if(bagcnt == 9'd105 && validlength == 10'd1023)begin
|
||||
berstart <= 1'b1;
|
||||
end else begin
|
||||
berstart <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
if(RAMaddrb == 17'd107519)begin
|
||||
berstart <= 1'b0;
|
||||
RAMaddrb <= 17'd0;
|
||||
end else begin
|
||||
berstart <= 1'b1;
|
||||
RAMaddrb <= RAMaddrb + 17'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
reg [16:0] ROMaddra_d1 = 17'd0;
|
||||
always @(posedge clk)begin
|
||||
berstart_1d <= berstart;
|
||||
if(rst)begin
|
||||
bercompare <= 1'b0;
|
||||
bercount <= 17'd0;
|
||||
ROMaddra_d1 <= 17'd0;
|
||||
ROMaddra_d2 <= 17'd0;
|
||||
RAMdout_d1 <= 1'd0;
|
||||
bercount_max <= bercount;
|
||||
end else begin
|
||||
if(nd_ber) begin
|
||||
bercompare <= dout_scramble_d1^ROMdout;
|
||||
bercount <= bercount + bercompare;
|
||||
|
||||
ROMaddra_d1 <= ROMaddra;
|
||||
ROMaddra_d2 <= ROMaddra_d1;
|
||||
RAMdout_d1 <= dout_scramble_d1;
|
||||
bercount_max <= bercount_max;
|
||||
end
|
||||
else begin
|
||||
bercompare <= 1'd0;
|
||||
bercount <= bercount;
|
||||
|
||||
ROMaddra_d1 <= ROMaddra_d1;
|
||||
ROMaddra_d2 <= ROMaddra_d2;
|
||||
RAMdout_d1 <= RAMdout_d1;
|
||||
bercount_max <= bercount_max;
|
||||
end
|
||||
end
|
||||
end
|
||||
//------------------------------------------比较误码率---------------------------//
|
||||
|
||||
|
||||
|
||||
// RAM_recv RAM_recv_1 (
|
||||
// .clka(clk), // input clka
|
||||
// .wea(validnd_1_1d), // input [0 : 0] wea
|
||||
// .addra(RAMaddra_1), // input [15 : 0] addra
|
||||
// .dina(dout_scramble), // input [0 : 0] dina
|
||||
// .clkb(clk2), // input clkb
|
||||
// .addrb(recv_addr1), // input [12 : 0] addrb
|
||||
// .doutb(recv_data1) // output [7 : 0] doutb
|
||||
// );
|
||||
|
||||
// RAM_recv RAM_recv_2 (
|
||||
// .clka(clk), // input clka
|
||||
// .wea(validnd_2_1d), // input [0 : 0] wea
|
||||
// .addra(RAMaddra_2), // input [15 : 0] addra
|
||||
// .dina(dout_scramble), // input [0 : 0] dina
|
||||
// .clkb(clk2), // input clkb
|
||||
// .addrb(recv_addr2), // input [12 : 0] addrb
|
||||
// .doutb(recv_data2) // output [7 : 0] doutb
|
||||
// );
|
||||
|
||||
RAM_recvnew RAM_recvnew_0 (
|
||||
.clka(clk), // input clka
|
||||
.wea(validnd_new_new), // input [0 : 0] wea
|
||||
.addra(RAMaddra_new_0), // input [16 : 0] addra
|
||||
.dina(dout_scramble), // input [0 : 0] dina
|
||||
.clkb(clk2), // input clkb
|
||||
.addrb(recv_addr_new_0), // input [13 : 0] addrb
|
||||
.doutb(recv_data_new_0) // output [7 : 0] doutb
|
||||
);
|
||||
|
||||
RAM_recvnew RAM_recvnew_1 (
|
||||
.clka(clk), // input clka
|
||||
.wea(validnd_new_new), // input [0 : 0] wea
|
||||
.addra(RAMaddra_new_1), // input [16 : 0] addra
|
||||
.dina(dout_scramble), // input [0 : 0] dina
|
||||
.clkb(clk2), // input clkb
|
||||
.addrb(recv_addr_new_1), // input [13 : 0] addrb
|
||||
.doutb(recv_data_new_1) // output [7 : 0] doutb
|
||||
);
|
||||
RAM_recvnew RAM_recvnew_2 (
|
||||
.clka(clk), // input clka
|
||||
.wea(validnd_new_new), // input [0 : 0] wea
|
||||
.addra(RAMaddra_new_2), // input [16 : 0] addra
|
||||
.dina(dout_scramble), // input [0 : 0] dina
|
||||
.clkb(clk2), // input clkb
|
||||
.addrb(recv_addr_new_2), // input [13 : 0] addrb
|
||||
.doutb(recv_data_new_2) // output [7 : 0] doutb
|
||||
);
|
||||
/*RAM_recvnew RAM_recvnew_3 (
|
||||
.clka(clk), // input clka
|
||||
.wea(validnd_new_new), // input [0 : 0] wea
|
||||
.addra(RAMaddra_new_3), // input [16 : 0] addra
|
||||
.dina(dout_scramble), // input [0 : 0] dina
|
||||
.clkb(clk2), // input clkb
|
||||
.addrb(recv_addr_new_3), // input [13 : 0] addrb
|
||||
.doutb(recv_data_new_3) // output [7 : 0] doutb
|
||||
);*/
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------//
|
||||
|
||||
//-------------------------------------找停止位---------------------------//
|
||||
|
||||
|
||||
// reg nd_stop_1 = 1'd0;
|
||||
// reg nd_stop_2 = 1'd0;
|
||||
reg nd_stop_new = 1'd0;
|
||||
|
||||
// reg [15:0] RAMaddra_1_temp = 16'd0;
|
||||
// reg [15:0] RAMaddra_2_temp = 16'd0;
|
||||
reg [16:0] RAMaddra_new_temp = 17'd0;
|
||||
find_stop find_stop (
|
||||
.clk(clk),
|
||||
// .nd_stop_1(nd_stop_1),
|
||||
// .nd_stop_2(nd_stop_2),
|
||||
.nd_stop_new(nd_stop_new),
|
||||
// .RAMaddra_1_temp(RAMaddra_1_temp),
|
||||
// .RAMaddra_2_temp(RAMaddra_2_temp),
|
||||
.RAMaddra_new_temp(RAMaddra_new_temp),
|
||||
// .stop_temp_1(stop_temp_1),
|
||||
// .stop_temp_2(stop_temp_2),
|
||||
.stop_temp_new(stop_temp_new),
|
||||
|
||||
.vio_stopbit(vio_stopbit),
|
||||
|
||||
.flag_stop_0(flag_stop_0),
|
||||
.addr_stop_0(addr_stop_0)
|
||||
);
|
||||
|
||||
// reg [63:0] stop_temp_1 = 64'd0;
|
||||
// reg [63:0] stop_temp_2 = 64'd0;
|
||||
// reg flag_stop_0 = 1'd0; //给shx，拉高1个clk表示当前时帧有效数据接收完毕
|
||||
// reg [15:0] addr_stop_0 = 16'd0; //给shx，拉高1个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
||||
always @(posedge clk)begin
|
||||
// nd_stop_1 <= validnd_1_1d;
|
||||
// nd_stop_2 <= validnd_2_1d;
|
||||
nd_stop_new <= validnd_new_1d;
|
||||
// if(validnd_1_1d) begin
|
||||
// stop_temp_1[0] <= dout_scramble;
|
||||
// stop_temp_1[63:1] <= stop_temp_1[62:0];
|
||||
// RAMaddra_1_temp <= RAMaddra_1;
|
||||
// RAMaddra_2_temp <= 16'd0;
|
||||
// end
|
||||
// else begin
|
||||
// if(validnd_2_1d) begin
|
||||
// stop_temp_2[0] <= dout_scramble;
|
||||
// stop_temp_2[63:1] <= stop_temp_2[62:0];
|
||||
// RAMaddra_1_temp <= 16'd0;
|
||||
// RAMaddra_2_temp <= RAMaddra_2;
|
||||
// end
|
||||
// else begin
|
||||
// stop_temp_1 <= stop_temp_1;
|
||||
// stop_temp_2 <= stop_temp_2;
|
||||
|
||||
// RAMaddra_1_temp <= RAMaddra_1_temp;
|
||||
// RAMaddra_2_temp <= RAMaddra_2_temp;
|
||||
// end
|
||||
// end
|
||||
if(validnd_new_1d) begin
|
||||
stop_temp_new[0] <= dout_scramble;
|
||||
stop_temp_new[63:1] <= stop_temp_new[62:0];
|
||||
if(recvNetData[63:56] == 8'd2 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_temp <= RAMaddra_new_0;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd3 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_temp <= RAMaddra_new_1;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'd4 && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_temp <= RAMaddra_new_2;
|
||||
end
|
||||
else if(recvNetData[63:56] == 8'hff && recvNetData[23:0]==24'h7E5A33) begin
|
||||
RAMaddra_new_temp <= RAMaddra_new_3;
|
||||
end
|
||||
else begin
|
||||
RAMaddra_new_temp <= RAMaddra_new_temp;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
stop_temp_new <= stop_temp_new;
|
||||
|
||||
RAMaddra_new_temp <= RAMaddra_new_temp;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// reg [2:0] cnt_8 = 3'b0;
|
||||
// reg state_8 = 1'd0;
|
||||
always @(posedge clk)begin
|
||||
case(state_8)
|
||||
1'd0:begin
|
||||
if(flag_stop_0)begin
|
||||
cnt_8 <= 3'b0;
|
||||
flag_stop <= 1'b1;
|
||||
addr_stop <= addr_stop_0;
|
||||
state_8 <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_8 <= 3'b0;
|
||||
flag_stop <= 1'b0;
|
||||
addr_stop <= addr_stop;
|
||||
state_8 <= state_8;
|
||||
end
|
||||
end
|
||||
1'd1:begin
|
||||
if(cnt_8==3'd7) begin
|
||||
cnt_8 <= 3'b0;
|
||||
flag_stop <= 1'b0;
|
||||
addr_stop <= addr_stop;
|
||||
state_8 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_8 <= 3'b1+cnt_8;
|
||||
flag_stop <= 1'b1;
|
||||
addr_stop <= addr_stop;
|
||||
state_8 <= state_8;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
reg [16:0] RAMaddra_new_0_d1 = 17'd0;
|
||||
reg [16:0] RAMaddra_new_1_d1 = 17'd0;
|
||||
reg [16:0] RAMaddra_new_2_d1 = 17'd0;
|
||||
reg [16:0] RAMaddra_new_3_d1 = 17'd0;
|
||||
always@(posedge clk2)begin
|
||||
RAMaddra_new_0_d1 <= RAMaddra_new_0;
|
||||
RAMaddra_new_1_d1 <= RAMaddra_new_1;
|
||||
RAMaddra_new_2_d1 <= RAMaddra_new_2;
|
||||
RAMaddra_new_3_d1 <= RAMaddra_new_3;
|
||||
RAMaddra_write_0 <= RAMaddra_new_0_d1;
|
||||
RAMaddra_write_1 <= RAMaddra_new_1_d1;
|
||||
RAMaddra_write_2 <= RAMaddra_new_2_d1;
|
||||
RAMaddra_write_3 <= RAMaddra_new_3_d1;
|
||||
end
|
||||
|
||||
//-------------------------------------找停止位---------------------------//
|
||||
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst2)begin
|
||||
framerdy <= 1'b0;
|
||||
end else begin
|
||||
if(bagcnt == 9'd105 && validlength == 10'd1023)begin
|
||||
framerdy <= 1'b1;
|
||||
end else begin
|
||||
framerdy <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ila_ber ila_ber(
|
||||
.clk(clk),
|
||||
.probe0(rst),
|
||||
.probe1(ROMdout),
|
||||
.probe2(validnd_new_delay),
|
||||
.probe3(bercount),
|
||||
.probe4(flag_stop_0),
|
||||
.probe5(framedata_d1),
|
||||
.probe6(recvNetDataNd),
|
||||
.probe7(addr_stop_0),
|
||||
.probe8(nd_recvnet_dout_d1),
|
||||
.probe9(recvNetData),
|
||||
.probe10(dout_scramble),
|
||||
.probe11(wr_en_232),
|
||||
.probe12(framedata),
|
||||
.probe13(data_net_byte[87]),
|
||||
.probe14(RAMaddra_new_0),
|
||||
.probe15(RAMaddra_new_1)
|
||||
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+149
@@ -0,0 +1,149 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 16:01:14 07/21/2018
|
||||
// Design Name:
|
||||
// Module Name: IQmerge
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module IQmerge(
|
||||
input clk,
|
||||
input clk2,
|
||||
input rst,
|
||||
input nd,
|
||||
input framesync,
|
||||
input [9:0] dini,
|
||||
input [9:0] dinq,
|
||||
|
||||
output reg rdy = 1'b0,
|
||||
output reg ldpcsyncin = 1'b0,
|
||||
output [7:0] dout
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg [9:0] addra = 10'd0;
|
||||
reg [15:0] dina = 16'd0;
|
||||
reg [10:0] addrb = 11'd0;
|
||||
RAM_IQmerge RAM_IQmerge (
|
||||
.clka(clk), // input clka
|
||||
.wea(1'b1), // input [0 : 0] wea
|
||||
.addra(addra), // input [9 : 0] addra
|
||||
.dina(dina), // input [15 : 0] dina
|
||||
.clkb(clk2), // input clkb
|
||||
.addrb(addrb), // input [10 : 0] addrb
|
||||
.doutb(dout) // output [7 : 0] doutb
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
reg [9:0] addradelay = 10'd0;
|
||||
reg [8:0] bagcount = 9'd0;
|
||||
reg [1:0] writevalid = 2'd0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
addra <= 10'd0;
|
||||
addradelay <= 10'd0;
|
||||
dina <= 16'd0;
|
||||
writevalid <= 2'd0;
|
||||
bagcount <= 9'd0;
|
||||
end else begin
|
||||
case(writevalid)
|
||||
2'd0:begin
|
||||
if(framesync)begin
|
||||
writevalid <= 2'd1;
|
||||
end else begin
|
||||
writevalid <= 2'd0;
|
||||
end
|
||||
bagcount <= 9'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
if(nd)begin
|
||||
addradelay <= addradelay + 10'd1;
|
||||
dina <= {dinq[9:2],dini[9:2]};
|
||||
addra <= addradelay;
|
||||
if(addradelay == 10'd1023)begin
|
||||
writevalid <= 2'd2;
|
||||
end else begin
|
||||
writevalid <= 2'd1;
|
||||
end
|
||||
end else begin
|
||||
addradelay <= addradelay;
|
||||
addra <= addra;
|
||||
dina <= dina;
|
||||
writevalid <= 2'd1;
|
||||
end
|
||||
end
|
||||
2'd2:begin
|
||||
bagcount <= bagcount + 9'd1;
|
||||
if(bagcount == 9'd104)begin
|
||||
writevalid <= 2'd0;
|
||||
end else begin
|
||||
writevalid <= 2'd1;
|
||||
end
|
||||
end
|
||||
default:writevalid <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
reg readvalid = 1'b0;
|
||||
always @(posedge clk2)begin
|
||||
if(rst)begin
|
||||
addrb <= 11'd0;
|
||||
readvalid <= 1'b0;
|
||||
ldpcsyncin <= 1'b0;
|
||||
end else begin
|
||||
if(!readvalid)begin
|
||||
addrb <= 11'd0;
|
||||
if(addra == 10'd1000)begin
|
||||
ldpcsyncin <= 1'b1;
|
||||
readvalid <= 1'b1;
|
||||
end else begin
|
||||
ldpcsyncin <= 1'b0;
|
||||
readvalid <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
ldpcsyncin <= 1'b0;
|
||||
addrb <= addrb + 11'd1;
|
||||
if(addrb == 11'd2047)begin
|
||||
readvalid <= 1'b0;
|
||||
end else begin
|
||||
readvalid <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk2)begin
|
||||
rdy <= readvalid;
|
||||
end
|
||||
|
||||
/*ila_IQmerge ila_IQmerge(
|
||||
.clk(clk2),
|
||||
.probe0(clk),
|
||||
.probe1(writevalid),
|
||||
.probe2(dini[9:2]),
|
||||
.probe3(dinq[9:2]),
|
||||
.probe4(dout),
|
||||
.probe5(framesync)
|
||||
);*/
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,71 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 21:06:38
|
||||
// Design Name:
|
||||
// Module Name: Interp_half
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Interp_half(
|
||||
input clk,
|
||||
input [9:0] din_p1,
|
||||
input [9:0] din_t0,
|
||||
input [9:0] din_n1,
|
||||
input [9:0] din_n2,
|
||||
|
||||
output reg [9:0] dout
|
||||
|
||||
);
|
||||
|
||||
wire [13:0] multquartert0;
|
||||
wire [13:0] multquartern1;
|
||||
CN1_half CT0_half (.CLK(clk), .A(din_t0), .P(multquartert0));
|
||||
CN1_half CN1_half (.CLK(clk), .A(din_n1), .P(multquartern1));
|
||||
|
||||
reg [9:0] multquarterp1 = 10'd0;
|
||||
reg [9:0] multquartern2 = 10'd0;
|
||||
always @(posedge clk)begin
|
||||
multquarterp1 <= din_p1;
|
||||
multquartern2 <= din_n2;
|
||||
end
|
||||
|
||||
reg [14:0] sumquarter1 = 15'd0;
|
||||
reg [14:0] sumquarter2 = 15'd0;
|
||||
always @(posedge clk)begin
|
||||
sumquarter1 <= {multquartert0[13],multquartert0}-{{5{multquarterp1[9]}},multquarterp1};
|
||||
sumquarter2 <= {multquartern1[13],multquartern1}-{{5{multquartern2[9]}},multquartern2};
|
||||
end
|
||||
|
||||
|
||||
reg [15:0] sumquarter3 = 16'd0;
|
||||
always @(posedge clk)begin
|
||||
sumquarter3 <= {sumquarter2[14],sumquarter2}+{sumquarter1[14],sumquarter1};
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(sumquarter3[15:13]==3'b111||sumquarter3[15:13]==3'b000)begin
|
||||
dout <= sumquarter3[13:4];
|
||||
end else begin
|
||||
dout <= (sumquarter3[15]==1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,69 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 21:06:38
|
||||
// Design Name:
|
||||
// Module Name: Interp_quarter
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Interp_quarter(
|
||||
input clk,
|
||||
input [9:0] din_p1,
|
||||
input [9:0] din_t0,
|
||||
input [9:0] din_n1,
|
||||
input [9:0] din_n2,
|
||||
|
||||
output reg [9:0] dout
|
||||
|
||||
);
|
||||
|
||||
wire [13:0] multquartern2;
|
||||
wire [15:0] multquartern1;
|
||||
wire [16:0] multquartert0;
|
||||
wire [13:0] multquarterp1;
|
||||
CN2 CN2_quarter (.CLK(clk), .A(din_p1), .P(multquartern2));
|
||||
CN1 CN1_quarter (.CLK(clk), .A(din_t0), .P(multquartern1));
|
||||
CT0 CT0_quarter (.CLK(clk), .A(din_n1), .P(multquartert0));
|
||||
CP1 CP1_quarter (.CLK(clk), .A(din_n2), .P(multquarterp1));
|
||||
|
||||
|
||||
|
||||
reg [16:0] sumquarter1 = 17'd0;
|
||||
reg [17:0] sumquarter2 = 18'd0;
|
||||
always @(posedge clk)begin
|
||||
sumquarter1 <= {{3{multquartern2[13]}},multquartern2}+{multquartern1[15],multquartern1};
|
||||
sumquarter2 <= {{4{multquarterp1[13]}},multquarterp1}+{multquartert0[16],multquartert0};
|
||||
end
|
||||
|
||||
|
||||
reg [18:0] sumquarter3 = 19'd0;
|
||||
always @(posedge clk)begin
|
||||
sumquarter3 <= {{2{sumquarter1[16]}},sumquarter1}+{sumquarter2[17],sumquarter2};
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(sumquarter3[18:16]==3'b111||sumquarter3[18:16]==3'b000)begin
|
||||
dout <= sumquarter3[16:7];
|
||||
end else begin
|
||||
dout <= (sumquarter3[18]==1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,100 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 21:03:55
|
||||
// Design Name:
|
||||
// Module Name: Interpolation
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Interpolation(
|
||||
input clk,
|
||||
input [9:0] dini,
|
||||
input [9:0] dinq,
|
||||
|
||||
input framesync,
|
||||
output reg framesync_Interpolation = 1'd0,
|
||||
|
||||
output reg [9:0] doutiA = 10'd0,
|
||||
output reg [9:0] doutqA = 10'd0,
|
||||
output [9:0] doutiB,
|
||||
output [9:0] doutqB,
|
||||
output [9:0] doutiC,
|
||||
output [9:0] doutqC,
|
||||
output [9:0] doutiD,
|
||||
output [9:0] doutqD
|
||||
);
|
||||
|
||||
reg [9:0] dini_p1 = 10'd0;
|
||||
reg [9:0] dini_t0 = 10'd0;
|
||||
reg [9:0] dini_n1 = 10'd0;
|
||||
reg [9:0] dini_n2 = 10'd0;
|
||||
reg [9:0] dini_n3 = 10'd0;
|
||||
reg [9:0] dini_n4 = 10'd0;
|
||||
|
||||
|
||||
reg [9:0] dinq_p1 = 10'd0;
|
||||
reg [9:0] dinq_t0 = 10'd0;
|
||||
reg [9:0] dinq_n1 = 10'd0;
|
||||
reg [9:0] dinq_n2 = 10'd0;
|
||||
reg [9:0] dinq_n3 = 10'd0;
|
||||
reg [9:0] dinq_n4 = 10'd0;
|
||||
|
||||
reg [0:0] framesync_p1 = 1'd0;
|
||||
reg [0:0] framesync_t0 = 1'd0;
|
||||
reg [0:0] framesync_n1 = 1'd0;
|
||||
reg [0:0] framesync_n2 = 1'd0;
|
||||
reg [0:0] framesync_n3 = 1'd0;
|
||||
reg [0:0] framesync_n4 = 1'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
dini_p1 <= dini;
|
||||
dini_t0 <= dini_p1;
|
||||
dini_n1 <= dini_t0;
|
||||
dini_n2 <= dini_n1;
|
||||
dini_n3 <= dini_n2;
|
||||
dini_n4 <= dini_n3;
|
||||
doutiA <= dini_n4;
|
||||
|
||||
dinq_p1 <= dinq;
|
||||
dinq_t0 <= dinq_p1;
|
||||
dinq_n1 <= dinq_t0;
|
||||
dinq_n2 <= dinq_n1;
|
||||
dinq_n3 <= dinq_n2;
|
||||
dinq_n4 <= dinq_n3;
|
||||
doutqA <= dinq_n4;
|
||||
|
||||
framesync_p1 <= framesync;
|
||||
framesync_t0 <= framesync_p1;
|
||||
framesync_n1 <= framesync_t0;
|
||||
framesync_n2 <= framesync_n1;
|
||||
framesync_n3 <= framesync_n2;
|
||||
framesync_n4 <= framesync_n3;
|
||||
framesync_Interpolation <= framesync_n4;
|
||||
end
|
||||
|
||||
|
||||
|
||||
Interp_quarter Interp_quarteri (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiB));
|
||||
Interp_quarter Interp_quarterq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqB));
|
||||
|
||||
Interp_half Interp_halfi (.clk(clk), .din_p1(dini_p1), .din_t0(dini_t0), .din_n1(dini_n1), .din_n2(dini_n2), .dout(doutiC));
|
||||
Interp_half Interp_halfq (.clk(clk), .din_p1(dinq_p1), .din_t0(dinq_t0), .din_n1(dinq_n1), .din_n2(dinq_n2), .dout(doutqC));
|
||||
|
||||
Interp_quarter Interp_quarteri3 (.clk(clk), .din_p1(dini_n2), .din_t0(dini_n1), .din_n1(dini_t0), .din_n2(dini_p1), .dout(doutiD));
|
||||
Interp_quarter Interp_quarterq3 (.clk(clk), .din_p1(dinq_n2), .din_t0(dinq_n1), .din_n1(dinq_t0), .din_n2(dinq_p1), .dout(doutqD));
|
||||
|
||||
endmodule
|
||||
|
||||
+1074
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,193 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: LDPC_TopManage_2
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module LDPC_TopManage_2 #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk, //工作时钟,100MHz
|
||||
input Rst, //同步复位信号,高有效
|
||||
input FrameSync_TM, //帧同步标志,高脉冲
|
||||
input Nd_TM, //译码输入数据有效标志,高有效
|
||||
input [WIDTH-1:0] Din_TM, //译码输入数据,软信息
|
||||
//A
|
||||
output FrameSync_A_TM, //帧同步标志,高脉冲
|
||||
output Nd_A_TM, //译码输入数据有效标志,高有效
|
||||
output [WIDTH-1:0] Din_A_TM, //译码输入数据,软信息
|
||||
//B
|
||||
output FrameSync_B_TM, //帧同步标志,高脉冲
|
||||
output Nd_B_TM, //译码输入数据有效标志,高有效
|
||||
output [WIDTH-1:0] Din_B_TM, //译码输入数据,软信息
|
||||
// flag A
|
||||
input LDPC_SyncOut_A_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
input Rdy_A_TM, //译码输出信号有效标志,高有效
|
||||
input [ 0:0] LDPC_Dout_A_TM, //译码输出信号
|
||||
input [ 8:0] good_frames_A_TM, //译码好帧计数
|
||||
input [ 8:0] bad_frames_A_TM, //译码坏帧计数
|
||||
input [ 8:0] total_frames_A_TM, //译码总帧数计数
|
||||
//flag B
|
||||
input LDPC_SyncOut_B_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
input Rdy_B_TM, //译码输出信号有效标志,高有效
|
||||
input [ 0:0] LDPC_Dout_B_TM, //译码输出信号
|
||||
input [ 8:0] good_frames_B_TM, //译码好帧计数
|
||||
input [ 8:0] bad_frames_B_TM, //译码坏帧计数
|
||||
input [ 8:0] total_frames_B_TM, //译码总帧数计数
|
||||
//result
|
||||
output LDPC_SyncOut_TM, //LDPC 模块帧同步输出信号,高脉冲,指示帧起点
|
||||
output Rdy_TM, //译码输出信号有效标志,高有效
|
||||
output [ 0:0] LDPC_Dout_TM, //译码输出信号
|
||||
output [ 8:0] good_frames_TM, //译码好帧计数
|
||||
output [ 8:0] bad_frames_TM, //译码坏帧计数
|
||||
output [ 8:0] total_frames_TM //译码总帧数计数
|
||||
);
|
||||
|
||||
reg FrameSync_TM_reg0, FrameSync_TM_reg1;
|
||||
reg Nd_TM_reg0, Nd_TM_reg1;
|
||||
reg [WIDTH-1:0] Din_TM_reg0, Din_TM_reg1;
|
||||
|
||||
//******输入过程控制
|
||||
always @(posedge clk) begin //接收数据缓存过程
|
||||
FrameSync_TM_reg0 <= FrameSync_TM;
|
||||
FrameSync_TM_reg1 <= FrameSync_TM_reg0;
|
||||
Nd_TM_reg0 <= Nd_TM;
|
||||
Nd_TM_reg1 <= Nd_TM_reg0;
|
||||
Din_TM_reg0 <= Din_TM;
|
||||
Din_TM_reg1 <= Din_TM_reg0;
|
||||
end
|
||||
|
||||
reg [0:0] flag_switch_in = 1'b1;
|
||||
always @(posedge clk) begin //输入乒乓控制过程
|
||||
if (Rst) begin
|
||||
flag_switch_in <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
if (FrameSync_TM) begin
|
||||
flag_switch_in <= ~flag_switch_in;
|
||||
end
|
||||
else flag_switch_in <= flag_switch_in;
|
||||
end
|
||||
end
|
||||
|
||||
assign FrameSync_A_TM = (flag_switch_in == 1'b0) ? FrameSync_TM_reg1 : 1'b0;
|
||||
assign Nd_A_TM = (flag_switch_in == 1'b0) ? Nd_TM_reg1 : 1'b0;
|
||||
assign Din_A_TM = (flag_switch_in == 1'b0) ? Din_TM_reg1 : 8'd0;
|
||||
|
||||
assign FrameSync_B_TM = (flag_switch_in == 1'b1) ? FrameSync_TM_reg1 : 1'b0;
|
||||
assign Nd_B_TM = (flag_switch_in == 1'b1) ? Nd_TM_reg1 : 1'b0;
|
||||
assign Din_B_TM = (flag_switch_in == 1'b1) ? Din_TM_reg1 : 8'd0;
|
||||
|
||||
reg LDPC_SyncOut_A_TM_reg0, LDPC_SyncOut_A_TM_reg1;
|
||||
reg Rdy_A_TM_reg0, Rdy_A_TM_reg1;
|
||||
reg [0:0] LDPC_Dout_A_TM_reg0, LDPC_Dout_A_TM_reg1;
|
||||
reg [8:0] good_frames_A_TM_reg0, good_frames_A_TM_reg1;
|
||||
reg [8:0] bad_frames_A_TM_reg0, bad_frames_A_TM_reg1;
|
||||
reg [8:0] total_frames_A_TM_reg0, total_frames_A_TM_reg1;
|
||||
|
||||
reg LDPC_SyncOut_B_TM_reg0, LDPC_SyncOut_B_TM_reg1;
|
||||
reg Rdy_B_TM_reg0, Rdy_B_TM_reg1;
|
||||
reg [0:0] LDPC_Dout_B_TM_reg0, LDPC_Dout_B_TM_reg1;
|
||||
reg [8:0] good_frames_B_TM_reg0, good_frames_B_TM_reg1;
|
||||
reg [8:0] bad_frames_B_TM_reg0, bad_frames_B_TM_reg1;
|
||||
reg [8:0] total_frames_B_TM_reg0, total_frames_B_TM_reg1;
|
||||
|
||||
//******输入过程控制
|
||||
always @(posedge clk) begin //输出数据缓存过程
|
||||
if (Rst) begin
|
||||
LDPC_SyncOut_A_TM_reg0 <= 1'b0;
|
||||
LDPC_SyncOut_A_TM_reg1 <= 1'b0;
|
||||
Rdy_A_TM_reg0 <= 1'b0;
|
||||
Rdy_A_TM_reg1 <= 1'b0;
|
||||
LDPC_Dout_A_TM_reg0 <= 1'b0;
|
||||
LDPC_Dout_A_TM_reg1 <= 1'b0;
|
||||
good_frames_A_TM_reg0 <= 9'd0;
|
||||
good_frames_A_TM_reg1 <= 9'd0;
|
||||
bad_frames_A_TM_reg0 <= 9'd0;
|
||||
bad_frames_A_TM_reg1 <= 9'd0;
|
||||
total_frames_A_TM_reg0 <= 9'd0;
|
||||
total_frames_A_TM_reg1 <= 9'd0;
|
||||
|
||||
LDPC_SyncOut_B_TM_reg0 <= 1'b0;
|
||||
LDPC_SyncOut_B_TM_reg1 <= 1'b0;
|
||||
Rdy_B_TM_reg0 <= 1'b0;
|
||||
Rdy_B_TM_reg1 <= 1'b0;
|
||||
LDPC_Dout_B_TM_reg0 <= 1'b0;
|
||||
LDPC_Dout_B_TM_reg1 <= 1'b0;
|
||||
good_frames_B_TM_reg0 <= 9'd0;
|
||||
good_frames_B_TM_reg1 <= 9'd0;
|
||||
bad_frames_B_TM_reg0 <= 9'd0;
|
||||
bad_frames_B_TM_reg1 <= 9'd0;
|
||||
total_frames_B_TM_reg0 <= 9'd0;
|
||||
total_frames_B_TM_reg1 <= 9'd0;
|
||||
end
|
||||
else begin
|
||||
LDPC_SyncOut_A_TM_reg0 <= LDPC_SyncOut_A_TM;
|
||||
LDPC_SyncOut_A_TM_reg1 <= LDPC_SyncOut_A_TM_reg0;
|
||||
Rdy_A_TM_reg0 <= Rdy_A_TM;
|
||||
Rdy_A_TM_reg1 <= Rdy_A_TM_reg0;
|
||||
LDPC_Dout_A_TM_reg0 <= LDPC_Dout_A_TM;
|
||||
LDPC_Dout_A_TM_reg1 <= LDPC_Dout_A_TM_reg0;
|
||||
good_frames_A_TM_reg0 <= good_frames_A_TM;
|
||||
good_frames_A_TM_reg1 <= good_frames_A_TM_reg0;
|
||||
bad_frames_A_TM_reg0 <= bad_frames_A_TM;
|
||||
bad_frames_A_TM_reg1 <= bad_frames_A_TM_reg0;
|
||||
total_frames_A_TM_reg0 <= total_frames_A_TM;
|
||||
total_frames_A_TM_reg1 <= total_frames_A_TM_reg0;
|
||||
|
||||
LDPC_SyncOut_B_TM_reg0 <= LDPC_SyncOut_B_TM;
|
||||
LDPC_SyncOut_B_TM_reg1 <= LDPC_SyncOut_B_TM_reg0;
|
||||
Rdy_B_TM_reg0 <= Rdy_B_TM;
|
||||
Rdy_B_TM_reg1 <= Rdy_B_TM_reg0;
|
||||
LDPC_Dout_B_TM_reg0 <= LDPC_Dout_B_TM;
|
||||
LDPC_Dout_B_TM_reg1 <= LDPC_Dout_B_TM_reg0;
|
||||
good_frames_B_TM_reg0 <= good_frames_B_TM;
|
||||
good_frames_B_TM_reg1 <= good_frames_B_TM_reg0;
|
||||
bad_frames_B_TM_reg0 <= bad_frames_B_TM;
|
||||
bad_frames_B_TM_reg1 <= bad_frames_B_TM_reg0;
|
||||
total_frames_B_TM_reg0 <= total_frames_B_TM;
|
||||
total_frames_B_TM_reg1 <= total_frames_B_TM_reg0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [0:0] flag_switch_out = 1'b1;
|
||||
always @(posedge clk) begin //输出乒乓控制过程
|
||||
if (Rst) begin
|
||||
flag_switch_out <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
if (LDPC_SyncOut_A_TM || LDPC_SyncOut_B_TM) flag_switch_out <= ~flag_switch_out;
|
||||
else flag_switch_out <= flag_switch_out;
|
||||
end
|
||||
end
|
||||
|
||||
assign LDPC_SyncOut_TM = (flag_switch_out == 1'b0) ? LDPC_SyncOut_A_TM_reg1 : LDPC_SyncOut_B_TM_reg1;
|
||||
assign Rdy_TM = (flag_switch_out == 1'b0) ? Rdy_A_TM_reg1 : Rdy_B_TM_reg1;
|
||||
assign LDPC_Dout_TM = (flag_switch_out == 1'b0) ? LDPC_Dout_A_TM_reg1 : LDPC_Dout_B_TM_reg1;
|
||||
|
||||
assign good_frames_TM = good_frames_B_TM_reg1 + good_frames_A_TM_reg1;
|
||||
assign bad_frames_TM = bad_frames_B_TM_reg1 + bad_frames_A_TM_reg1;
|
||||
assign total_frames_TM = total_frames_B_TM_reg1 + total_frames_A_TM_reg1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:44 11/14/2019
|
||||
// Design Name:
|
||||
// Module Name: MF_Top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module MF_Top (
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input [11:0] dini,
|
||||
input [11:0] dinq,
|
||||
input start,
|
||||
|
||||
output reg [9:0] matchfilterout_i = 10'd0,
|
||||
output reg [9:0] matchfilterout_q = 10'd0,
|
||||
output reg MF_rdy,
|
||||
output reg MF_rst
|
||||
);
|
||||
|
||||
wire s_axis_data_tvalid_i;
|
||||
wire s_axis_data_tready_i;
|
||||
wire m_axis_data_tvalid_i;
|
||||
wire [31:0] MF_m_axis_data_tdata_i;
|
||||
|
||||
assign s_axis_data_tvalid_i = start;
|
||||
MF12p5_12bit MF12p5_12bit_i (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid_i), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready_i), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid_i), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (MF_m_axis_data_tdata_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
wire s_axis_data_tvalid_q;
|
||||
wire s_axis_data_tready_q;
|
||||
wire m_axis_data_tvalid_q;
|
||||
wire [31:0] MF_m_axis_data_tdata_q;
|
||||
|
||||
assign s_axis_data_tvalid_q = start;
|
||||
MF12p5_12bit MF12p5_12bit_q (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid_q), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready_q), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid_q), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (MF_m_axis_data_tdata_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
//截位：结果为MF_m_axis_data_tdata_i/q[25:0]
|
||||
//低位截位15bit，高位截位1bit，得10bit宽结果
|
||||
always @(posedge clk) begin
|
||||
if (MF_m_axis_data_tdata_i[25:24] == 2'b00 || MF_m_axis_data_tdata_i[25:24] == 2'b11) begin
|
||||
matchfilterout_i <= MF_m_axis_data_tdata_i[24:15];
|
||||
end
|
||||
else begin
|
||||
matchfilterout_i <= (MF_m_axis_data_tdata_i[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
|
||||
if (MF_m_axis_data_tdata_q[25:24] == 2'b00 || MF_m_axis_data_tdata_q[25:24] == 2'b11) begin
|
||||
matchfilterout_q <= MF_m_axis_data_tdata_q[24:15];
|
||||
end
|
||||
else begin
|
||||
matchfilterout_q <= (MF_m_axis_data_tdata_q[25] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
reg MF_rdy_d1;
|
||||
always @(posedge clk) begin
|
||||
MF_rdy_d1 <= MF_rdy;
|
||||
if (rst) begin
|
||||
MF_rdy <= 1'b0;
|
||||
MF_rst <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
MF_rdy <= start;
|
||||
if ((MF_rdy == 1'b1) && (MF_rdy_d1 == 1'b0)) begin
|
||||
MF_rst <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
MF_rst <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//------DEBUG模块------//
|
||||
`ifdef MF_debug
|
||||
|
||||
//ILA
|
||||
/*ila_16x8 ila_MF_inst(
|
||||
.clk(clk),
|
||||
.probe0(dini),
|
||||
.probe1(dinq),
|
||||
.probe2(start),
|
||||
.probe3(matchfilterout_i),
|
||||
.probe4(matchfilterout_q),
|
||||
.probe5(MF_rdy),
|
||||
.probe6(8'b0),
|
||||
.probe7(8'b0)
|
||||
);*/
|
||||
|
||||
|
||||
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module MagnitudeEstimator #(
|
||||
parameter VEC_WIDTH = 21
|
||||
|
||||
@@ -0,0 +1,385 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: Message_Store
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Message_Store #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input rst_MS,
|
||||
input framesync_MS, //帧同步标志，高脉冲
|
||||
input nd_MS, //译码输入数据有效标志，高有效
|
||||
input [WIDTH-1:0] din_MS, //译码输入软信息
|
||||
input [ 0:0] oe_MS, //使能输出信号，高脉冲
|
||||
|
||||
output deal_end_MS, //转换完成标志
|
||||
output syncout_MS, //高脉冲
|
||||
output rdy_MS, //高有效的连续信号
|
||||
output reg [WIDTH-1:0] dout01_MS = 8'd0, // 输出数据
|
||||
output reg [WIDTH-1:0] dout02_MS = 8'd0,
|
||||
output reg [WIDTH-1:0] dout03_MS = 8'd0,
|
||||
output reg [WIDTH-1:0] dout04_MS = 8'd0
|
||||
);
|
||||
reg [10:0] cnt_MS = 11'd0;
|
||||
reg flag_end = 1'd0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
flag_end <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (framesync_MS) flag_end <= 1'd1;
|
||||
else if (nd_MS && cnt_MS == 11'd2047) flag_end <= 1'd0;
|
||||
else flag_end <= flag_end;
|
||||
end
|
||||
end
|
||||
|
||||
// 产生基准计数
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
cnt_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_end) begin
|
||||
if (nd_MS) cnt_MS <= cnt_MS + 11'd1;
|
||||
else begin
|
||||
cnt_MS <= cnt_MS;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_MS <= cnt_MS;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg wea1_01 = 1'd0, wea1_02 = 1'd0, wea1_03 = 1'd0, wea1_04 = 1'd0, wea2_01 = 1'd0, wea2_02 = 1'd0, wea2_03 = 1'd0, wea2_04 = 1'd0;
|
||||
reg [8:0] addr_wr1_01 = 9'd511, addr_wr1_02 = 9'd511, addr_wr1_03 = 9'd511, addr_wr1_04 = 9'd511, addr_wr2_01 = 9'd511, addr_wr2_02 = 9'd511, addr_wr2_03 = 9'd511, addr_wr2_04 = 9'd511;
|
||||
reg [WIDTH-1:0] din1_01 = 8'd0, din1_02 = 8'd0, din1_03 = 8'd0, din1_04 = 8'd0, din2_01 = 8'd0, din2_02 = 8'd0, din2_03 = 8'd0, din2_04 = 8'd0;
|
||||
reg [8:0] addr_rd1_01 = 9'd511, addr_rd1_02 = 9'd511, addr_rd1_03 = 9'd511, addr_rd1_04 = 9'd511, addr_rd2_01 = 9'd511, addr_rd2_02 = 9'd511, addr_rd2_03 = 9'd511, addr_rd2_04 = 9'd511;
|
||||
wire [WIDTH-1:0] dout1_01, dout1_02, dout1_03, dout1_04, dout2_01, dout2_02, dout2_03, dout2_04;
|
||||
|
||||
RAM_512_8 Lp1_01 (
|
||||
.clka (clk),
|
||||
.wea (wea1_01),
|
||||
.addra(addr_wr1_01),
|
||||
.dina (din1_01),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_01),
|
||||
.doutb(dout1_01)
|
||||
);
|
||||
RAM_512_8 Lp1_02 (
|
||||
.clka (clk),
|
||||
.wea (wea1_02),
|
||||
.addra(addr_wr1_02),
|
||||
.dina (din1_02),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_02),
|
||||
.doutb(dout1_02)
|
||||
);
|
||||
RAM_512_8 Lp1_03 (
|
||||
.clka (clk),
|
||||
.wea (wea1_03),
|
||||
.addra(addr_wr1_03),
|
||||
.dina (din1_03),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_03),
|
||||
.doutb(dout1_03)
|
||||
);
|
||||
RAM_512_8 Lp1_04 (
|
||||
.clka (clk),
|
||||
.wea (wea1_04),
|
||||
.addra(addr_wr1_04),
|
||||
.dina (din1_04),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd1_04),
|
||||
.doutb(dout1_04)
|
||||
);
|
||||
RAM_512_8 Lp2_01 (
|
||||
.clka (clk),
|
||||
.wea (wea2_01),
|
||||
.addra(addr_wr2_01),
|
||||
.dina (din2_01),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_01),
|
||||
.doutb(dout2_01)
|
||||
);
|
||||
RAM_512_8 Lp2_02 (
|
||||
.clka (clk),
|
||||
.wea (wea2_02),
|
||||
.addra(addr_wr2_02),
|
||||
.dina (din2_02),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_02),
|
||||
.doutb(dout2_02)
|
||||
);
|
||||
RAM_512_8 Lp2_03 (
|
||||
.clka (clk),
|
||||
.wea (wea2_03),
|
||||
.addra(addr_wr2_03),
|
||||
.dina (din2_03),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_03),
|
||||
.doutb(dout2_03)
|
||||
);
|
||||
RAM_512_8 Lp2_04 (
|
||||
.clka (clk),
|
||||
.wea (wea2_04),
|
||||
.addra(addr_wr2_04),
|
||||
.dina (din2_04),
|
||||
.clkb (clk),
|
||||
.addrb(addr_rd2_04),
|
||||
.doutb(dout2_04)
|
||||
);
|
||||
|
||||
reg flag_switch_MS = 1'd0;
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) flag_switch_MS <= 1'd0;
|
||||
else begin
|
||||
if (nd_MS && cnt_MS == 11'd2047) flag_switch_MS <= ~flag_switch_MS;
|
||||
else flag_switch_MS <= flag_switch_MS;
|
||||
end
|
||||
end
|
||||
|
||||
// 乒乓写缓存过程
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
wea1_01 <= 1'd0;
|
||||
wea1_02 <= 1'd0;
|
||||
wea1_03 <= 1'd0;
|
||||
wea1_04 <= 1'd0;
|
||||
wea2_01 <= 1'd0;
|
||||
wea2_02 <= 1'd0;
|
||||
wea2_03 <= 1'd0;
|
||||
wea2_04 <= 1'd0;
|
||||
addr_wr1_01 <= 9'd511;
|
||||
addr_wr1_02 <= 9'd511;
|
||||
addr_wr1_03 <= 9'd511;
|
||||
addr_wr1_04 <= 9'd511;
|
||||
addr_wr2_01 <= 9'd511;
|
||||
addr_wr2_02 <= 9'd511;
|
||||
addr_wr2_03 <= 9'd511;
|
||||
addr_wr2_04 <= 9'd511;
|
||||
din1_01 <= 8'd0;
|
||||
din1_02 <= 8'd0;
|
||||
din1_03 <= 8'd0;
|
||||
din1_04 <= 8'd0;
|
||||
din2_01 <= 8'd0;
|
||||
din2_02 <= 8'd0;
|
||||
din2_03 <= 8'd0;
|
||||
din2_04 <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (nd_MS) //所有的写操作均在nd_MS有效时进行
|
||||
if (flag_switch_MS == 1'd0) begin //写第一个缓存区
|
||||
if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
|
||||
wea1_01 <= 1'd1;
|
||||
addr_wr1_01 <= addr_wr1_01 + 9'd1;
|
||||
din1_01 <= din_MS;
|
||||
end
|
||||
else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
|
||||
wea1_02 <= 1'd1;
|
||||
addr_wr1_02 <= addr_wr1_02 + 9'd1;
|
||||
din1_02 <= din_MS;
|
||||
wea1_01 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
|
||||
wea1_03 <= 1'd1;
|
||||
addr_wr1_03 <= addr_wr1_03 + 9'd1;
|
||||
din1_03 <= din_MS;
|
||||
wea1_02 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
|
||||
wea1_04 <= 1'd1;
|
||||
addr_wr1_04 <= addr_wr1_04 + 9'd1;
|
||||
din1_04 <= din_MS;
|
||||
wea1_03 <= 1'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (cnt_MS >= 11'd0 && cnt_MS < 11'd512) begin
|
||||
wea2_01 <= 1'd1;
|
||||
addr_wr2_01 <= addr_wr2_01 + 9'd1;
|
||||
din2_01 <= din_MS;
|
||||
end
|
||||
else if (cnt_MS >= 11'd512 && cnt_MS < 11'd1024) begin
|
||||
wea2_02 <= 1'd1;
|
||||
addr_wr2_02 <= addr_wr2_02 + 9'd1;
|
||||
din2_02 <= din_MS;
|
||||
wea2_01 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1024 && cnt_MS < 11'd1536) begin
|
||||
wea2_03 <= 1'd1;
|
||||
addr_wr2_03 <= addr_wr2_03 + 9'd1;
|
||||
din2_03 <= din_MS;
|
||||
wea2_02 <= 1'd0;
|
||||
end
|
||||
else if (cnt_MS >= 11'd1536 && cnt_MS <= 11'd2047) begin
|
||||
wea2_04 <= 1'd1;
|
||||
addr_wr2_04 <= addr_wr2_04 + 9'd1;
|
||||
din2_04 <= din_MS;
|
||||
wea2_03 <= 1'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
wea1_01 <= 1'd0;
|
||||
wea1_02 <= 1'd0;
|
||||
wea1_03 <= 1'd0;
|
||||
wea1_04 <= 1'd0;
|
||||
wea2_01 <= 1'd0;
|
||||
wea2_02 <= 1'd0;
|
||||
wea2_03 <= 1'd0;
|
||||
wea2_04 <= 1'd0;
|
||||
din1_01 <= 8'd0;
|
||||
din1_02 <= 8'd0;
|
||||
din1_03 <= 8'd0;
|
||||
din1_04 <= 8'd0;
|
||||
din2_01 <= 8'd0;
|
||||
din2_02 <= 8'd0;
|
||||
din2_03 <= 8'd0;
|
||||
din2_04 <= 8'd0;
|
||||
addr_wr1_01 <= addr_wr1_01;
|
||||
addr_wr1_02 <= addr_wr1_02;
|
||||
addr_wr1_03 <= addr_wr1_03;
|
||||
addr_wr1_04 <= addr_wr1_04;
|
||||
addr_wr2_01 <= addr_wr2_01;
|
||||
addr_wr2_02 <= addr_wr2_02;
|
||||
addr_wr2_03 <= addr_wr2_03;
|
||||
addr_wr2_04 <= addr_wr2_04;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg flag_out = 1'd0;
|
||||
reg [10:0] cnt_out_MS = 11'd0;
|
||||
// 产生输出计数器
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
flag_out <= 1'd0;
|
||||
cnt_out_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (oe_MS) begin
|
||||
flag_out <= 1'd1;
|
||||
cnt_out_MS <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_out && cnt_out_MS < 11'd540) begin
|
||||
cnt_out_MS <= cnt_out_MS + 11'd1;
|
||||
end
|
||||
else begin
|
||||
flag_out <= 1'd0;
|
||||
cnt_out_MS <= cnt_out_MS;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// 控制输出缓存地址
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
addr_rd1_01 <= 9'd511;
|
||||
addr_rd1_02 <= 9'd511;
|
||||
addr_rd1_03 <= 9'd511;
|
||||
addr_rd1_04 <= 9'd511;
|
||||
addr_rd2_01 <= 9'd511;
|
||||
addr_rd2_02 <= 9'd511;
|
||||
addr_rd2_03 <= 9'd511;
|
||||
addr_rd2_04 <= 9'd511;
|
||||
end
|
||||
else begin
|
||||
if (flag_switch_MS) begin // 输出缓存１中的数据
|
||||
if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
|
||||
addr_rd1_01 <= addr_rd1_01 + 9'd1;
|
||||
addr_rd1_02 <= addr_rd1_02 + 9'd1;
|
||||
addr_rd1_03 <= addr_rd1_03 + 9'd1;
|
||||
addr_rd1_04 <= addr_rd1_04 + 9'd1;
|
||||
end
|
||||
else begin
|
||||
addr_rd1_01 <= 9'd511;
|
||||
addr_rd1_02 <= 9'd511;
|
||||
addr_rd1_03 <= 9'd511;
|
||||
addr_rd1_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
else begin // 输出缓存2中的数据
|
||||
if (cnt_out_MS >= 11'd1 && cnt_out_MS <= 11'd512) begin
|
||||
addr_rd2_01 <= addr_rd2_01 + 9'd1;
|
||||
addr_rd2_02 <= addr_rd2_02 + 9'd1;
|
||||
addr_rd2_03 <= addr_rd2_03 + 9'd1;
|
||||
addr_rd2_04 <= addr_rd2_04 + 9'd1;
|
||||
end
|
||||
else begin
|
||||
addr_rd2_01 <= 9'd511;
|
||||
addr_rd2_02 <= 9'd511;
|
||||
addr_rd2_03 <= 9'd511;
|
||||
addr_rd2_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 输出缓存数据到译码器
|
||||
always @(posedge clk) begin
|
||||
if (rst_MS) begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (flag_switch_MS) begin
|
||||
if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
|
||||
dout01_MS <= dout1_01;
|
||||
dout02_MS <= dout1_02;
|
||||
dout03_MS <= dout1_03;
|
||||
dout04_MS <= dout1_04;
|
||||
end
|
||||
else begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (cnt_out_MS >= 11'd5 && cnt_out_MS <= 11'd516) begin
|
||||
dout01_MS <= dout2_01;
|
||||
dout02_MS <= dout2_02;
|
||||
dout03_MS <= dout2_03;
|
||||
dout04_MS <= dout2_04;
|
||||
end
|
||||
else begin
|
||||
dout01_MS <= 8'd0;
|
||||
dout02_MS <= 8'd0;
|
||||
dout03_MS <= 8'd0;
|
||||
dout04_MS <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
// 输出处理完成、同步脉冲和使能标志
|
||||
assign deal_end_MS = (cnt_MS == 11'd2047 && nd_MS) ? 1'd1 : 1'd0;
|
||||
assign syncout_MS = (cnt_out_MS == 11'd5) ? 1'd1 : 1'd0;
|
||||
assign rdy_MS = (cnt_out_MS >= 11'd6 && cnt_out_MS <= 11'd517) ? 1'd1 : 1'd0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,187 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/12/20 15:37:19
|
||||
// Design Name:
|
||||
// Module Name: Noise_Estimate
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module Noise_Estimate(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input nd_pilot2,
|
||||
input [9:0] pilot_noisei,
|
||||
input [9:0] pilot_noiseq,
|
||||
|
||||
output reg nd_EstNoise = 1'd0,
|
||||
output reg [27:0] EstNoise_i = 28'd0,
|
||||
output reg [27:0] EstNoise_q = 28'd0 //应当为0
|
||||
|
||||
);
|
||||
|
||||
//----------------------------------------共轭相乘，延时为6clk-----------------------------------//
|
||||
reg [9:0] noisei = 10'd0;
|
||||
reg [9:0] noiseq = 10'd0;
|
||||
reg [9:0] noiseqh = 10'd0;
|
||||
reg nd_noise_d0 = 1'd0;
|
||||
reg nd_noise_d1 = 1'd0;
|
||||
reg nd_noise_d2 = 1'd0;
|
||||
reg nd_noise_d3 = 1'd0;
|
||||
reg nd_noise_d4 = 1'd0;
|
||||
reg nd_noise_d5 = 1'd0;
|
||||
reg nd_noise_d6 = 1'd0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
noisei <= 10'd0;
|
||||
noiseq <= 10'd0;
|
||||
noiseqh <= 10'd0;
|
||||
nd_noise_d0 <= 1'd0;
|
||||
nd_noise_d1 <= 1'd0;
|
||||
nd_noise_d2 <= 1'd0;
|
||||
nd_noise_d3 <= 1'd0;
|
||||
nd_noise_d4 <= 1'd0;
|
||||
nd_noise_d5 <= 1'd0;
|
||||
nd_noise_d6 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
noisei <= pilot_noisei;
|
||||
noiseq <= pilot_noiseq;
|
||||
if(pilot_noiseq==10'd512) noiseqh <= 10'd511;
|
||||
else noiseqh <= -pilot_noiseq;
|
||||
nd_noise_d0 <= nd_pilot2;
|
||||
nd_noise_d1 <= nd_noise_d0;
|
||||
nd_noise_d2 <= nd_noise_d1;
|
||||
nd_noise_d3 <= nd_noise_d2;
|
||||
nd_noise_d4 <= nd_noise_d3;
|
||||
nd_noise_d5 <= nd_noise_d4;
|
||||
nd_noise_d6 <= nd_noise_d5;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire m_axis_dout_tvalid;
|
||||
wire [47:0] m_axis_dout_tdata;
|
||||
ComMul_EstNoise ComMul_EstNoise (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_a_tvalid (1'd1), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata ({6'd0,noiseq,6'd0,noisei}), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (1'd1), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata ({6'd0,noiseqh,6'd0,noisei}), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid (m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
wire [19:0] ComMul_Noisei;
|
||||
wire [19:0] ComMul_Noiseq;
|
||||
|
||||
assign ComMul_Noiseq = m_axis_dout_tdata[43:24];
|
||||
assign ComMul_Noisei = m_axis_dout_tdata[19:0];
|
||||
|
||||
|
||||
//--------------------------------------------累加求和，状态机控制----------------------------------------//
|
||||
reg state_noise = 1'd0;
|
||||
reg [27:0] add_Noisei = 28'd0;
|
||||
reg [27:0] add_Noiseq = 28'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
add_Noisei <= 28'd0;
|
||||
add_Noiseq <= 28'd0;
|
||||
nd_EstNoise <= 1'd0;
|
||||
EstNoise_i <= 28'd0;
|
||||
EstNoise_q <= 28'd0;
|
||||
state_noise <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_noise)
|
||||
//帧间复位结束后，等待nd_noise_d6拉高，拉高持续256clk，期间数据全部累加
|
||||
//nd_noise_d6拉低说明256clk的累加结束，给一次噪声估计结果，伴随nd
|
||||
1'd0:begin
|
||||
if(nd_noise_d6) begin
|
||||
add_Noisei <= {{8{ComMul_Noisei[19]}},ComMul_Noisei};
|
||||
add_Noiseq <= {{8{ComMul_Noiseq[19]}},ComMul_Noiseq};
|
||||
nd_EstNoise <= 1'd0;
|
||||
EstNoise_i <= EstNoise_i;
|
||||
EstNoise_q <= EstNoise_q;
|
||||
state_noise <= state_noise + 1'd1;
|
||||
end
|
||||
else begin
|
||||
add_Noisei <= 28'd0;
|
||||
add_Noiseq <= 28'd0;
|
||||
nd_EstNoise <= 1'd0;
|
||||
EstNoise_i <= EstNoise_i;
|
||||
EstNoise_q <= EstNoise_q;
|
||||
state_noise <= state_noise;
|
||||
end
|
||||
end
|
||||
1'd1:begin
|
||||
if(nd_noise_d6==1'd0) begin
|
||||
add_Noisei <= add_Noisei;
|
||||
add_Noiseq <= add_Noiseq;
|
||||
nd_EstNoise <= 1'd1;
|
||||
EstNoise_i <= add_Noisei;
|
||||
EstNoise_q <= add_Noiseq;
|
||||
state_noise <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
add_Noisei <= add_Noisei + {{8{ComMul_Noisei[19]}},ComMul_Noisei};
|
||||
add_Noiseq <= add_Noiseq + {{8{ComMul_Noiseq[19]}},ComMul_Noiseq};
|
||||
nd_EstNoise <= 1'd0;
|
||||
EstNoise_i <= EstNoise_i;
|
||||
EstNoise_q <= EstNoise_q;
|
||||
state_noise <= state_noise;
|
||||
end
|
||||
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------除data_length=256，再乘2-----------------------------------//
|
||||
//----------------------------------------除49，再除2-----------------------------------//
|
||||
//根据量化方案，此处不再做除法，相当于噪声估计结果放大了256*49倍
|
||||
//FullSystem_v5.m
|
||||
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("ComMul_Noisei.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("ComMul_Noiseq.txt","w"); $fclose(handle02);
|
||||
|
||||
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
// if(nd_noise_d6)begin
|
||||
// handle01=$fopen("ComMul_Noisei.txt","a+");$fwrite(handle01,"%d\n",$signed(ComMul_Noisei));$fclose(handle01);
|
||||
// handle02=$fopen("ComMul_Noiseq.txt","a+");$fwrite(handle02,"%d\n",$signed(ComMul_Noiseq));$fclose(handle02);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,60 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 21:27:25 01/18/2018
|
||||
// Design Name:
|
||||
// Module Name: Normalization_Factor_0_8125
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Normalization_Factor_0_8125 #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] din_NF, //输入为非负数
|
||||
output reg [WIDTH-1:0] dout_NF = 8'd0 //输出相对输入延时3个时钟周期
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] din_NF_reg0 = 8'd0, din_NF_reg1 = 8'd0;
|
||||
reg [WIDTH-1:0] sum_1 = 8'd0, sum_2 = 8'd0;
|
||||
always @(posedge clk) begin
|
||||
din_NF_reg0 <= din_NF;
|
||||
din_NF_reg1 <= din_NF_reg0;
|
||||
end
|
||||
always @(posedge clk) begin //对输入数据乘以系数0.8125
|
||||
sum_1 <= (din_NF >> 1) + (din_NF >> 2);
|
||||
sum_2 <= sum_1 + (din_NF_reg0 >> 4);
|
||||
case ({
|
||||
din_NF_reg1[3:0]
|
||||
}) //matlab中用round函数，verilog中默认是floor函数
|
||||
4'b0000: dout_NF <= sum_2 + 8'd0;
|
||||
4'b0001: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0010: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0011: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0100: dout_NF <= sum_2 + 8'd0;
|
||||
4'b0101: dout_NF <= sum_2 + 8'd1;
|
||||
4'b0110: dout_NF <= sum_2 + 8'd1; //32个数，0~15和16~31的数是一样的，所以用din_NF_reg1&4'b1111，
|
||||
4'b0111: dout_NF <= sum_2 + 8'd2; //例如，din_NF_reg1=6'd19,经过din_NF_reg1&4'b1111之后，变成了6'd3
|
||||
4'b1000: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1001: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1010: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1011: dout_NF <= sum_2 + 8'd2;
|
||||
4'b1100: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1101: dout_NF <= sum_2 + 8'd2;
|
||||
4'b1110: dout_NF <= sum_2 + 8'd1;
|
||||
4'b1111: dout_NF <= sum_2 + 8'd2;
|
||||
default: dout_NF <= 8'd0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
+144
@@ -0,0 +1,144 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: OUT_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module OUT_PRO
|
||||
#(
|
||||
parameter OUT_ONLY_INFORMATION = 1'd0 //译码输出格式选择标志，1:只输出信息位；0：输出整个码字
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_OUT,
|
||||
input start_OUT,
|
||||
|
||||
input [0:0] DR_dout_01,
|
||||
input [0:0] DR_dout_02,
|
||||
input [0:0] DR_dout_03,
|
||||
input [0:0] DR_dout_04,
|
||||
|
||||
output reg [8:0] DR_addr_rd_01=9'd511,
|
||||
output reg [8:0] DR_addr_rd_02=9'd511,
|
||||
output reg [8:0] DR_addr_rd_03=9'd511,
|
||||
output reg [8:0] DR_addr_rd_04=9'd511,
|
||||
|
||||
output ldpc_syncout_OUT,
|
||||
output rdy_OUT,
|
||||
output reg [0:0] ldpc_dout_OUT=1'd0
|
||||
);
|
||||
|
||||
reg [11:0] cnt_OUT=12'd0;
|
||||
reg flag_OUT=1'd0;
|
||||
always @ (posedge clk) begin//产生该模块的计数基准
|
||||
if(rst_OUT) begin
|
||||
cnt_OUT <= 12'd0;
|
||||
flag_OUT <= 1'b0;
|
||||
end else begin
|
||||
if(start_OUT) begin
|
||||
flag_OUT <= 1'b1;
|
||||
cnt_OUT <= 12'd0;
|
||||
end else begin
|
||||
if(flag_OUT) begin
|
||||
if(cnt_OUT<12'd2080)begin
|
||||
flag_OUT <= flag_OUT;
|
||||
cnt_OUT <= cnt_OUT + 12'd1;
|
||||
end else begin
|
||||
cnt_OUT <= cnt_OUT;
|
||||
flag_OUT <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_OUT <= cnt_OUT;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
// 控制DR的读地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUT) begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
DR_addr_rd_03 <= 9'd511;
|
||||
DR_addr_rd_04 <= 9'd511;
|
||||
end else begin
|
||||
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
|
||||
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
|
||||
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
|
||||
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
|
||||
else begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
end
|
||||
end else begin // 输出整个码字
|
||||
if (cnt_OUT >= 12'd1 && cnt_OUT <= 12'd512)
|
||||
DR_addr_rd_01 <= DR_addr_rd_01 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd513 && cnt_OUT <= 12'd1024)
|
||||
DR_addr_rd_02 <= DR_addr_rd_02 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd1025 && cnt_OUT <= 12'd1536)
|
||||
DR_addr_rd_03 <= DR_addr_rd_03 + 9'd1;
|
||||
else if (cnt_OUT >= 12'd1537 && cnt_OUT <= 12'd2048)
|
||||
DR_addr_rd_04 <= DR_addr_rd_04 + 9'd1;
|
||||
else begin
|
||||
DR_addr_rd_01 <= 9'd511;
|
||||
DR_addr_rd_02 <= 9'd511;
|
||||
DR_addr_rd_03 <= 9'd511;
|
||||
DR_addr_rd_04 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
parameter DELAY_OUT = 4'd6;
|
||||
// 控制DR的输出数据到译码器的输出
|
||||
always @ (posedge clk) begin
|
||||
if (rst_OUT) begin
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end else begin
|
||||
if (OUT_ONLY_INFORMATION) begin // 只输出信息位
|
||||
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_01;
|
||||
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_02;
|
||||
else
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end else begin // 输出整个码字
|
||||
if (cnt_OUT >= 12'd1 + DELAY_OUT && cnt_OUT <= 12'd512 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_01;
|
||||
else if (cnt_OUT >= 12'd513 + DELAY_OUT && cnt_OUT <= 12'd1024 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_02;
|
||||
else if (cnt_OUT >= 12'd1025 + DELAY_OUT && cnt_OUT <= 12'd1536 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_03;
|
||||
else if (cnt_OUT >= 12'd1537 + DELAY_OUT && cnt_OUT <= 12'd2048 + DELAY_OUT)
|
||||
ldpc_dout_OUT <= DR_dout_04;
|
||||
else
|
||||
ldpc_dout_OUT <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 产生状态指示标志
|
||||
assign ldpc_syncout_OUT = (cnt_OUT == 12'd1 + DELAY_OUT) ? 1'd1 : 1'd0;
|
||||
|
||||
assign rdy_OUT = (OUT_ONLY_INFORMATION == 1'd0) ?
|
||||
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd2048 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0) :
|
||||
((cnt_OUT >= 12'd1 + DELAY_OUT + 12'd1 && cnt_OUT <= 12'd1024 + DELAY_OUT + 12'd1) ? 1'd1 : 1'd0);
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+99
-72
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
// +------------------------------+
|
||||
// | |
|
||||
@@ -36,19 +36,32 @@ module PAPR #(
|
||||
);
|
||||
|
||||
localparam SUM_WIDTH = 32;
|
||||
localparam CNT_START = 16; // 32*4 / 8 * mag_valid signal is active high per 8 clk
|
||||
localparam CNT_END = 44; // 88*4 / 8
|
||||
localparam PULSE_PERIOD = 50;
|
||||
|
||||
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d1;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d2;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d3;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_reserved;
|
||||
|
||||
// accumulate ==> average ==> papr
|
||||
wire [MAG_WIDTH-1:0] vec_mag_1024;
|
||||
reg [ 7:0] cnt;
|
||||
|
||||
|
||||
wire [MAG_WIDTH-1:0] data_avg;
|
||||
reg [SUM_WIDTH-1:0] data_sum;
|
||||
assign data_avg = data_sum[SUM_WIDTH-1:10];
|
||||
|
||||
|
||||
reg mag_valid_d1;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d1;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d2;
|
||||
reg [MAG_WIDTH-1:0] vec_mag_d3;
|
||||
reg frame_sync_d1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
mag_valid_d1 <= mag_valid;
|
||||
if (rst) begin
|
||||
vec_mag_d1 <= 'd0;
|
||||
vec_mag_d2 <= 'd0;
|
||||
vec_mag_d3 <= 'd0;
|
||||
vec_mag_d1 <= 0;
|
||||
vec_mag_d2 <= 0;
|
||||
vec_mag_d3 <= 0;
|
||||
end
|
||||
else if (mag_valid) begin
|
||||
vec_mag_d1 <= vec_mag;
|
||||
@@ -61,14 +74,7 @@ module PAPR #(
|
||||
vec_mag_d3 <= vec_mag_d3;
|
||||
end
|
||||
end
|
||||
// accumulate ==> average ==> papr
|
||||
wire [MAG_WIDTH-1:0] vec_mag_1024;
|
||||
reg [ 5:0] cnt;
|
||||
// shift_1024 shift_1024 (
|
||||
// .D (vec_mag), // input wire [21 : 0] D
|
||||
// .CLK(clk), // input wire CLK
|
||||
// .Q (vec_mag_1024) // output wire [21 : 0] Q
|
||||
// );
|
||||
|
||||
|
||||
shift_reg #(
|
||||
.DATA_WIDTH(MAG_WIDTH),
|
||||
@@ -82,10 +88,9 @@ module PAPR #(
|
||||
);
|
||||
|
||||
|
||||
reg [SUM_WIDTH-1:0] data_sum;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
data_sum <= 'd0;
|
||||
data_sum <= 0;
|
||||
end
|
||||
else begin
|
||||
if (mag_valid) begin
|
||||
@@ -97,70 +102,92 @@ module PAPR #(
|
||||
end
|
||||
end
|
||||
|
||||
wire [MAG_WIDTH-1:0] data_avg;
|
||||
assign data_avg = data_sum[SUM_WIDTH-1:10];
|
||||
|
||||
|
||||
|
||||
// FSM
|
||||
reg [2:0] cs = 0;
|
||||
reg [2:0] ns = 0;
|
||||
always @(posedge clk) begin
|
||||
cs <= ns;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
ns = cs;
|
||||
case (cs)
|
||||
0: begin
|
||||
if (mag_valid && vec_mag_1024 != 'd0 && data_avg != 'd0 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
|
||||
ns = 1;
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
if (cnt == CNT_START - 1) begin
|
||||
ns = 2;
|
||||
end
|
||||
end
|
||||
2: begin
|
||||
if (vec_mag_reserved < {vec_mag[MAG_WIDTH-3:0], 2'b0}) begin
|
||||
ns = 0;
|
||||
end
|
||||
else if (cnt == CNT_END - 1) begin
|
||||
ns = 3;
|
||||
end
|
||||
end
|
||||
3: begin
|
||||
// generate pulse
|
||||
ns = 4;
|
||||
end
|
||||
4: begin
|
||||
if (cnt == PULSE_PERIOD - 1) begin
|
||||
ns = 0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
frame_sync <= 1'd0;
|
||||
if (cs == 0 && ns == 1) begin
|
||||
vec_mag_reserved <= vec_mag_d2;
|
||||
end
|
||||
else if (vec_mag_1024 != 'd0 && data_avg != 'd0) begin
|
||||
// NOTE: 防止0均值的情况，比如，一开始信号很小，刚好接收到有信号，那么均值为0，峰值有值，那么一定会过门限。
|
||||
if (mag_valid_d1 && ({3'd0, vec_mag_d2[MAG_WIDTH-1:3]} >= data_avg) && (vec_mag_d2 >= vec_mag_d1) && (vec_mag_d2 >= vec_mag_d3) && (vec_mag_d2 >= 22'h5000)) begin
|
||||
frame_sync <= 1'd1;
|
||||
end
|
||||
else if (cnt == 6'b111111) begin
|
||||
frame_sync <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
frame_sync <= frame_sync;
|
||||
else if (cs == 0) begin
|
||||
vec_mag_reserved <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == 1 || cs == 2) begin
|
||||
if (mag_valid) begin
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
end
|
||||
else if (cs == 4) begin
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
else if (cs == 0) begin
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
frame_sync_pulse <= (cs == 3);
|
||||
|
||||
if (cs == 4) begin
|
||||
frame_sync <= 1;
|
||||
end
|
||||
else begin
|
||||
frame_sync <= frame_sync;
|
||||
frame_sync <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
frame_sync_d1 <= frame_sync;
|
||||
if (frame_sync && ~frame_sync_d1) begin
|
||||
frame_sync_pulse <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
frame_sync_pulse <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 6'd0;
|
||||
end
|
||||
else if (frame_sync && mag_valid_d1) begin
|
||||
cnt <= cnt + 6'd1;
|
||||
end
|
||||
else if (cnt == 6'b111111) begin
|
||||
cnt <= 6'd0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
// NOTE: comment
|
||||
|
||||
ila_frame_sync u_ila_frame_sync (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(vec_mag), // input wire [21:0] probe0
|
||||
.probe1(mag_valid), // input wire [0:0] probe1
|
||||
.probe2(frame_sync) // input wire [0:0] probe2
|
||||
.probe1(data_avg), // input wire [21:0] probe0
|
||||
.probe2(cs), // input wire [2:0] probe2
|
||||
.probe3(cnt), // input wire [7:0] probe2
|
||||
.probe4(frame_sync) // input wire [0:0] probe2
|
||||
);
|
||||
|
||||
|
||||
|
||||
@@ -74,6 +74,7 @@ module Receiver (
|
||||
dmf_s_valid <= 1'd0;
|
||||
end
|
||||
else if (startup_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
|
||||
// fifo_out_valid may be not trustable at the rst state
|
||||
dmf_s_valid <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
|
||||
+677
@@ -0,0 +1,677 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:42 11/14/2019
|
||||
// Design Name:
|
||||
// Module Name: RecvTop
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RecvTop (
|
||||
input clk,
|
||||
input clk_2x, // clk_2x
|
||||
input clk_4x,
|
||||
input clk_half, // clk_1/2
|
||||
input clk_quarter, // clk_1/4
|
||||
input rst,
|
||||
input rst2, // TODO： delete the signal
|
||||
// phy wave
|
||||
input [11:0] dini,
|
||||
input [11:0] dinq,
|
||||
// mgc control
|
||||
output [ 3:0] ad9361_ctrl_in,
|
||||
output wire flag_mgc_done_pulse, // active high pulse signal
|
||||
output wire frame_sync_pulse_1x, // in domain clk
|
||||
//vio
|
||||
input vio_tsync_inter16, //为1的时候启用内插，从16倍过采样中挑一路
|
||||
input EQUenable_vio, //为1时启用均衡
|
||||
input [ 7:0] Zerozone_vio, //零域估计，默认值为8'd29
|
||||
input [ 6:0] vio_stopbit, //寻找停止位，默认值为7'd60
|
||||
// stop signal
|
||||
output flag_stop, //给shx，拉高8个clk表示当前时帧有效数据接收完毕
|
||||
output [16:0] addr_stop, //给shx，拉高8个clk,与flag_stop对齐，指示位置与最后1bit有效数据的位置对齐
|
||||
// mac frame header
|
||||
output [63:0] recvNetData,
|
||||
output recvNetDataNd,
|
||||
// rx data src
|
||||
output wire [31:0] rx_data_src_fifo_tdata,
|
||||
output wire rx_data_src_fifo_tlast,
|
||||
input wire rx_data_src_fifo_tready,
|
||||
output wire rx_data_src_fifo_tvalid,
|
||||
// ber
|
||||
output reg err_flag_pos
|
||||
);
|
||||
|
||||
wire rst_TimeSync;
|
||||
wire rst_freq;
|
||||
wire DAGC_rdy;
|
||||
wire framesync; //帧同步峰
|
||||
wire flag_cfo_done; //帧同步峰，与频率补偿输出对应
|
||||
wire framesync_tsync; //帧同步标志，与TSync输出对应
|
||||
wire IntpARdy; //TSync输出nd
|
||||
wire nd_SC_FDE_dout; //SC_FDE输出nd
|
||||
wire framerdy; //一帧译码结果存储完毕标志
|
||||
reg flag_bercount = 1'd0;
|
||||
reg flag_badframe = 1'd0;
|
||||
reg flag_ber = 1'd0;
|
||||
wire [11:0] dc_removal_dout_i; //MGC_adaptation、去直流输出
|
||||
wire [11:0] dc_removal_dout_q;
|
||||
wire [ 9:0] matchfilterout_i; //MF输出
|
||||
wire [ 9:0] matchfilterout_q;
|
||||
wire [ 9:0] DAGC_out_i; //DAGC输出
|
||||
wire [ 9:0] DAGC_out_q;
|
||||
wire [ 9:0] freqdataout_i; //频率补偿输出
|
||||
wire [ 9:0] freqdataout_q;
|
||||
wire [ 9:0] IntpOuti; //TSync输出
|
||||
wire [ 9:0] IntpOutq;
|
||||
wire [ 9:0] SC_FDE_douti; //SC_FDE输出
|
||||
wire [ 9:0] SC_FDE_doutq;
|
||||
wire [24:0] mean_temp;
|
||||
wire [12:0] acc_mean;
|
||||
wire [ 4:0] state_mgc;
|
||||
wire mgc1_rdy;
|
||||
wire flag_state_mgc;
|
||||
wire [ 2:0] state_rst;
|
||||
wire flag_overflow;
|
||||
wire flag_small;
|
||||
wire [11:0] dc_value_i;
|
||||
wire [11:0] dc_value_q;
|
||||
wire flag_dc;
|
||||
wire flag_agch;
|
||||
wire flag_agcl;
|
||||
wire flag_agc_power;
|
||||
wire [12:0] agc_ref;
|
||||
wire [12:0] agc_check;
|
||||
wire flag_powerabsh;
|
||||
wire flag_powerabsl;
|
||||
wire flag_abs_power;
|
||||
wire [10:0] abs_ref;
|
||||
wire [10:0] abs_check;
|
||||
wire [ 3:0] flag_clk_4bit; //位同步选取通道结果
|
||||
wire flagoverflow_fftpilot_26to14; //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||||
wire flagoverflow_ChnZF_26to18; //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||||
wire flagoverflow_comdiv_34to20i; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
wire flagoverflow_comdiv_34to20q; //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
wire flagoverflow_ifftzero_29to17i; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
wire flagoverflow_ifftzero_29to17q; //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
wire flagoverflow_MMSEdiv_divisor_31to28; //第2个除法器，即MMSE除法的分母截位，31截到28
|
||||
wire flagoverflow_divmmse_34to11; //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
wire flagoverflow_ifftindata_28to20i; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
wire flagoverflow_ifftindata_28to20q; //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
wire flagoverflow_fftdata_26to16i; //数据段ow的fft输出截位，26截到16
|
||||
wire flagoverflow_fftdata_26to16q; //数据段ow的fft输出截位，26截到16
|
||||
wire flagoverflow_FDE_dataout_29to10i; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
wire flagoverflow_FDE_dataout_29to10q; //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
reg flagoverflow = 1'd0; //总溢出标志
|
||||
wire Pilot_rdy_hide1_d1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg [ 7:0] cnt_mgc_delay;
|
||||
wire mgc_start;
|
||||
wire mgc_start_quarter;
|
||||
wire flag_mgc_done; // level flag, under clk_1x
|
||||
wire flag_mgc_done_4x; // level flag
|
||||
|
||||
// startup delay
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_mgc_delay <= 0;
|
||||
end
|
||||
else if (cnt_mgc_delay < 8'hff) begin
|
||||
cnt_mgc_delay <= cnt_mgc_delay + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_mgc_delay <= cnt_mgc_delay;
|
||||
end
|
||||
end
|
||||
|
||||
assign mgc_start = (cnt_mgc_delay == 8'hFE);
|
||||
assign mgc_start_quarter = (cnt_mgc_delay >= 8'hF0) && (cnt_mgc_delay <= 8'hFE);
|
||||
|
||||
// * MGC module
|
||||
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (mgc_start),
|
||||
.rx_data_i (dini),
|
||||
.rx_data_q (dinq),
|
||||
.ad9361_ctrl_in (ad9361_ctrl_in),
|
||||
.flag_mgc_done_pulse(flag_mgc_done_pulse),
|
||||
.flag_mgc_done (flag_mgc_done)
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg MF_rdy; // flag_mgc_done_d1
|
||||
wire MF_rst; // flag_mgc_done_pulse_d2
|
||||
always @(posedge clk_quarter) begin
|
||||
if (rst) begin
|
||||
MF_rdy <= 0;
|
||||
end
|
||||
else begin
|
||||
MF_rdy <= flag_mgc_done;
|
||||
end
|
||||
end
|
||||
|
||||
wire fifo_out_valid;
|
||||
reg [ 2:0] cnt_fifo_out_valid;
|
||||
reg [ 2:0] cnt_fifo_out_valid_sel = 7; // 根据speed mode对应的计数器边界值 // refer to Receiver.v
|
||||
|
||||
wire [31:0] fifo_out;
|
||||
reg dmf_s_valid;
|
||||
wire dmf_tvalid_interp16_i;
|
||||
wire dmf_tvalid_interp16_q;
|
||||
wire [31:0] mf_data_interp16_i;
|
||||
wire [31:0] mf_data_interp16_q;
|
||||
wire [23:0] dmf_tdata_interp16_i;
|
||||
wire [23:0] dmf_tdata_interp16_q;
|
||||
|
||||
// in domain clk_quarter
|
||||
wire [ 9:0] mf_data_downsample_i;
|
||||
wire [ 9:0] mf_data_downsample_q;
|
||||
|
||||
|
||||
// valid signal for dmf
|
||||
always @(posedge clk_4x) begin
|
||||
if (rst) begin
|
||||
dmf_s_valid <= 1'd0;
|
||||
end
|
||||
else if (flag_mgc_done_4x && fifo_out_valid && cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin
|
||||
// fifo_out_valid may be not trustable at the rst state
|
||||
dmf_s_valid <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
dmf_s_valid <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_4x) begin
|
||||
if (rst) begin
|
||||
cnt_fifo_out_valid <= 3'd0;
|
||||
end
|
||||
else if (fifo_out_valid) begin
|
||||
if (cnt_fifo_out_valid == cnt_fifo_out_valid_sel) begin // refer to Receiver.v
|
||||
cnt_fifo_out_valid <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_fifo_out_valid <= cnt_fifo_out_valid + 3'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_fifo_out_valid <= cnt_fifo_out_valid;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire mf_fir_s_tready_i;
|
||||
wire mf_fir_s_tready_q;
|
||||
|
||||
// Match filter
|
||||
// fir_match_interp4 u_fir_match_filter_interp4_i (
|
||||
// .aclk (clk), // input wire aclk
|
||||
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (mf_data_interp4_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
// fir_match_interp4 u_fir_match_filter_interp4_q (
|
||||
// .aclk (clk), // input wire aclk
|
||||
// .s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
// .s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
|
||||
// .s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
|
||||
// .m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
// .m_axis_data_tdata (mf_data_interp4_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
// );
|
||||
|
||||
fir_match_interp16 u_fir_match_filter_interp16_i (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(mf_fir_s_tready_i), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dini}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp16_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
fir_match_interp16 u_fir_match_filter_interp16_q (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_data_tvalid(flag_mgc_done), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(mf_fir_s_tready_q), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, dinq}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (mf_data_interp16_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
// CDC into clk_4x
|
||||
fifo_shift u_fifo_shift (
|
||||
// input
|
||||
.s_aclk (clk), // input wire s_aclk
|
||||
.s_aresetn (flag_mgc_done), // input wire s_aresetn
|
||||
.s_axis_tvalid(flag_mgc_done), // input wire s_axis_tvalid
|
||||
.s_axis_tready(), // output wire s_axis_tready
|
||||
.s_axis_tdata ({8'd0, mf_data_interp16_q[31-:12], mf_data_interp16_i[31-:12]}), // input wire [31 : 0] s_axis_tdata
|
||||
// output
|
||||
.m_aclk (clk_4x), // input wire m_aclk
|
||||
.m_axis_tvalid(fifo_out_valid), // output wire m_axis_tvalid
|
||||
.m_axis_tready(1'b1), // input wire m_axis_tready
|
||||
.m_axis_tdata (fifo_out), // output wire [31 : 0] m_axis_tdata
|
||||
.wr_rst_busy (),
|
||||
.rd_rst_busy ()
|
||||
);
|
||||
|
||||
// fir_dmf_interp4 u_fir_dmf_interp4_i (
|
||||
// .aclk (clk_4x),
|
||||
// .s_axis_data_tvalid(dmf_s_valid),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata ({4'd0, fifo_out[11:0]}),
|
||||
// .m_axis_data_tvalid(dmf_tvalid_interp4_i),
|
||||
// .m_axis_data_tdata (dmf_tdata_interp4_i)
|
||||
// );
|
||||
|
||||
// fir_dmf_interp4 u_fir_dmf_interp4_q (
|
||||
// .aclk (clk_4x),
|
||||
// .s_axis_data_tvalid(dmf_s_valid),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata ({4'd0, fifo_out[23:12]}),
|
||||
// .m_axis_data_tvalid(dmf_tvalid_interp4_q),
|
||||
// .m_axis_data_tdata (dmf_tdata_interp4_q)
|
||||
// );
|
||||
|
||||
// dmf filter
|
||||
fir_dmf_interp16 u_fir_dmf_interp16_i (
|
||||
.aclk (clk_4x), // input wire aclk
|
||||
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, fifo_out[11:0]}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(dmf_tvalid_interp16_i), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (dmf_tdata_interp16_i) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
fir_dmf_interp16 u_fir_dmf_interp16_q (
|
||||
.aclk (clk_4x), // input wire aclk
|
||||
.s_axis_data_tvalid(dmf_s_valid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata ({4'd0, fifo_out[23:12]}), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(dmf_tvalid_interp16_q), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (dmf_tdata_interp16_q) // output wire [31 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
|
||||
wire [7:0] cnt_chu_seq_sync_max_vio;
|
||||
localparam CNT_CHU_SEQ_SYNC_MAX = 40; //! should not less than 3 due to the minimum rst of aresetn
|
||||
|
||||
wire [21:0] mag;
|
||||
wire mag_valid;
|
||||
wire frame_sync_4x;
|
||||
wire frame_sync_pulse; // in baseband process clock domain, quater clock
|
||||
reg flag_frame_sync; // active high level
|
||||
wire rst_frame_sync; // derive from frame sync pulse
|
||||
reg [ 7:0] cnt_chu_seq_sync; // frame sync delay to chu seq sample start pos
|
||||
|
||||
|
||||
|
||||
//* calc the magnitude
|
||||
MagnitudeEstimator #(
|
||||
.VEC_WIDTH(21)
|
||||
) u_MagnitudeEstimator (
|
||||
.clk (clk_4x),
|
||||
.rst (rst),
|
||||
.vec_valid(dmf_tvalid_interp16_i),
|
||||
.I (dmf_tdata_interp16_i[20:0]),
|
||||
.Q (dmf_tdata_interp16_q[20:0]),
|
||||
.mag (mag),
|
||||
.mag_valid(mag_valid)
|
||||
);
|
||||
//* frame sync threashold judgement
|
||||
PAPR #(
|
||||
.MAG_WIDTH (22),
|
||||
.WINDOW_DEPTH(1023)
|
||||
) u_PAPR (
|
||||
.clk (clk_4x),
|
||||
.rst (rst),
|
||||
.vec_mag (mag),
|
||||
.mag_valid (mag_valid),
|
||||
.frame_sync (frame_sync_4x),
|
||||
.frame_sync_pulse() // under clk_4x
|
||||
);
|
||||
|
||||
|
||||
// ! ATTENTION
|
||||
// frame_sync_pulse is under clk_quarter
|
||||
always @(posedge clk_quarter) begin
|
||||
if (frame_sync_pulse && ~flag_frame_sync) begin
|
||||
cnt_chu_seq_sync <= 1;
|
||||
end
|
||||
// avoid the tailing of the convolution (here we use CNT_CHU_SEQ_SYNC_MAX clocks)
|
||||
else if (cnt_chu_seq_sync >= 1 && cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio) begin
|
||||
cnt_chu_seq_sync <= cnt_chu_seq_sync + 1;
|
||||
end
|
||||
else begin
|
||||
cnt_chu_seq_sync <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign rst_frame_sync = ((cnt_chu_seq_sync >= 1) && (cnt_chu_seq_sync < cnt_chu_seq_sync_max_vio));
|
||||
|
||||
always @(posedge clk_quarter) begin
|
||||
if (rst) begin
|
||||
flag_frame_sync <= 0;
|
||||
end
|
||||
else if (cnt_chu_seq_sync == cnt_chu_seq_sync_max_vio) begin
|
||||
flag_frame_sync <= 1;
|
||||
end
|
||||
else begin
|
||||
flag_frame_sync <= flag_frame_sync;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
wire [9:0] FrameSync_douti;
|
||||
wire [9:0] FrameSync_doutq;
|
||||
wire dagc_rdy;
|
||||
wire mgc_rdy;
|
||||
wire rst_dagc;
|
||||
|
||||
wire [9:0] dagc_data_in_i;
|
||||
wire [9:0] dagc_data_in_q;
|
||||
|
||||
reg [1:0] cnt_downsample = 0;
|
||||
wire pulse_downsample_enable;
|
||||
|
||||
assign pulse_downsample_enable = (cnt_downsample == 3);
|
||||
always @(posedge clk) begin
|
||||
cnt_downsample <= cnt_downsample + 1;
|
||||
end
|
||||
|
||||
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_i (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk_quarter), // input wire rd_clk
|
||||
.din (mf_data_interp16_i[31-:10]), // input wire [9 : 0] din
|
||||
.wr_en (pulse_downsample_enable), // input wire wr_en
|
||||
.rd_en (1), // input wire rd_en
|
||||
.dout (mf_data_downsample_i), // output wire [9 : 0] dout
|
||||
.full (), // output wire full
|
||||
.empty () // output wire empty
|
||||
);
|
||||
|
||||
fifo_cdc_downsample_1_4 u_fifo_cdc_downsample_1_4_q (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk_quarter), // input wire rd_clk
|
||||
.din (mf_data_interp16_q[31-:10]), // input wire [9 : 0] din
|
||||
.wr_en (pulse_downsample_enable), // input wire wr_en
|
||||
.rd_en (1), // input wire rd_en
|
||||
.dout (mf_data_downsample_q), // output wire [9 : 0] dout
|
||||
.full (), // output wire full
|
||||
.empty () // output wire empty
|
||||
);
|
||||
|
||||
//* CLOCK_QUARTER DOMAIN
|
||||
|
||||
shift_register_64 u_shift_register_64_i (
|
||||
.D (mf_data_downsample_i), // input wire [9 : 0] D
|
||||
.CLK(clk_quarter), // input wire CLK
|
||||
.Q (dagc_data_in_i) // output wire [9 : 0] Q
|
||||
);
|
||||
shift_register_64 u_shift_register_64_q (
|
||||
.D (mf_data_downsample_q), // input wire [9 : 0] D
|
||||
.CLK(clk_quarter), // input wire CLK
|
||||
.Q (dagc_data_in_q) // output wire [9 : 0] Q
|
||||
);
|
||||
|
||||
DAGC_v2 DAGC_v2 (
|
||||
.clk (clk_quarter),
|
||||
.rst (~flag_mgc_done),
|
||||
.mgc1_rdy (MF_rdy),
|
||||
.framesync_d0 (flag_frame_sync),
|
||||
.vio_powertest_h (2'b00),
|
||||
.vio_powertest_l (2'b00),
|
||||
.matchfilterout_i(dagc_data_in_i), // input,
|
||||
.matchfilterout_q(dagc_data_in_q), // input
|
||||
.DAGC_out_i (DAGC_out_i), // output
|
||||
.DAGC_out_q (DAGC_out_q), // output
|
||||
// debug
|
||||
.flag_agch (flag_agch),
|
||||
.flag_agcl (flag_agcl),
|
||||
.flag_agc_power (flag_agc_power),
|
||||
.agc_ref (agc_ref),
|
||||
.agc_check (agc_check),
|
||||
.dagc_rdy (dagc_rdy),
|
||||
.mgc_rdy (mgc_rdy),
|
||||
.rst_dagc (rst_dagc)
|
||||
);
|
||||
|
||||
|
||||
// CFO estimation
|
||||
freqestm freqestm (
|
||||
.clk (clk_quarter),
|
||||
.rst (mgc_start_quarter),
|
||||
.mgc_rdy (mgc_rdy),
|
||||
.framesync (dagc_rdy),
|
||||
.datain_i (DAGC_out_i),
|
||||
.datain_q (DAGC_out_q),
|
||||
.dataout_i (freqdataout_i),
|
||||
.dataout_q (freqdataout_q),
|
||||
.framesync_delay(flag_cfo_done),
|
||||
.data_save (data_save),
|
||||
.rst_freq (rst_freq)
|
||||
);
|
||||
|
||||
//位同步
|
||||
wire [1:0] cnt_tsync;
|
||||
TimeSync_top TimeSync_top (
|
||||
.clk (clk_quarter),
|
||||
.rst (rst_frame_sync),
|
||||
.dini (freqdataout_i),
|
||||
.dinq (freqdataout_q),
|
||||
.rdy (IntpARdy),
|
||||
.douti (IntpOuti),
|
||||
.doutq (IntpOutq),
|
||||
.vio_tsync_inter16(vio_tsync_inter16),
|
||||
.framesync (flag_cfo_done), //帧同步标志
|
||||
.framesync_tsync (framesync_tsync), //帧同步标志
|
||||
//debug
|
||||
.cnt_tsync (cnt_tsync),
|
||||
.flag_clk_4bit (flag_clk_4bit)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// SC-FDE
|
||||
SC_FDE_TOP SC_FDE_TOP_djy (
|
||||
.clk (clk_quarter),
|
||||
.rst (rst_frame_sync),
|
||||
// param
|
||||
.EQUenable_vio (EQUenable_vio), //为1时启用均衡
|
||||
.Zerozone_vio (Zerozone_vio), //零域估计，默认值为8'd29
|
||||
.flag_ow_left (framesync_tsync), //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
|
||||
.nd (IntpARdy),
|
||||
.dini (IntpOuti),
|
||||
.dinq (IntpOutq),
|
||||
.nd_SC_FDE_dout (nd_SC_FDE_dout),
|
||||
.SC_FDE_douti (SC_FDE_douti),
|
||||
.SC_FDE_doutq (SC_FDE_doutq),
|
||||
// debug,溢出标志
|
||||
.flagoverflow_fftpilot_26to14 (),
|
||||
.flagoverflow_ChnZF_26to18 (),
|
||||
.flagoverflow_comdiv_34to20i (),
|
||||
.flagoverflow_comdiv_34to20q (),
|
||||
.flagoverflow_ifftzero_29to17i (),
|
||||
.flagoverflow_ifftzero_29to17q (),
|
||||
.flagoverflow_MMSEdiv_divisor_31to28(),
|
||||
.flagoverflow_divmmse_34to11 (),
|
||||
.flagoverflow_ifftindata_28to20i (),
|
||||
.flagoverflow_ifftindata_28to20q (),
|
||||
.flagoverflow_fftdata_26to16i (),
|
||||
.flagoverflow_fftdata_26to16q (),
|
||||
.flagoverflow_FDE_dataout_29to10i (),
|
||||
.flagoverflow_FDE_dataout_29to10q ()
|
||||
);
|
||||
|
||||
|
||||
wire phase_adjust_rdy;
|
||||
wire [9:0] phase_adjust_douti;
|
||||
wire [9:0] phase_adjust_doutq;
|
||||
phase_adjust phase_adjust (
|
||||
.clk (clk_quarter),
|
||||
.rst (rst_frame_sync),
|
||||
.din_i (SC_FDE_douti),
|
||||
.din_q (SC_FDE_doutq),
|
||||
.nd (nd_SC_FDE_dout),
|
||||
.framesync(framesync_tsync),
|
||||
.rdy (phase_adjust_rdy),
|
||||
.dout_i (phase_adjust_douti),
|
||||
.dout_q (phase_adjust_doutq)
|
||||
);
|
||||
|
||||
wire IQmergerdy;
|
||||
wire ldpcsyncin;
|
||||
wire [7:0] IQmergedout;
|
||||
|
||||
IQmerge IQmerge (
|
||||
.clk (clk_quarter),
|
||||
.clk2 (clk_half),
|
||||
.rst (rst2 || rst_frame_sync),
|
||||
.nd (phase_adjust_rdy),
|
||||
.framesync (framesync_tsync),
|
||||
.dini (phase_adjust_douti),
|
||||
.dinq (phase_adjust_doutq),
|
||||
.rdy (IQmergerdy),
|
||||
.ldpcsyncin(ldpcsyncin),
|
||||
.dout (IQmergedout)
|
||||
);
|
||||
|
||||
wire LDPC_SyncOut;
|
||||
wire LDPC_Rdy;
|
||||
wire LDPC_Dout;
|
||||
wire [8:0] good_frames;
|
||||
wire [8:0] bad_frames;
|
||||
wire [8:0] total_frames;
|
||||
|
||||
CCSDS_LDPC_DEC_K1024_R12_TOPP LDPC_decode (
|
||||
.clk (clk_half),
|
||||
.Rst (rst2 || rst_frame_sync),
|
||||
.FrameSync (ldpcsyncin),
|
||||
.Nd (IQmergerdy),
|
||||
.Din (IQmergedout),
|
||||
.LDPC_SyncOut(LDPC_SyncOut),
|
||||
.Rdy (LDPC_Rdy),
|
||||
.LDPC_Dout (LDPC_Dout),
|
||||
.good_frames (good_frames),
|
||||
.bad_frames (bad_frames),
|
||||
.total_frames(total_frames)
|
||||
);
|
||||
|
||||
extract_mac_frame u_extract_mac_frame (
|
||||
.clk (clk_half),
|
||||
.rst (rst2 || rst_frame_sync),
|
||||
.ldpc_dec_out_start (LDPC_SyncOut),
|
||||
.ldpc_dec_out_valid (LDPC_Rdy),
|
||||
.ldpc_dec_out_data (LDPC_Dout),
|
||||
.m_axis_mac_frame_tvalid(rx_data_src_fifo_tvalid),
|
||||
.m_axis_mac_frame_tdata (rx_data_src_fifo_tdata),
|
||||
.m_axis_mac_frame_tready(rx_data_src_fifo_tready),
|
||||
.m_axis_mac_frame_tlast (rx_data_src_fifo_tlast)
|
||||
);
|
||||
|
||||
reg err_flag;
|
||||
reg err_flag_d1;
|
||||
// reg err_flag_pos;
|
||||
always @(posedge clk) begin
|
||||
if (rst2 || rst_frame_sync) begin
|
||||
err_flag <= 0;
|
||||
end
|
||||
else if (total_frames == 105 && bad_frames > 0) begin
|
||||
err_flag <= 1;
|
||||
end
|
||||
|
||||
err_flag_d1 <= err_flag;
|
||||
err_flag_pos <= err_flag & ~err_flag_d1;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// ***** cdc *****
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (2), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) xpm_cdc_startup_inst (
|
||||
.dest_out(flag_mgc_done_4x), // 1-bit output: src_in synchronized to the destination clock domain. This output is
|
||||
// registered.
|
||||
.dest_clk(clk_4x), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (clk), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (flag_mgc_done) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4),
|
||||
.INIT_SYNC_FF (1),
|
||||
.REG_OUTPUT (1),
|
||||
.RST_USED (0),
|
||||
.SIM_ASSERT_CHK(1)
|
||||
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_1x (
|
||||
.dest_pulse(frame_sync_pulse_1x),
|
||||
.dest_clk (clk),
|
||||
.dest_rst (),
|
||||
.src_clk (clk_4x),
|
||||
.src_pulse (frame_sync_4x),
|
||||
.src_rst ()
|
||||
);
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4),
|
||||
.INIT_SYNC_FF (1),
|
||||
.REG_OUTPUT (1),
|
||||
.RST_USED (0),
|
||||
.SIM_ASSERT_CHK(1)
|
||||
) u_xpm_cdc_frame_sync_pulse_inst_clk_4x_to_clk_quarter (
|
||||
.dest_pulse(frame_sync_pulse),
|
||||
.dest_clk (clk_quarter),
|
||||
.dest_rst (),
|
||||
.src_clk (clk_4x),
|
||||
.src_pulse (frame_sync_4x),
|
||||
.src_rst ()
|
||||
);
|
||||
|
||||
// ***** debug *****
|
||||
|
||||
vio_recv_top u_vio_recv_top (
|
||||
.clk (clk_quarter),
|
||||
.probe_out0(cnt_chu_seq_sync_max_vio)
|
||||
);
|
||||
|
||||
ila_recv_top u_ila_recv_top (
|
||||
.clk (clk_quarter),
|
||||
.probe0(dagc_data_in_i), // width: 12
|
||||
.probe1(dagc_data_in_q), // width: 12
|
||||
.probe2(flag_frame_sync), // width: 1
|
||||
.probe3(phase_adjust_rdy), // width: 1
|
||||
.probe4(phase_adjust_douti), // width: 10
|
||||
.probe5(phase_adjust_doutq), // width: 10
|
||||
.probe6(good_frames), // width: 9
|
||||
.probe7(bad_frames) // width: 9
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,409 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/12/20 21:52:37
|
||||
// Design Name:
|
||||
// Module Name: SCFDE_recv_FrameSync
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module SCFDE_recv_FrameSync (
|
||||
|
||||
input clk,
|
||||
input rst,
|
||||
input rst_ready,
|
||||
input [9:0] datain_i,
|
||||
input [9:0] datain_q,
|
||||
input debug_loss,
|
||||
output reg [9:0] Sync_i = 10'd0,
|
||||
output reg [9:0] Sync_q = 10'd0,
|
||||
output reg Sync_rdy = 1'b0, //判断出峰的标志位，出峰后拉高1clk
|
||||
output reg Pilot_rdy = 1'b0, //出峰后88个clk后拉高1clk，对齐导频头
|
||||
output reg flag_sync = 1'b0,
|
||||
output reg Pilot_rdy_hide1_d1 = 1'b0
|
||||
|
||||
//debug
|
||||
|
||||
);
|
||||
|
||||
//----------卷积与流水累加替代模块----------//
|
||||
|
||||
//wire [19:0] add_regi_2048;
|
||||
//wire [19:0] add_regq_2048;
|
||||
wire [18:0] add_regi_19bit;
|
||||
wire [18:0] add_regq_19bit;
|
||||
/*conv_add conv_add(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.data_i(datain_i),
|
||||
.data_q(datain_q),
|
||||
.add_regi_2048(add_regi_2048),
|
||||
.add_regq_2048(add_regq_2048)
|
||||
);*/
|
||||
wire [ 9:0] dataout_i;
|
||||
wire dout_valid_i;
|
||||
DMF DMF_i (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.din_data (datain_i),
|
||||
.din_valid (1'b1),
|
||||
.dout_dmf (add_regi_19bit),
|
||||
.dout_data (dataout_i),
|
||||
.dout_valid(dout_valid_i)
|
||||
);
|
||||
|
||||
wire [9:0] dataout_q;
|
||||
wire dout_valid_q;
|
||||
DMF DMF_q (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.din_data (datain_q),
|
||||
.din_valid (1'b1),
|
||||
.dout_dmf (add_regq_19bit),
|
||||
.dout_data (dataout_q),
|
||||
.dout_valid(dout_valid_q)
|
||||
);
|
||||
|
||||
|
||||
|
||||
//----------将实部和虚部的相关结果求近似模值----------//
|
||||
//----------6 delay----------//
|
||||
wire [19:0] reg_add11;
|
||||
wire [18:0] add_regi;
|
||||
wire [18:0] add_regq;
|
||||
wire ApproxAbs_rdy;
|
||||
|
||||
assign add_regi = (add_regi_19bit[18] == 1'd1) ? -add_regi_19bit : add_regi_19bit;
|
||||
assign add_regq = (add_regq_19bit[18] == 1'd1) ? -add_regq_19bit : add_regq_19bit;
|
||||
|
||||
ApproxAbs_v2_20bit ApproxAbs_v2_tsync4 (
|
||||
.clk (clk),
|
||||
.ND (dout_valid_i),
|
||||
.Din_I(add_regi),
|
||||
.Din_Q(add_regq),
|
||||
.Dout (reg_add11),
|
||||
.Rdy (ApproxAbs_rdy)
|
||||
);
|
||||
|
||||
|
||||
//----------将1024个相关结果流水累加----------//
|
||||
reg rst_1 = 1'b0;
|
||||
reg [7:0] rst_1_cnt = 8'b0;
|
||||
always @(posedge clk) begin
|
||||
if (!ApproxAbs_rdy) begin
|
||||
rst_1_cnt = 8'b0;
|
||||
end
|
||||
else begin
|
||||
rst_1_cnt <= rst_1_cnt > 8'd128 ? 8'd129 : rst_1_cnt + 8'd1;
|
||||
end
|
||||
rst_1 <= (rst_1_cnt < 8'd128);
|
||||
end
|
||||
wire [19:0] average_add10;
|
||||
|
||||
average_1024 average_1024 (
|
||||
.clk (clk),
|
||||
.rst (rst_1),
|
||||
.nd (ApproxAbs_rdy),
|
||||
.din (reg_add11),
|
||||
.average(average_add10)
|
||||
);
|
||||
|
||||
|
||||
//----------将和求平均值，从而得到门限----------//
|
||||
reg [19:0] reg_save1024 = 20'd0;
|
||||
reg [19:0] reg_save1024_d1 = 20'd0;
|
||||
reg [19:0] reg_save1024_d2 = 20'd0;
|
||||
reg [19:0] reg_save1024_d2_x2 = 20'd0;
|
||||
reg [19:0] reg_save_pilot;
|
||||
reg [19:0] Threshold;
|
||||
reg [ 3:0] th_control = 4'd8;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
reg_save1024 <= 20'd0;
|
||||
reg_save1024_d1 <= 20'd0;
|
||||
reg_save1024_d2 <= 20'd0;
|
||||
reg_save1024_d2_x2 <= 20'd0;
|
||||
Threshold <= 20'd0;
|
||||
end
|
||||
else begin
|
||||
reg_save1024 <= reg_add11;
|
||||
reg_save1024_d1 <= reg_save1024;
|
||||
reg_save1024_d2 <= reg_save1024_d1;
|
||||
case (th_control)
|
||||
4'd1: begin
|
||||
Threshold <= average_add10;
|
||||
reg_save1024_d2_x2 <= reg_save1024_d1;
|
||||
end
|
||||
4'd2: begin
|
||||
Threshold <= {average_add10[18:0], 1'b0};
|
||||
reg_save1024_d2_x2 <= reg_save1024_d1;
|
||||
end
|
||||
4'd3: begin
|
||||
Threshold <= average_add10 + {average_add10[18:0], 1'b0};
|
||||
reg_save1024_d2_x2 <= reg_save1024_d1;
|
||||
end
|
||||
4'd4: begin
|
||||
Threshold <= {average_add10[17:0], 2'b00};
|
||||
reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
|
||||
end
|
||||
4'd5: begin
|
||||
Threshold <= average_add10 + {average_add10[17:0], 2'b00};
|
||||
reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
|
||||
end
|
||||
4'd6: begin
|
||||
Threshold <= {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b00};
|
||||
reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0};
|
||||
end
|
||||
4'd7: begin
|
||||
Threshold <= average_add10 + {average_add10[18:0], 1'b0} + {average_add10[17:0], 2'b0};
|
||||
reg_save1024_d2_x2 <= reg_save1024_d1 + {reg_save1024_d1[18:0], 1'b0};
|
||||
end
|
||||
4'd8: begin
|
||||
Threshold <= {average_add10[16:0], 3'b000};
|
||||
reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00};
|
||||
end
|
||||
4'd9: begin
|
||||
Threshold <= average_add10 + {average_add10[16:0], 3'b000};
|
||||
reg_save1024_d2_x2 <= {reg_save1024_d1[17:0], 2'b00};
|
||||
end
|
||||
default: begin
|
||||
Threshold <= {average_add10[17:0], 2'b00};
|
||||
reg_save1024_d2_x2 <= {reg_save1024_d1[18:0], 1'b0};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//----------将相关求和后的近似模值与门限比较；若高于门限，再与相邻近似模值比较----------//
|
||||
|
||||
reg [ 6:0] counter88 = 7'd0;
|
||||
//rst之后500个clk之内不允许拉高Pilot_rdy_hide1
|
||||
reg [11:0] count_rst500 = 12'd0;
|
||||
reg [ 3:0] state_framesync;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
count_rst500 <= 15'd0;
|
||||
state_framesync <= 4'd0;
|
||||
counter88 <= 7'd0;
|
||||
reg_save_pilot <= 20'd0;
|
||||
Pilot_rdy_hide1_d1 <= 1'b0;
|
||||
flag_sync <= 1'b0;
|
||||
Sync_rdy <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case (state_framesync)
|
||||
4'd0: begin
|
||||
if (count_rst500 == 12'd32) begin //等待32个clk的rst
|
||||
count_rst500 <= 12'd0;
|
||||
state_framesync <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
count_rst500 <= count_rst500 + 12'd1;
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
end
|
||||
4'd1: begin
|
||||
if (Threshold != 20'd0) begin
|
||||
state_framesync <= 4'd2;
|
||||
end
|
||||
else begin
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
end
|
||||
4'd2: begin
|
||||
if (count_rst500 == 12'd2048) begin //等待计数过2048个clk
|
||||
count_rst500 <= 12'd0;
|
||||
state_framesync <= 4'd3;
|
||||
end
|
||||
else begin
|
||||
count_rst500 <= count_rst500 + 12'd1;
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
end
|
||||
4'd3: begin
|
||||
if ((reg_save1024_d1 > Threshold)) begin //检测到过门限值
|
||||
if ((reg_save1024_d1 >= reg_save1024) && (reg_save1024_d1 >= reg_save1024_d2)) begin
|
||||
if (reg_save1024_d1 >= 20'd128) begin
|
||||
Sync_rdy <= 1'b1;
|
||||
state_framesync <= 4'd4;
|
||||
reg_save_pilot <= reg_save1024_d1;
|
||||
end
|
||||
else begin
|
||||
Sync_rdy <= 1'b0;
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
end
|
||||
|
||||
else begin
|
||||
Sync_rdy <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
else begin
|
||||
Sync_rdy <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd4: begin
|
||||
if (counter88 == 7'd86) begin
|
||||
Sync_rdy <= 1'b0;
|
||||
flag_sync <= 1'b1;
|
||||
Pilot_rdy_hide1_d1 <= 1'b1;
|
||||
state_framesync <= 4'd5;
|
||||
end
|
||||
else if (counter88 >= 7'd32) begin
|
||||
if (reg_save_pilot >= reg_save1024_d2_x2) begin // ? reg_save_pilot是DMF滤波器输出峰值
|
||||
counter88 <= counter88 + 7'd1;
|
||||
end
|
||||
else begin
|
||||
counter88 <= 7'd0;
|
||||
state_framesync <= 4'd3;
|
||||
Sync_rdy <= 1'b0;
|
||||
end
|
||||
flag_sync <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
counter88 <= counter88 + 7'd1;
|
||||
flag_sync <= 1'b0;
|
||||
end
|
||||
end
|
||||
4'd5: begin
|
||||
flag_sync <= 1'b1;
|
||||
Pilot_rdy_hide1_d1 <= 1'b0;
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
default: begin
|
||||
if (count_rst500 == 12'd32) begin
|
||||
count_rst500 <= 12'd0;
|
||||
state_framesync <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
count_rst500 <= count_rst500 + 12'd1;
|
||||
state_framesync <= state_framesync;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//----------将输入数据打延迟，与Sync_rdy拉高的时刻同步输出----------//
|
||||
reg [9:0] datain_i_d1;
|
||||
reg [9:0] datain_q_d1;
|
||||
reg [9:0] datain_i_d2;
|
||||
reg [9:0] datain_q_d2;
|
||||
reg [9:0] datain_i_d3;
|
||||
reg [9:0] datain_q_d3;
|
||||
reg [9:0] datain_i_d4;
|
||||
reg [9:0] datain_q_d4;
|
||||
reg [9:0] datain_i_d5;
|
||||
reg [9:0] datain_q_d5;
|
||||
reg [9:0] datain_i_d6;
|
||||
reg [9:0] datain_q_d6;
|
||||
reg [9:0] datain_i_d7;
|
||||
reg [9:0] datain_q_d7;
|
||||
reg [9:0] datain_i_d8;
|
||||
reg [9:0] datain_q_d8;
|
||||
reg [9:0] datain_i_d9;
|
||||
reg [9:0] datain_q_d9;
|
||||
/*shift_ram_x shift_ram_i1 (
|
||||
.D(datain_i),
|
||||
.CLK(clk),
|
||||
.Q(datain_i_d3)
|
||||
);
|
||||
wire [9:0] datain_q_d3;
|
||||
shift_ram_x shift_ram_q1 (
|
||||
.D(datain_q),
|
||||
.CLK(clk),
|
||||
.Q(datain_q_d3)
|
||||
);*/
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
Sync_i <= 10'd0;
|
||||
Sync_q <= 10'd0;
|
||||
datain_i_d1 <= 10'd0;
|
||||
datain_q_d1 <= 10'd0;
|
||||
datain_i_d2 <= 10'd0;
|
||||
datain_q_d2 <= 10'd0;
|
||||
datain_i_d3 <= 10'd0;
|
||||
datain_q_d3 <= 10'd0;
|
||||
datain_i_d4 <= 10'd0;
|
||||
datain_q_d4 <= 10'd0;
|
||||
datain_i_d5 <= 10'd0;
|
||||
datain_q_d5 <= 10'd0;
|
||||
datain_i_d6 <= 10'd0;
|
||||
datain_q_d6 <= 10'd0;
|
||||
datain_i_d7 <= 10'd0;
|
||||
datain_q_d7 <= 10'd0;
|
||||
datain_i_d8 <= 10'd0;
|
||||
datain_q_d8 <= 10'd0;
|
||||
datain_i_d9 <= 10'd0;
|
||||
datain_q_d9 <= 10'd0;
|
||||
end
|
||||
else begin
|
||||
datain_i_d1 <= datain_i;
|
||||
datain_q_d1 <= datain_q;
|
||||
datain_i_d2 <= datain_i_d1;
|
||||
datain_q_d2 <= datain_q_d1;
|
||||
datain_i_d3 <= datain_i_d2;
|
||||
datain_q_d3 <= datain_q_d2;
|
||||
datain_i_d4 <= datain_i_d3;
|
||||
datain_q_d4 <= datain_q_d3;
|
||||
datain_i_d5 <= datain_i_d4;
|
||||
datain_q_d5 <= datain_q_d4;
|
||||
datain_i_d6 <= datain_i_d5;
|
||||
datain_q_d6 <= datain_q_d5;
|
||||
datain_i_d7 <= datain_i_d6;
|
||||
datain_q_d7 <= datain_q_d6;
|
||||
datain_i_d8 <= datain_i_d7;
|
||||
datain_q_d8 <= datain_q_d7;
|
||||
datain_i_d9 <= datain_i_d8;
|
||||
datain_q_d9 <= datain_q_d8;
|
||||
Sync_i <= datain_i_d9;
|
||||
Sync_q <= datain_q_d9;
|
||||
end
|
||||
end
|
||||
|
||||
// `ifdef FrameSync_debug
|
||||
|
||||
/* ila_FS_inst ila_FS_inst(
|
||||
.clk(clk),
|
||||
.probe0(datain_i),//10
|
||||
.probe1(datain_q),//10
|
||||
.probe2(rst),//1
|
||||
.probe3(Pilot_rdy_hide1_d1),//1
|
||||
.probe4(reg_save1024_d2_x2),//20
|
||||
.probe5(average_add10),//20
|
||||
.probe6(Threshold),//20
|
||||
.probe7(reg_save1024_d1),//20
|
||||
.probe8(debug_loss),//1
|
||||
.probe9(flag_sync),//1
|
||||
.probe10(state_framesync),//4
|
||||
.probe11(counter88),//7
|
||||
.probe12(Sync_rdy),//1
|
||||
.probe13(th_control)//4
|
||||
|
||||
);*/
|
||||
|
||||
// ILA LARGE
|
||||
/*ila_large ila_MF_large_inst(
|
||||
.clk(clk),
|
||||
.probe0(datain_i[9:0]),
|
||||
.probe1({rst_ready,rst,Pilot_rdy_hide1})
|
||||
);*/
|
||||
|
||||
// `endif
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,568 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/12/18 16:00:24
|
||||
// Design Name:
|
||||
// Module Name: SC_FDE_TOP
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module SC_FDE_TOP (
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input EQUenable_vio, //为1时启用均衡
|
||||
|
||||
input [7:0] Zerozone_vio, //零域估计，默认值为8'd29
|
||||
|
||||
input flag_ow_left, //在一帧内，与第一个数据段的pilot的ow第一个nd对齐
|
||||
input nd,
|
||||
input [9:0] dini,
|
||||
input [9:0] dinq,
|
||||
|
||||
output nd_SC_FDE_dout,
|
||||
output [9:0] SC_FDE_douti,
|
||||
output [9:0] SC_FDE_doutq,
|
||||
|
||||
// debug,溢出标志
|
||||
output flagoverflow_fftpilot_26to14, //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||||
output flagoverflow_ChnZF_26to18, //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||||
output flagoverflow_comdiv_34to20i, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
output flagoverflow_comdiv_34to20q, //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到18
|
||||
output flagoverflow_ifftzero_29to17i, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
output flagoverflow_ifftzero_29to17q, //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
output flagoverflow_MMSEdiv_divisor_31to28, //第2个除法器，即MMSE除法的分母截位，31截到28
|
||||
output flagoverflow_divmmse_34to11, //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
|
||||
output flagoverflow_ifftindata_28to20i, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output flagoverflow_ifftindata_28to20q, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output flagoverflow_fftdata_26to16i, //数据段ow的fft输出截位，26截到16
|
||||
output flagoverflow_fftdata_26to16q, //数据段ow的fft输出截位，26截到16
|
||||
output flagoverflow_FDE_dataout_29to10i, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
output flagoverflow_FDE_dataout_29to10q //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
);
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------导频和数据ow的缓存--------------------------------------------//
|
||||
//----------------------还负责计算正负导频头的和与差。流水得到结果用于信道估计----------------------------//
|
||||
//数据的fifo，4个
|
||||
wire [9:0] din_data1i;
|
||||
wire [9:0] din_data1q;
|
||||
wire wr_en_data1;
|
||||
wire [9:0] din_data2i;
|
||||
wire [9:0] din_data2q;
|
||||
wire wr_en_data2;
|
||||
wire flag_dataow; //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||||
wire flag_ChnEstFFT_done; //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
|
||||
//正负导频段的加减结果
|
||||
wire nd_pilot2;
|
||||
wire [9:0] pilot_datai;
|
||||
wire [9:0] pilot_dataq;
|
||||
wire [9:0] pilot_noisei;
|
||||
wire [9:0] pilot_noiseq;
|
||||
|
||||
data_ow data_ow_djy (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.flag_ow_left(flag_ow_left),
|
||||
.nd (nd),
|
||||
.dini (dini),
|
||||
.dinq (dinq),
|
||||
|
||||
.din_data1i (din_data1i),
|
||||
.din_data1q (din_data1q),
|
||||
.wr_en_data1(wr_en_data1),
|
||||
.din_data2i (din_data2i),
|
||||
.din_data2q (din_data2q),
|
||||
.wr_en_data2(wr_en_data2),
|
||||
.flag_dataow(flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||||
|
||||
.nd_pilot2 (nd_pilot2),
|
||||
.pilot_datai (pilot_datai),
|
||||
.pilot_dataq (pilot_dataq),
|
||||
.pilot_noisei(pilot_noisei),
|
||||
.pilot_noiseq(pilot_noiseq)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------data数据ow的fifo，4个--------------------------------------------//
|
||||
wire rd_en_data1;
|
||||
wire [9:0] dout_data1i;
|
||||
wire full_data1i;
|
||||
wire empty_data1i;
|
||||
fifo_ow256 fifo_data_ow1i (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk), // input wire rd_clk
|
||||
.din (din_data1i), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_data1), // input wire wr_en
|
||||
.rd_en (rd_en_data1), // input wire rd_en
|
||||
.dout (dout_data1i), // output wire [9 : 0] dout
|
||||
.full (full_data1i), // output wire full
|
||||
.empty (empty_data1i) // output wire empty
|
||||
);
|
||||
|
||||
wire [9:0] dout_data1q;
|
||||
wire full_data1q;
|
||||
wire empty_data1q;
|
||||
fifo_ow256 fifo_data_ow1q (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk), // input wire rd_clk
|
||||
.din (din_data1q), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_data1), // input wire wr_en
|
||||
.rd_en (rd_en_data1), // input wire rd_en
|
||||
.dout (dout_data1q), // output wire [9 : 0] dout
|
||||
.full (full_data1q), // output wire full
|
||||
.empty (empty_data1q) // output wire empty
|
||||
);
|
||||
|
||||
wire rd_en_data2;
|
||||
wire [9:0] dout_data2i;
|
||||
wire full_data2i;
|
||||
wire empty_data2i;
|
||||
fifo_ow256 fifo_data_ow2i (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk), // input wire rd_clk
|
||||
.din (din_data2i), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_data2), // input wire wr_en
|
||||
.rd_en (rd_en_data2), // input wire rd_en
|
||||
.dout (dout_data2i), // output wire [9 : 0] dout
|
||||
.full (full_data2i), // output wire full
|
||||
.empty (empty_data2i) // output wire empty
|
||||
);
|
||||
|
||||
wire [9:0] dout_data2q;
|
||||
wire full_data2q;
|
||||
wire empty_data2q;
|
||||
fifo_ow256 fifo_data_ow2q (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk(clk), // input wire wr_clk
|
||||
.rd_clk(clk), // input wire rd_clk
|
||||
.din (din_data2q), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_data2), // input wire wr_en
|
||||
.rd_en (rd_en_data2), // input wire rd_en
|
||||
.dout (dout_data2q), // output wire [9 : 0] dout
|
||||
.full (full_data2q), // output wire full
|
||||
.empty (empty_data2q) // output wire empty
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------噪声估计--------------------------------------------------//
|
||||
//--------------------------------------------噪声估计结果放大了256*49倍-----------------------------------------//
|
||||
//噪声估计结果
|
||||
wire nd_EstNoise;
|
||||
wire [27:0] EstNoise_i;
|
||||
wire [27:0] EstNoise_q;
|
||||
|
||||
Noise_Estimate Noise_Estimate_djy (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
.nd_pilot2 (nd_pilot2),
|
||||
.pilot_noisei(pilot_noisei),
|
||||
.pilot_noiseq(pilot_noiseq),
|
||||
|
||||
.nd_EstNoise(nd_EstNoise),
|
||||
.EstNoise_i (EstNoise_i),
|
||||
.EstNoise_q (EstNoise_q)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//------------------------------------------fft核，及其输入输出控制器------------------------------------------//
|
||||
reg fft_config_tvalid = 1'd0;
|
||||
wire fft_config_tready;
|
||||
reg [16:0] fft_in_i = 17'd0;
|
||||
reg [16:0] fft_in_q = 17'd0;
|
||||
reg fft_in_nd = 1'd0;
|
||||
wire fft_in_tready;
|
||||
wire [63:0] fft_out_tdata;
|
||||
wire [25:0] fft_out_i;
|
||||
wire [25:0] fft_out_q;
|
||||
wire fft_out_nd;
|
||||
wire [ 7:0] fft_index;
|
||||
|
||||
assign fft_out_i = fft_out_tdata[25:0];
|
||||
assign fft_out_q = fft_out_tdata[57:32];
|
||||
|
||||
wire m_axis_data_tlast;
|
||||
wire event_frame_started;
|
||||
wire event_tlast_unexpected;
|
||||
wire event_tlast_missing;
|
||||
wire event_status_channel_halt;
|
||||
wire event_data_in_channel_halt;
|
||||
wire event_data_out_channel_halt;
|
||||
|
||||
fft_256 fft_256 (
|
||||
.aclk (clk), // input wire aclk
|
||||
.aresetn (~rst), // input wire aresetn低有效复位，每次帧结束后复位8clk，满足核要求
|
||||
.s_axis_config_tdata (8'd1), // input wire [7 : 0] s_axis_config_tdata
|
||||
.s_axis_config_tvalid (fft_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tready (fft_config_tready), // output wire s_axis_config_tready
|
||||
// s data
|
||||
.s_axis_data_tdata ({7'd0, fft_in_q, 7'd0, fft_in_i}), // input wire [47 : 0] s_axis_data_tdata
|
||||
.s_axis_data_tvalid (fft_in_nd), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready (fft_in_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tlast (1'd0), // input wire s_axis_data_tlastn不用给这个信号
|
||||
// m data
|
||||
.m_axis_data_tdata (fft_out_tdata), // output wire [63 : 0] m_axis_data_tdata
|
||||
.m_axis_data_tuser (fft_index), // output wire [7 : 0] m_axis_data_tuser
|
||||
.m_axis_data_tvalid (fft_out_nd), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tready (1'd1), // input wire m_axis_data_tready
|
||||
.m_axis_data_tlast (m_axis_data_tlast), // output wire m_axis_data_tlast
|
||||
//flag
|
||||
.event_frame_started (event_frame_started), // output wire event_frame_started
|
||||
.event_tlast_unexpected (event_tlast_unexpected), // output wire event_tlast_unexpected
|
||||
.event_tlast_missing (event_tlast_missing), // output wire event_tlast_missing
|
||||
.event_status_channel_halt (event_status_channel_halt), // output wire event_status_channel_halt
|
||||
.event_data_in_channel_halt (event_data_in_channel_halt), // output wire event_data_in_channel_halt
|
||||
.event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt
|
||||
);
|
||||
|
||||
|
||||
reg [ 1:0] state_fft = 2'd0;
|
||||
wire nd_pilotfft;
|
||||
wire [16:0] fft_in_i_pilot;
|
||||
wire [16:0] fft_in_q_pilot;
|
||||
wire nd_datafft;
|
||||
wire [16:0] fft_in_i_data;
|
||||
wire [16:0] fft_in_q_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
fft_config_tvalid <= 1'd0;
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
state_fft <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
case (state_fft)
|
||||
//帧间复位结束后，先等待fft_config_tvalid拉高，说明fft核允许配置，先写入一次fft配置
|
||||
2'd0: begin
|
||||
if (fft_config_tready) begin
|
||||
fft_config_tvalid <= 1'd1;
|
||||
fft_in_nd <= 1'd0;
|
||||
state_fft <= state_fft + 2'd1;
|
||||
end
|
||||
else begin
|
||||
fft_config_tvalid <= 1'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
state_fft <= state_fft;
|
||||
end
|
||||
end
|
||||
//每帧一开始fft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出)
|
||||
2'd1: begin
|
||||
fft_config_tvalid <= 1'd0;
|
||||
if (flag_ChnEstFFT_done) begin
|
||||
fft_in_i <= fft_in_i_data;
|
||||
fft_in_q <= fft_in_q_data;
|
||||
fft_in_nd <= nd_datafft;
|
||||
state_fft <= state_fft + 2'd1;
|
||||
end
|
||||
else begin
|
||||
fft_in_i <= fft_in_i_pilot;
|
||||
fft_in_q <= fft_in_q_pilot;
|
||||
fft_in_nd <= nd_pilotfft;
|
||||
state_fft <= state_fft;
|
||||
end
|
||||
end
|
||||
//nd_pilot2拉高，说明下一个征服导频头处理完毕，fft输入控制权交还信道估计模块
|
||||
2'd2: begin
|
||||
fft_config_tvalid <= 1'd0;
|
||||
if (nd_pilot2) begin
|
||||
fft_in_i <= fft_in_i_pilot;
|
||||
fft_in_q <= fft_in_q_pilot;
|
||||
fft_in_nd <= nd_pilotfft;
|
||||
state_fft <= 2'd1;
|
||||
end
|
||||
else begin
|
||||
fft_in_i <= fft_in_i_data;
|
||||
fft_in_q <= fft_in_q_data;
|
||||
fft_in_nd <= nd_datafft;
|
||||
state_fft <= state_fft;
|
||||
end
|
||||
end
|
||||
default: state_fft <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
//------------------------------------------ifft核，及其输入输出控制器------------------------------------------//
|
||||
reg ifft_config_tvalid = 1'd0;
|
||||
wire ifft_config_tready;
|
||||
reg [19:0] ifft_in_i = 20'd0;
|
||||
reg [19:0] ifft_in_q = 20'd0;
|
||||
reg ifft_in_nd = 1'd0;
|
||||
wire ifft_in_tready;
|
||||
wire [63:0] ifft_out_tdata;
|
||||
wire [28:0] ifft_out_i;
|
||||
wire [28:0] ifft_out_q;
|
||||
wire ifft_out_nd;
|
||||
wire [ 7:0] ifft_index;
|
||||
|
||||
assign ifft_out_i = ifft_out_tdata[28:0];
|
||||
assign ifft_out_q = ifft_out_tdata[60:32];
|
||||
|
||||
wire m_axis_data_tlast_ifft;
|
||||
wire event_frame_started_ifft;
|
||||
wire event_tlast_unexpected_ifft;
|
||||
wire event_tlast_missing_ifft;
|
||||
wire event_status_channel_halt_ifft;
|
||||
wire event_data_in_channel_halt_ifft;
|
||||
wire event_data_out_channel_halt_ifft;
|
||||
|
||||
ifft_256 ifft_256 (
|
||||
.aclk (clk), // input wire aclk
|
||||
.aresetn(~rst), // input wire aresetn
|
||||
|
||||
.s_axis_config_tdata (8'd0), // input wire [7 : 0] s_axis_config_tdata
|
||||
.s_axis_config_tvalid(ifft_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tready(ifft_config_tready), // output wire s_axis_config_tready
|
||||
|
||||
.s_axis_data_tdata ({4'd0, ifft_in_q, 4'd0, ifft_in_i}), // input wire [47 : 0] s_axis_data_tdata
|
||||
.s_axis_data_tvalid(ifft_in_nd), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(ifft_in_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tlast (1'd0), // input wire s_axis_data_tlast
|
||||
|
||||
.m_axis_data_tdata (ifft_out_tdata), // output wire [63 : 0] m_axis_data_tdata
|
||||
.m_axis_data_tuser (ifft_index), // output wire [7 : 0] m_axis_data_tuser
|
||||
.m_axis_data_tvalid(ifft_out_nd), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tready(1'd1), // input wire m_axis_data_tready
|
||||
.m_axis_data_tlast (m_axis_data_tlast_ifft), // output wire m_axis_data_tlast
|
||||
|
||||
.event_frame_started (event_frame_started_ifft), // output wire event_frame_started
|
||||
.event_tlast_unexpected (event_tlast_unexpected_ifft), // output wire event_tlast_unexpected
|
||||
.event_tlast_missing (event_tlast_missing_ifft), // output wire event_tlast_missing
|
||||
.event_status_channel_halt (event_status_channel_halt_ifft), // output wire event_status_channel_halt
|
||||
.event_data_in_channel_halt (event_data_in_channel_halt_ifft), // output wire event_data_in_channel_halt
|
||||
.event_data_out_channel_halt(event_data_out_channel_halt_ifft) // output wire event_data_out_channel_halt
|
||||
);
|
||||
|
||||
|
||||
reg [ 1:0] state_ifft = 2'd0;
|
||||
wire nd_pilotifft;
|
||||
wire [19:0] ifft_in_i_pilot;
|
||||
wire [19:0] ifft_in_q_pilot;
|
||||
wire nd_dataifft;
|
||||
wire [19:0] ifft_in_i_data;
|
||||
wire [19:0] ifft_in_q_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ifft_config_tvalid <= 1'd0;
|
||||
ifft_in_i <= 20'd0;
|
||||
ifft_in_q <= 20'd0;
|
||||
ifft_in_nd <= 1'd0;
|
||||
state_ifft <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
case (state_ifft)
|
||||
//帧间复位结束后，先等待ifft_config_tvalid拉高，说明ifft核允许配置，先写入一次ifft配置
|
||||
2'd0: begin
|
||||
if (ifft_config_tready) begin
|
||||
ifft_config_tvalid <= 1'd1;
|
||||
ifft_in_nd <= 1'd0;
|
||||
state_ifft <= state_ifft + 2'd1;
|
||||
end
|
||||
else begin
|
||||
ifft_config_tvalid <= 1'd0;
|
||||
ifft_in_nd <= 1'd0;
|
||||
state_ifft <= state_ifft;
|
||||
end
|
||||
end
|
||||
//每帧一开始ifft核输入交给信道估计模块，直到flag_ChnEstFFT_done到来，说明信道估计两次fft输入完毕(Chn_Estimate给出)
|
||||
2'd1: begin
|
||||
ifft_config_tvalid <= 1'd0;
|
||||
if (flag_ChnEstFFT_done) begin
|
||||
ifft_in_i <= ifft_in_i_data;
|
||||
ifft_in_q <= ifft_in_q_data;
|
||||
ifft_in_nd <= nd_dataifft;
|
||||
state_ifft <= state_ifft + 2'd1;
|
||||
end
|
||||
else begin
|
||||
ifft_in_i <= ifft_in_i_pilot;
|
||||
ifft_in_q <= ifft_in_q_pilot;
|
||||
ifft_in_nd <= nd_pilotifft;
|
||||
state_ifft <= state_ifft;
|
||||
end
|
||||
end
|
||||
//nd_pilot2拉高，说明下一个征服导频头处理完毕，ifft输入控制权交还信道估计模块
|
||||
2'd2: begin
|
||||
ifft_config_tvalid <= 1'd0;
|
||||
if (nd_pilot2) begin
|
||||
ifft_in_i <= ifft_in_i_pilot;
|
||||
ifft_in_q <= ifft_in_q_pilot;
|
||||
ifft_in_nd <= nd_pilotifft;
|
||||
state_ifft <= 2'd1;
|
||||
end
|
||||
else begin
|
||||
ifft_in_i <= ifft_in_i_data;
|
||||
ifft_in_q <= ifft_in_q_data;
|
||||
ifft_in_nd <= nd_dataifft;
|
||||
state_ifft <= state_ifft;
|
||||
end
|
||||
end
|
||||
default: state_ifft <= 2'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------------------MMSE信道估计结果RAM--------------------------------------------------//
|
||||
wire write_MMSE_wea;
|
||||
wire [ 7:0] addrin_MMSE;
|
||||
wire [ 7:0] addrout_MMSE;
|
||||
wire [21:0] din_MMSE;
|
||||
wire [21:0] dout_MMSE;
|
||||
|
||||
RAM_ChnEst_MMSE RAM_ChnEst_MMSE (
|
||||
.clka (clk), // input wire clka
|
||||
.wea (write_MMSE_wea), // input wire [0 : 0] wea
|
||||
.addra(addrin_MMSE), // input wire [7 : 0] addra
|
||||
.dina (din_MMSE), // input wire [21 : 0] dina
|
||||
.clkb (clk), // input wire clkb
|
||||
.addrb(addrout_MMSE), // input wire [7 : 0] addrb
|
||||
.doutb(dout_MMSE) // output wire [21 : 0] doutb
|
||||
);
|
||||
|
||||
//----------------------------------------------------MMSE信道估计模块--------------------------------------------------//
|
||||
Chn_Estimate Chn_Estimate_djy (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
//零域估计，默认值为8'd29
|
||||
.Zerozone_vio (Zerozone_vio),
|
||||
//增强导频序列
|
||||
.nd_pilot2 (nd_pilot2),
|
||||
.pilot_datai (pilot_datai),
|
||||
.pilot_dataq (pilot_dataq),
|
||||
//噪声估计结果
|
||||
.nd_EstNoise (nd_EstNoise),
|
||||
.EstNoise_i (EstNoise_i),
|
||||
.EstNoise_q (EstNoise_q),
|
||||
//fft核
|
||||
.fft_out_i (fft_out_i),
|
||||
.fft_out_q (fft_out_q),
|
||||
.fft_out_nd (fft_out_nd),
|
||||
.fft_index (fft_index),
|
||||
.fft_in_i (fft_in_i_pilot),
|
||||
.fft_in_q (fft_in_q_pilot),
|
||||
.fft_in_nd (nd_pilotfft),
|
||||
//ifft核
|
||||
.ifft_out_i (ifft_out_i),
|
||||
.ifft_out_q (ifft_out_q),
|
||||
.ifft_out_nd (ifft_out_nd),
|
||||
.ifft_index (ifft_index),
|
||||
.ifft_in_i (ifft_in_i_pilot),
|
||||
.ifft_in_q (ifft_in_q_pilot),
|
||||
.ifft_in_nd (nd_pilotifft),
|
||||
//信道估计两次fft输入完毕后拉高1clk
|
||||
.flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk
|
||||
//MMSE信道估计结果RAM
|
||||
.write_MMSE_wea (write_MMSE_wea),
|
||||
.addrin_MMSE (addrin_MMSE),
|
||||
.din_MMSE (din_MMSE),
|
||||
//debug,溢出标志
|
||||
.flagoverflow_fftpilot_26to14 (flagoverflow_fftpilot_26to14), //第1个fft结果截位，即导频fft结果的截位，26截到14
|
||||
.flagoverflow_ChnZF_26to18 (flagoverflow_ChnZF_26to18), //第2个fft结果截位，即ZF信道估计结果的截位，26截到18
|
||||
.flagoverflow_comdiv_34to20i (flagoverflow_comdiv_34to20i), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20
|
||||
.flagoverflow_comdiv_34to20q (flagoverflow_comdiv_34to20q), //第1个除法器结果截位，即复数除法结果的截位，得到没有去噪的ZF估计，34截到20
|
||||
.flagoverflow_ifftzero_29to17i (flagoverflow_ifftzero_29to17i), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
.flagoverflow_ifftzero_29to17q (flagoverflow_ifftzero_29to17q), //第1个ifft结果截位，即ZF零域估计处，结果先除掉低8位，29-8=21截到17
|
||||
.flagoverflow_MMSEdiv_divisor_31to28(flagoverflow_MMSEdiv_divisor_31to28), //第2个除法器，即MMSE除法的分母截位，31截到28
|
||||
.flagoverflow_divmmse_34to11 (flagoverflow_divmmse_34to11) //第2个除法器结果截位，即MMSE信道估计结果的截位，34截到11
|
||||
);
|
||||
|
||||
//------------------------------------------------------------均衡模块-------------------------------------------------------//
|
||||
|
||||
data_equalizer data_equalizer_djy (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.EQUenable_vio (EQUenable_vio),
|
||||
//进程flag
|
||||
.nd_pilot2 (nd_pilot2),
|
||||
.flag_ChnEstFFT_done (flag_ChnEstFFT_done), //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
|
||||
//数据的fifo，4个
|
||||
.dout_data1i (dout_data1i),
|
||||
.dout_data1q (dout_data1q),
|
||||
.rd_en_data1 (rd_en_data1),
|
||||
.dout_data2i (dout_data2i),
|
||||
.dout_data2q (dout_data2q),
|
||||
.rd_en_data2 (rd_en_data2),
|
||||
.flag_dataow (flag_dataow), //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||||
//fft核
|
||||
.fft_out_i (fft_out_i),
|
||||
.fft_out_q (fft_out_q),
|
||||
.fft_out_nd (fft_out_nd),
|
||||
.fft_index (fft_index),
|
||||
.fft_in_i (fft_in_i_data),
|
||||
.fft_in_q (fft_in_q_data),
|
||||
.fft_in_nd (nd_datafft),
|
||||
//ifft核
|
||||
.ifft_out_i (ifft_out_i),
|
||||
.ifft_out_q (ifft_out_q),
|
||||
.ifft_out_nd (ifft_out_nd),
|
||||
.ifft_index (ifft_index),
|
||||
.ifft_in_i (ifft_in_i_data),
|
||||
.ifft_in_q (ifft_in_q_data),
|
||||
.ifft_in_nd (nd_dataifft),
|
||||
//MMSE信道估计结果RAM
|
||||
.addrout_MMSE (addrout_MMSE),
|
||||
.dout_MMSE (dout_MMSE),
|
||||
//均衡结果输出
|
||||
.nd_SC_FDE_dout (nd_SC_FDE_dout),
|
||||
.SC_FDE_douti (SC_FDE_douti),
|
||||
.SC_FDE_doutq (SC_FDE_doutq),
|
||||
//debug,溢出标志
|
||||
.flagoverflow_ifftindata_28to20i (flagoverflow_ifftindata_28to20i), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
.flagoverflow_ifftindata_28to20q (flagoverflow_ifftindata_28to20q), //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
.flagoverflow_fftdata_26to16i (flagoverflow_fftdata_26to16i), //数据段ow的fft输出截位，26截到16
|
||||
.flagoverflow_fftdata_26to16q (flagoverflow_fftdata_26to16q), //数据段ow的fft输出截位，26截到16
|
||||
.flagoverflow_FDE_dataout_29to10i(flagoverflow_FDE_dataout_29to10i), //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
.flagoverflow_FDE_dataout_29to10q(flagoverflow_FDE_dataout_29to10q) //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
);
|
||||
|
||||
// ila_scfde u_ila_scfde (
|
||||
// .clk (clk), // input wire clk
|
||||
// .probe0(flag_ow_left), // 1
|
||||
// .probe1(ifft_out_nd), // 1
|
||||
// .probe2(ifft_index), // 8
|
||||
// .probe3(ifft_out_tdata) //64
|
||||
// );
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,889 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 21:03:55
|
||||
// Design Name:
|
||||
// Module Name: TSync_Abs_new16
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//4倍过采样内插至16
|
||||
//帧内不更新
|
||||
|
||||
module TSync_Abs_new16(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input framesync_Interpolation,
|
||||
output reg framesync_out16 = 1'd0,
|
||||
|
||||
input [9:0] datain1_i,
|
||||
input [9:0] datain1_q,
|
||||
input [9:0] datain2_i,
|
||||
input [9:0] datain2_q,
|
||||
input [9:0] datain3_i,
|
||||
input [9:0] datain3_q,
|
||||
input [9:0] datain4_i,
|
||||
input [9:0] datain4_q,
|
||||
|
||||
output reg TSyncout_nd = 1'd0,
|
||||
output reg [9:0] TSyncout_i = 10'd0,
|
||||
output reg [9:0] TSyncout_q = 10'd0,
|
||||
|
||||
//debug
|
||||
output reg [1:0] cnt = 2'd0, //12.5
|
||||
|
||||
output reg [1:0] flag_clk16 = 2'd0, //12.5
|
||||
output reg [1:0] flag_num16 = 2'd0
|
||||
|
||||
|
||||
);
|
||||
|
||||
//-------------------------------------状态机控制----------------------------------------------//
|
||||
|
||||
|
||||
// reg [3:0] cnt = 4'd0;
|
||||
reg nd_1 = 1'd0;
|
||||
|
||||
reg flag_framesync = 1'd0;
|
||||
// reg [3:0] flag_clk = 4'd0;
|
||||
// reg [1:0] flag_num = 2'd0;
|
||||
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
cnt <= 2'd3;
|
||||
nd_1 <= 1'd0;
|
||||
|
||||
TSyncout_nd <= 1'd0;
|
||||
TSyncout_i <= 10'd0;
|
||||
TSyncout_q <= 10'd0;
|
||||
|
||||
flag_framesync <= 1'd0;
|
||||
framesync_out16 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 2'd1;
|
||||
|
||||
if(cnt == 2'd3) nd_1 <= 1'd1;
|
||||
else nd_1 <= 1'd0;
|
||||
|
||||
if(framesync_Interpolation) begin
|
||||
if(cnt == flag_clk16) begin
|
||||
framesync_out16 <= 1'd1;
|
||||
TSyncout_nd <= 1'd1;
|
||||
case(flag_num16)
|
||||
2'd0:begin
|
||||
TSyncout_i <= datain1_i;
|
||||
TSyncout_q <= datain1_q;
|
||||
end
|
||||
2'd1:begin
|
||||
TSyncout_i <= datain2_i;
|
||||
TSyncout_q <= datain2_q;
|
||||
end
|
||||
2'd2:begin
|
||||
TSyncout_i <= datain3_i;
|
||||
TSyncout_q <= datain3_q;
|
||||
end
|
||||
2'd3:begin
|
||||
TSyncout_i <= datain4_i;
|
||||
TSyncout_q <= datain4_q;
|
||||
end
|
||||
endcase
|
||||
flag_framesync <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
framesync_out16 <= 1'd0;
|
||||
TSyncout_nd <= 1'd0;
|
||||
flag_framesync <= 1'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
framesync_out16 <= 1'd0;
|
||||
flag_framesync <= 1'd0;
|
||||
TSyncout_nd <= 1'd0;
|
||||
TSyncout_i <= 10'd0;
|
||||
TSyncout_q <= 10'd0;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------求近似模值Abs，delay=6-------------------------------------//
|
||||
wire [10:0] data_1;
|
||||
ApproxAbs_v2 ApproxAbs_v2_tsync1 (
|
||||
.clk (clk),
|
||||
.ND (1'd1),
|
||||
.Din_I (datain1_i),
|
||||
.Din_Q (datain1_q),
|
||||
.Dout (data_1),
|
||||
.Rdy ()
|
||||
);
|
||||
|
||||
wire [10:0] data_2;
|
||||
ApproxAbs_v2 ApproxAbs_v2_tsync2 (
|
||||
.clk (clk),
|
||||
.ND (1'd1),
|
||||
.Din_I (datain2_i),
|
||||
.Din_Q (datain2_q),
|
||||
.Dout (data_2),
|
||||
.Rdy ()
|
||||
);
|
||||
|
||||
wire [10:0] data_3;
|
||||
ApproxAbs_v2 ApproxAbs_v2_tsync3 (
|
||||
.clk (clk),
|
||||
.ND (1'd1),
|
||||
.Din_I (datain3_i),
|
||||
.Din_Q (datain3_q),
|
||||
.Dout (data_3),
|
||||
.Rdy ()
|
||||
);
|
||||
|
||||
wire [10:0] data_4;
|
||||
ApproxAbs_v2 ApproxAbs_v2_tsync4 (
|
||||
.clk (clk),
|
||||
.ND (1'd1),
|
||||
.Din_I (datain4_i),
|
||||
.Din_Q (datain4_q),
|
||||
.Dout (data_4),
|
||||
.Rdy ()
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg nd_2 = 1'd0;
|
||||
reg nd_3 = 1'd0;
|
||||
reg nd_4 = 1'd0;
|
||||
reg nd_5 = 1'd0;
|
||||
reg nd_6 = 1'd0;
|
||||
reg nd_7 = 1'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
nd_2 <= nd_1;
|
||||
nd_3 <= nd_2;
|
||||
nd_4 <= nd_3;
|
||||
nd_5 <= nd_4;
|
||||
|
||||
nd_6 <= nd_5;
|
||||
nd_7 <= nd_6;
|
||||
end
|
||||
|
||||
|
||||
|
||||
//-------------------------------------累加，delay=1-------------------------------------------------//
|
||||
reg [19:0] acc_01 = 20'd0;
|
||||
reg [19:0] acc_02 = 20'd0;
|
||||
reg [19:0] acc_03 = 20'd0;
|
||||
reg [19:0] acc_04 = 20'd0;
|
||||
reg [19:0] acc_05 = 20'd0;
|
||||
reg [19:0] acc_06 = 20'd0;
|
||||
reg [19:0] acc_07 = 20'd0;
|
||||
reg [19:0] acc_08 = 20'd0;
|
||||
reg [19:0] acc_09 = 20'd0;
|
||||
reg [19:0] acc_10 = 20'd0;
|
||||
reg [19:0] acc_11 = 20'd0;
|
||||
reg [19:0] acc_12 = 20'd0;
|
||||
reg [19:0] acc_13 = 20'd0;
|
||||
reg [19:0] acc_14 = 20'd0;
|
||||
reg [19:0] acc_15 = 20'd0;
|
||||
reg [19:0] acc_16 = 20'd0;
|
||||
|
||||
reg [1:0] cnt_4 =2'd0;
|
||||
reg nd_acc = 1'd0;
|
||||
reg nd_flag = 1'd0;
|
||||
|
||||
reg flag_cnt_0 = 1'd0;
|
||||
|
||||
reg [5:0] cnt_64 = 6'd0;
|
||||
reg [6:0] cnt_128 = 7'd0;
|
||||
reg [7:0] cnt_256 = 8'd0;
|
||||
reg [8:0] cnt_512 = 9'd0;
|
||||
reg [9:0] cnt_1024 = 10'd0;
|
||||
|
||||
reg [2:0] state_tsync4 = 3'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
acc_01 <= 20'd0;
|
||||
acc_02 <= 20'd0;
|
||||
acc_03 <= 20'd0;
|
||||
acc_04 <= 20'd0;
|
||||
acc_05 <= 20'd0;
|
||||
acc_06 <= 20'd0;
|
||||
acc_07 <= 20'd0;
|
||||
acc_08 <= 20'd0;
|
||||
acc_09 <= 20'd0;
|
||||
acc_10 <= 20'd0;
|
||||
acc_11 <= 20'd0;
|
||||
acc_12 <= 20'd0;
|
||||
acc_13 <= 20'd0;
|
||||
acc_14 <= 20'd0;
|
||||
acc_15 <= 20'd0;
|
||||
acc_16 <= 20'd0;
|
||||
|
||||
cnt_4 <= 2'd3;
|
||||
nd_acc <= 1'd0;
|
||||
nd_flag<= 1'd0;
|
||||
|
||||
cnt_64 <= 6'd0;
|
||||
cnt_128 <= 7'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
cnt_512 <= 9'd0;
|
||||
cnt_1024 <= 10'd0;
|
||||
|
||||
flag_cnt_0 <= 1'd0;
|
||||
|
||||
state_tsync4 <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
if(nd_6) cnt_4 <= 4'd0;
|
||||
else cnt_4 <= cnt_4 + 4'd1;
|
||||
|
||||
if (nd_6) nd_flag <= 1'd1;
|
||||
else nd_flag <= nd_flag;
|
||||
|
||||
case(state_tsync4)
|
||||
//等待第一次的数据幅值估计结果（与nd_7对齐）
|
||||
3'd0:begin
|
||||
if(nd_6) state_tsync4 <= 3'd1;
|
||||
else state_tsync4 <= state_tsync4;
|
||||
end
|
||||
//此clk内nd_7、第一次的数据幅值估计结果同时到来，cnt_4结果为4'd0。
|
||||
//累积，直到最后一个累积结束后转至下一状态
|
||||
3'd1:begin
|
||||
if(cnt_4==2'd3) begin
|
||||
cnt_64 <=cnt_64 +6'd1;
|
||||
cnt_128 <=cnt_128 +7'd1;
|
||||
cnt_256 <=cnt_256 +8'd1;
|
||||
cnt_512 <=cnt_512 +9'd1;
|
||||
cnt_1024 <=cnt_1024 +10'd1;
|
||||
|
||||
if(cnt_512==9'd511) flag_cnt_0 <= 1'd1;
|
||||
else flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_64 <= cnt_64;
|
||||
cnt_128 <= cnt_128 ;
|
||||
cnt_256 <= cnt_256 ;
|
||||
cnt_512 <= cnt_512 ;
|
||||
cnt_1024 <= cnt_1024;
|
||||
flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
|
||||
if(cnt_512==9'd0) begin
|
||||
case(cnt_4)
|
||||
2'd0:begin
|
||||
acc_01 <= {9'd0,data_1};
|
||||
acc_02 <= {9'd0,data_2};
|
||||
acc_03 <= {9'd0,data_3};
|
||||
acc_04 <= {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
acc_05 <= {9'd0,data_1};
|
||||
acc_06 <= {9'd0,data_2};
|
||||
acc_07 <= {9'd0,data_3};
|
||||
acc_08 <= {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd2:begin
|
||||
acc_09 <= {9'd0,data_1};
|
||||
acc_10 <= {9'd0,data_2};
|
||||
acc_11 <= {9'd0,data_3};
|
||||
acc_12 <= {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd3:begin
|
||||
acc_13 <= {9'd0,data_1};
|
||||
acc_14 <= {9'd0,data_2};
|
||||
acc_15 <= {9'd0,data_3};
|
||||
acc_16 <= {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
case(cnt_4)
|
||||
2'd0:begin
|
||||
acc_01 <= acc_01 + {9'd0,data_1};
|
||||
acc_02 <= acc_02 + {9'd0,data_2};
|
||||
acc_03 <= acc_03 + {9'd0,data_3};
|
||||
acc_04 <= acc_04 + {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
acc_05 <= acc_05 + {9'd0,data_1};
|
||||
acc_06 <= acc_06 + {9'd0,data_2};
|
||||
acc_07 <= acc_07 + {9'd0,data_3};
|
||||
acc_08 <= acc_08 + {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd2:begin
|
||||
acc_09 <= acc_09 + {9'd0,data_1};
|
||||
acc_10 <= acc_10 + {9'd0,data_2};
|
||||
acc_11 <= acc_11 + {9'd0,data_3};
|
||||
acc_12 <= acc_12 + {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd3:begin
|
||||
acc_13 <= acc_13 + {9'd0,data_1};
|
||||
acc_14 <= acc_14 + {9'd0,data_2};
|
||||
acc_15 <= acc_15 + {9'd0,data_3};
|
||||
acc_16 <= acc_16 + {9'd0,data_4};
|
||||
|
||||
nd_acc <= 1'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if(cnt_512==9'd511&&cnt_4==2'd3) state_tsync4 <= 3'd2;
|
||||
else state_tsync4 <= state_tsync4;
|
||||
end
|
||||
3'd2:begin
|
||||
state_tsync4 <= state_tsync4;
|
||||
flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
default:state_tsync4 <= 3'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
//---------------------------------------排序找最大值，delay=3-------------------------------------------------//
|
||||
|
||||
reg [19:0] temp_1_01 = 20'd0;
|
||||
reg [19:0] temp_1_02 = 20'd0;
|
||||
reg [19:0] temp_1_03 = 20'd0;
|
||||
reg [19:0] temp_1_04 = 20'd0;
|
||||
reg [19:0] temp_1_05 = 20'd0;
|
||||
reg [19:0] temp_1_06 = 20'd0;
|
||||
reg [19:0] temp_1_07 = 20'd0;
|
||||
reg [19:0] temp_1_08 = 20'd0;
|
||||
|
||||
reg [1:0] flag_clk_1_01 =2'd0;
|
||||
reg [1:0] flag_clk_1_02 =2'd0;
|
||||
reg [1:0] flag_clk_1_03 =2'd0;
|
||||
reg [1:0] flag_clk_1_04 =2'd0;
|
||||
reg [1:0] flag_clk_1_05 =2'd0;
|
||||
reg [1:0] flag_clk_1_06 =2'd0;
|
||||
reg [1:0] flag_clk_1_07 =2'd0;
|
||||
reg [1:0] flag_clk_1_08 =2'd0;
|
||||
|
||||
reg [1:0] flag_num_1_01 =2'd0;
|
||||
reg [1:0] flag_num_1_02 =2'd0;
|
||||
reg [1:0] flag_num_1_03 =2'd0;
|
||||
reg [1:0] flag_num_1_04 =2'd0;
|
||||
reg [1:0] flag_num_1_05 =2'd0;
|
||||
reg [1:0] flag_num_1_06 =2'd0;
|
||||
reg [1:0] flag_num_1_07 =2'd0;
|
||||
reg [1:0] flag_num_1_08 =2'd0;
|
||||
|
||||
reg nd_acc1 = 1'd0;
|
||||
|
||||
//ila用
|
||||
reg [19:0] acc_01_reg = 20'd0;
|
||||
reg [19:0] acc_02_reg = 20'd0;
|
||||
reg [19:0] acc_03_reg = 20'd0;
|
||||
reg [19:0] acc_04_reg = 20'd0;
|
||||
reg [19:0] acc_05_reg = 20'd0;
|
||||
reg [19:0] acc_06_reg = 20'd0;
|
||||
reg [19:0] acc_07_reg = 20'd0;
|
||||
reg [19:0] acc_08_reg = 20'd0;
|
||||
reg [19:0] acc_09_reg = 20'd0;
|
||||
reg [19:0] acc_10_reg = 20'd0;
|
||||
reg [19:0] acc_11_reg = 20'd0;
|
||||
reg [19:0] acc_12_reg = 20'd0;
|
||||
reg [19:0] acc_13_reg = 20'd0;
|
||||
reg [19:0] acc_14_reg = 20'd0;
|
||||
reg [19:0] acc_15_reg = 20'd0;
|
||||
reg [19:0] acc_16_reg = 20'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
temp_1_01 <= 20'd0;
|
||||
temp_1_02 <= 20'd0;
|
||||
temp_1_03 <= 20'd0;
|
||||
temp_1_04 <= 20'd0;
|
||||
temp_1_05 <= 20'd0;
|
||||
temp_1_06 <= 20'd0;
|
||||
temp_1_07 <= 20'd0;
|
||||
temp_1_08 <= 20'd0;
|
||||
|
||||
flag_clk_1_01 <=2'd0;
|
||||
flag_clk_1_02 <=2'd0;
|
||||
flag_clk_1_03 <=2'd0;
|
||||
flag_clk_1_04 <=2'd0;
|
||||
flag_clk_1_05 <=2'd0;
|
||||
flag_clk_1_06 <=2'd0;
|
||||
flag_clk_1_07 <=2'd0;
|
||||
flag_clk_1_08 <=2'd0;
|
||||
|
||||
flag_num_1_01 <=2'd0;
|
||||
flag_num_1_02 <=2'd0;
|
||||
flag_num_1_03 <=2'd0;
|
||||
flag_num_1_04 <=2'd0;
|
||||
flag_num_1_05 <=2'd0;
|
||||
flag_num_1_06 <=2'd0;
|
||||
flag_num_1_07 <=2'd0;
|
||||
flag_num_1_08 <=2'd0;
|
||||
|
||||
nd_acc1 <= 1'd0;
|
||||
|
||||
//ila用
|
||||
acc_01_reg <= 20'd0;
|
||||
acc_02_reg <= 20'd0;
|
||||
acc_03_reg <= 20'd0;
|
||||
acc_04_reg <= 20'd0;
|
||||
acc_05_reg <= 20'd0;
|
||||
acc_06_reg <= 20'd0;
|
||||
acc_07_reg <= 20'd0;
|
||||
acc_08_reg <= 20'd0;
|
||||
acc_09_reg <= 20'd0;
|
||||
acc_10_reg <= 20'd0;
|
||||
acc_11_reg <= 20'd0;
|
||||
acc_12_reg <= 20'd0;
|
||||
acc_13_reg <= 20'd0;
|
||||
acc_14_reg <= 20'd0;
|
||||
acc_15_reg <= 20'd0;
|
||||
acc_16_reg <= 20'd0;
|
||||
end
|
||||
else begin
|
||||
if(nd_acc&&flag_cnt_0) begin
|
||||
nd_acc1 <= 1'd1;
|
||||
|
||||
//ila用
|
||||
acc_01_reg <= acc_01;
|
||||
acc_02_reg <= acc_02;
|
||||
acc_03_reg <= acc_03;
|
||||
acc_04_reg <= acc_04;
|
||||
acc_05_reg <= acc_05;
|
||||
acc_06_reg <= acc_06;
|
||||
acc_07_reg <= acc_07;
|
||||
acc_08_reg <= acc_08;
|
||||
acc_09_reg <= acc_09;
|
||||
acc_10_reg <= acc_10;
|
||||
acc_11_reg <= acc_11;
|
||||
acc_12_reg <= acc_12;
|
||||
acc_13_reg <= acc_13;
|
||||
acc_14_reg <= acc_14;
|
||||
acc_15_reg <= acc_15;
|
||||
acc_16_reg <= acc_16;
|
||||
//ila用
|
||||
|
||||
if(acc_01>=acc_02) begin
|
||||
temp_1_01 <= acc_01;
|
||||
flag_clk_1_01 <= 2'd0;
|
||||
flag_num_1_01 <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
temp_1_01 <= acc_02;
|
||||
flag_clk_1_01 <= 2'd0;
|
||||
flag_num_1_01 <= 2'd1;
|
||||
end
|
||||
|
||||
if(acc_03>=acc_04) begin
|
||||
temp_1_02 <= acc_03;
|
||||
flag_clk_1_02 <= 2'd0;
|
||||
flag_num_1_02 <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
temp_1_02 <= acc_04;
|
||||
flag_clk_1_02 <= 2'd0;
|
||||
flag_num_1_02 <= 2'd3;
|
||||
end
|
||||
|
||||
if(acc_05>=acc_06) begin
|
||||
temp_1_03 <= acc_05;
|
||||
flag_clk_1_03 <= 2'd1;
|
||||
flag_num_1_03 <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
temp_1_03 <= acc_06;
|
||||
flag_clk_1_03 <= 2'd1;
|
||||
flag_num_1_03 <= 2'd1;
|
||||
end
|
||||
|
||||
if(acc_07>=acc_08) begin
|
||||
temp_1_04 <= acc_07;
|
||||
flag_clk_1_04 <= 2'd1;
|
||||
flag_num_1_04 <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
temp_1_04 <= acc_08;
|
||||
flag_clk_1_04 <= 2'd1;
|
||||
flag_num_1_04 <= 2'd3;
|
||||
end
|
||||
|
||||
if(acc_09>=acc_10) begin
|
||||
temp_1_05 <= acc_09;
|
||||
flag_clk_1_05 <= 2'd2;
|
||||
flag_num_1_05 <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
temp_1_05 <= acc_10;
|
||||
flag_clk_1_05 <= 2'd2;
|
||||
flag_num_1_05 <= 2'd1;
|
||||
end
|
||||
|
||||
if(acc_11>=acc_12) begin
|
||||
temp_1_06 <= acc_11;
|
||||
flag_clk_1_06 <= 2'd2;
|
||||
flag_num_1_06 <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
temp_1_06 <= acc_12;
|
||||
flag_clk_1_06 <= 2'd2;
|
||||
flag_num_1_06 <= 2'd3;
|
||||
end
|
||||
|
||||
if(acc_13>=acc_14) begin
|
||||
temp_1_07 <= acc_13;
|
||||
flag_clk_1_07 <= 2'd3;
|
||||
flag_num_1_07 <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
temp_1_07 <= acc_14;
|
||||
flag_clk_1_07 <= 2'd3;
|
||||
flag_num_1_07 <= 2'd1;
|
||||
end
|
||||
|
||||
if(acc_15>=acc_16) begin
|
||||
temp_1_08 <= acc_15;
|
||||
flag_clk_1_08 <= 2'd3;
|
||||
flag_num_1_08 <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
temp_1_08 <= acc_16;
|
||||
flag_clk_1_08 <= 2'd3;
|
||||
flag_num_1_08 <= 2'd3;
|
||||
end
|
||||
end
|
||||
else nd_acc1 <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [19:0] temp_2_01 = 20'd0;
|
||||
reg [19:0] temp_2_02 = 20'd0;
|
||||
reg [19:0] temp_2_03 = 20'd0;
|
||||
reg [19:0] temp_2_04 = 20'd0;
|
||||
|
||||
reg [1:0] flag_clk_2_01 = 2'd0;
|
||||
reg [1:0] flag_clk_2_02 = 2'd0;
|
||||
reg [1:0] flag_clk_2_03 = 2'd0;
|
||||
reg [1:0] flag_clk_2_04 = 2'd0;
|
||||
|
||||
reg [1:0] flag_num_2_01 = 2'd0;
|
||||
reg [1:0] flag_num_2_02 = 2'd0;
|
||||
reg [1:0] flag_num_2_03 = 2'd0;
|
||||
reg [1:0] flag_num_2_04 = 2'd0;
|
||||
|
||||
reg nd_acc2 = 1'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
temp_2_01 <= 20'd0;
|
||||
temp_2_02 <= 20'd0;
|
||||
temp_2_03 <= 20'd0;
|
||||
temp_2_04 <= 20'd0;
|
||||
|
||||
flag_clk_2_01 <= 2'd0;
|
||||
flag_clk_2_02 <= 2'd0;
|
||||
flag_clk_2_03 <= 2'd0;
|
||||
flag_clk_2_04 <= 2'd0;
|
||||
|
||||
flag_num_2_01 <= 2'd0;
|
||||
flag_num_2_02 <= 2'd0;
|
||||
flag_num_2_03 <= 2'd0;
|
||||
flag_num_2_04 <= 2'd0;
|
||||
|
||||
nd_acc2 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
nd_acc2 <= nd_acc1;
|
||||
if(nd_acc1) begin
|
||||
if(temp_1_01>=temp_1_02) begin
|
||||
temp_2_01 <= temp_1_01;
|
||||
flag_clk_2_01 <= flag_clk_1_01;
|
||||
flag_num_2_01 <= flag_num_1_01;
|
||||
end
|
||||
else begin
|
||||
temp_2_01 <= temp_1_02;
|
||||
flag_clk_2_01 <= flag_clk_1_02;
|
||||
flag_num_2_01 <= flag_num_1_02;
|
||||
end
|
||||
|
||||
if(temp_1_03>=temp_1_04) begin
|
||||
temp_2_02 <= temp_1_03;
|
||||
flag_clk_2_02 <= flag_clk_1_03;
|
||||
flag_num_2_02 <= flag_num_1_03;
|
||||
end
|
||||
else begin
|
||||
temp_2_02 <= temp_1_04;
|
||||
flag_clk_2_02 <= flag_clk_1_04;
|
||||
flag_num_2_02 <= flag_num_1_04;
|
||||
end
|
||||
|
||||
if(temp_1_05>=temp_1_06) begin
|
||||
temp_2_03 <= temp_1_05;
|
||||
flag_clk_2_03 <= flag_clk_1_05;
|
||||
flag_num_2_03 <= flag_num_1_05;
|
||||
end
|
||||
else begin
|
||||
temp_2_03 <= temp_1_06;
|
||||
flag_clk_2_03 <= flag_clk_1_06;
|
||||
flag_num_2_03 <= flag_num_1_06;
|
||||
end
|
||||
|
||||
if(temp_1_07>=temp_1_08) begin
|
||||
temp_2_04 <= temp_1_07;
|
||||
flag_clk_2_04 <= flag_clk_1_07;
|
||||
flag_num_2_04 <= flag_num_1_07;
|
||||
end
|
||||
else begin
|
||||
temp_2_04 <= temp_1_08;
|
||||
flag_clk_2_04 <= flag_clk_1_08;
|
||||
flag_num_2_04 <= flag_num_1_08;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
reg [19:0] temp_3_1 = 20'd0;
|
||||
reg [19:0] temp_3_2 = 20'd0;
|
||||
|
||||
reg [1:0] flag_clk_3_1 = 2'd0;
|
||||
reg [1:0] flag_clk_3_2 = 2'd0;
|
||||
|
||||
reg [1:0] flag_num_3_1 = 2'd0;
|
||||
reg [1:0] flag_num_3_2 = 2'd0;
|
||||
|
||||
reg nd_acc3 = 1'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
temp_3_1 <= 20'd0;
|
||||
temp_3_2 <= 20'd0;
|
||||
|
||||
flag_clk_3_1 <= 2'd0;
|
||||
flag_clk_3_2 <= 2'd0;
|
||||
|
||||
flag_num_3_1 <= 2'd0;
|
||||
flag_num_3_2 <= 2'd0;
|
||||
|
||||
nd_acc3 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
nd_acc3 <= nd_acc2;
|
||||
if(nd_acc2) begin
|
||||
if(temp_2_01>=temp_2_02) begin
|
||||
temp_3_1 <= temp_2_01;
|
||||
flag_clk_3_1 <= flag_clk_2_01;
|
||||
flag_num_3_1 <= flag_num_2_01;
|
||||
end
|
||||
else begin
|
||||
temp_3_1 <= temp_2_02;
|
||||
flag_clk_3_1 <= flag_clk_2_02;
|
||||
flag_num_3_1 <= flag_num_2_02;
|
||||
end
|
||||
|
||||
if(temp_2_03>=temp_2_04) begin
|
||||
temp_3_2 <= temp_2_03;
|
||||
flag_clk_3_2 <= flag_clk_2_03;
|
||||
flag_num_3_2 <= flag_num_2_03;
|
||||
end
|
||||
else begin
|
||||
temp_3_2 <= temp_2_04;
|
||||
flag_clk_3_2 <= flag_clk_2_04;
|
||||
flag_num_3_2 <= flag_num_2_04;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------------------给采样标志,delay=1--------------------------------------//
|
||||
|
||||
reg nd_acc4 = 1'd0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
flag_clk16 <= 2'd0;
|
||||
nd_acc4 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
nd_acc4 <= nd_acc3;
|
||||
if(nd_acc3) begin
|
||||
if(temp_3_1>=temp_3_2) begin
|
||||
flag_clk16 <= flag_clk_3_1;
|
||||
flag_num16 <= flag_num_3_1;
|
||||
end
|
||||
else begin
|
||||
flag_clk16 <= flag_clk_3_2;
|
||||
flag_num16 <= flag_num_3_2;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
//ila用
|
||||
// reg [6:0] state_check = 7'd0;
|
||||
// always @(posedge clk)begin
|
||||
// if(rst)begin
|
||||
// state_check <= 7'd0;
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// cnt_tsync_shixu <= 4'd0;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= 20'd0;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// else begin
|
||||
// case(state_check)
|
||||
// 7'd0:begin
|
||||
// if(nd_acc4) begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= 7'd1;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd0;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd1:begin
|
||||
// if(flag_save) begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= 7'd2;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd2:begin
|
||||
// if(cnt==2'd3) begin
|
||||
// flag_TSync_check<= 1'd1;
|
||||
// state_check <= 7'd3;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd03:begin acc_tsync <= acc_01_reg; num_tsync <= 6'd00; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd04; end
|
||||
// 7'd04:begin acc_tsync <= acc_02_reg; num_tsync <= 6'd01; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd05; end
|
||||
// 7'd05:begin acc_tsync <= acc_03_reg; num_tsync <= 6'd02; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd06; end
|
||||
// 7'd06:begin acc_tsync <= acc_04_reg; num_tsync <= 6'd03; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd07; end
|
||||
// 7'd07:begin acc_tsync <= acc_05_reg; num_tsync <= 6'd04; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd08; end
|
||||
// 7'd08:begin acc_tsync <= acc_06_reg; num_tsync <= 6'd05; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd09; end
|
||||
// 7'd09:begin acc_tsync <= acc_07_reg; num_tsync <= 6'd06; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd10; end
|
||||
// 7'd10:begin acc_tsync <= acc_08_reg; num_tsync <= 6'd07; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd11; end
|
||||
// 7'd11:begin acc_tsync <= acc_09_reg; num_tsync <= 6'd08; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd12; end
|
||||
// 7'd12:begin acc_tsync <= acc_10_reg; num_tsync <= 6'd09; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd13; end
|
||||
// 7'd13:begin acc_tsync <= acc_11_reg; num_tsync <= 6'd10; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd14; end
|
||||
// 7'd14:begin acc_tsync <= acc_12_reg; num_tsync <= 6'd11; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd15; end
|
||||
// 7'd15:begin acc_tsync <= acc_13_reg; num_tsync <= 6'd12; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd16; end
|
||||
// 7'd16:begin acc_tsync <= acc_14_reg; num_tsync <= 6'd13; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd17; end
|
||||
// 7'd17:begin acc_tsync <= acc_15_reg; num_tsync <= 6'd14; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd18; end
|
||||
// 7'd18:begin acc_tsync <= acc_16_reg; num_tsync <= 6'd15; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd0; end
|
||||
// endcase
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
|
||||
// reg enable = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("TSyncout_i.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("TSyncout_q.txt","w"); $fclose(handle02);
|
||||
|
||||
// #10;
|
||||
// enable = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable)begin
|
||||
// if(TSyncout_nd)begin
|
||||
// handle01=$fopen("TSyncout_i.txt","a+");$fwrite(handle01,"%d\n",$signed(TSyncout_i));$fclose(handle01);
|
||||
// handle02=$fopen("TSyncout_q.txt","a+");$fwrite(handle02,"%d\n",$signed(TSyncout_q));$fclose(handle02);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
integer handle01;
|
||||
integer handle02;
|
||||
integer handle03;
|
||||
integer handle04;
|
||||
|
||||
|
||||
reg enable1 = 0;
|
||||
reg flag_save = 0;
|
||||
initial begin
|
||||
handle01=$fopen("data_1.txt","w"); $fclose(handle01);
|
||||
handle02=$fopen("data_2.txt","w"); $fclose(handle02);
|
||||
handle03=$fopen("data_3.txt","w"); $fclose(handle03);
|
||||
handle04=$fopen("data_4.txt","w"); $fclose(handle04);
|
||||
|
||||
#10;
|
||||
enable1 = 1;
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(enable1)begin
|
||||
if(nd_6) flag_save <= 1'd1;
|
||||
else flag_save <= flag_save;
|
||||
if(flag_save) begin
|
||||
handle01=$fopen("data_1.txt","a+");$fwrite(handle01,"%d\n",$signed(data_1));$fclose(handle01);
|
||||
handle02=$fopen("data_2.txt","a+");$fwrite(handle02,"%d\n",$signed(data_2));$fclose(handle02);
|
||||
handle03=$fopen("data_3.txt","a+");$fwrite(handle03,"%d\n",$signed(data_3));$fclose(handle03);
|
||||
handle04=$fopen("data_4.txt","a+");$fwrite(handle04,"%d\n",$signed(data_4));$fclose(handle04);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,472 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 21:03:55
|
||||
// Design Name:
|
||||
// Module Name: TSync_Abs_new4
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//4倍过采样不内插
|
||||
//帧内不更新
|
||||
|
||||
module TSync_Abs_new4(
|
||||
input clk,
|
||||
input rst,
|
||||
input framesync_Interpolation,
|
||||
output reg framesync_out4 = 1'd0,
|
||||
|
||||
input [9:0] dataini,
|
||||
input [9:0] datainq,
|
||||
|
||||
output reg TSyncout_nd = 1'd0,
|
||||
output reg [9:0] TSyncout_i = 10'd0,
|
||||
output reg [9:0] TSyncout_q = 10'd0,
|
||||
|
||||
//debug
|
||||
output reg [1:0] cnt = 2'd0, //12.5
|
||||
|
||||
output reg [1:0] flag_clk4 = 2'd0 //12.5
|
||||
|
||||
|
||||
);
|
||||
|
||||
//-------------------------------------状态机控制----------------------------------------------//
|
||||
|
||||
|
||||
// reg [3:0] cnt = 4'd0;
|
||||
reg nd_1 = 1'd0;
|
||||
|
||||
reg flag_framesync = 1'd0;
|
||||
|
||||
// reg [3:0] flag_clk = 4'd0;
|
||||
// reg [1:0] flag_num = 2'd0;
|
||||
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
cnt <= 2'd3;
|
||||
nd_1 <= 1'd0;
|
||||
|
||||
TSyncout_nd <= 1'd0;
|
||||
TSyncout_i <= 10'd0;
|
||||
TSyncout_q <= 10'd0;
|
||||
|
||||
flag_framesync <= 1'd0;
|
||||
framesync_out4 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 2'd1;
|
||||
|
||||
if(cnt == 2'd3) nd_1 <= 1'd1;
|
||||
else nd_1 <= 1'd0;
|
||||
if(framesync_Interpolation) begin
|
||||
if(cnt == flag_clk4) begin
|
||||
framesync_out4 <= 1'd1;
|
||||
TSyncout_nd <= 1'd1;
|
||||
TSyncout_i <= dataini;
|
||||
TSyncout_q <= datainq;
|
||||
flag_framesync <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
framesync_out4 <= 1'd0;
|
||||
TSyncout_nd <= 1'd0;
|
||||
TSyncout_i <= 10'd0;
|
||||
TSyncout_q <= 10'd0;
|
||||
flag_framesync <= 1'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
framesync_out4 <= 1'd0;
|
||||
flag_framesync <= 1'd0;
|
||||
TSyncout_nd <= 1'd0;
|
||||
TSyncout_i <= 10'd0;
|
||||
TSyncout_q <= 10'd0;
|
||||
end
|
||||
|
||||
// if(cnt == flag_clk4) begin
|
||||
// TSyncout_nd <= 1'd1;
|
||||
// TSyncout_i <= dataini;
|
||||
// TSyncout_q <= datainq;
|
||||
// end
|
||||
// else begin
|
||||
// TSyncout_nd <= 1'd0;
|
||||
// end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//---------------------------------------求近似模值Abs，delay=6-------------------------------------//
|
||||
wire [10:0] data_Abs;
|
||||
ApproxAbs_v2 ApproxAbs_v2_tsync (
|
||||
.clk (clk),
|
||||
.ND (1'd1),
|
||||
.Din_I (dataini),
|
||||
.Din_Q (datainq),
|
||||
.Dout (data_Abs),
|
||||
.Rdy ()
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg nd_2 = 1'd0;
|
||||
reg nd_3 = 1'd0;
|
||||
reg nd_4 = 1'd0;
|
||||
reg nd_5 = 1'd0;
|
||||
reg nd_6 = 1'd0;
|
||||
reg nd_7 = 1'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
nd_2 <= nd_1;
|
||||
nd_3 <= nd_2;
|
||||
nd_4 <= nd_3;
|
||||
nd_5 <= nd_4;
|
||||
|
||||
nd_6 <= nd_5;
|
||||
nd_7 <= nd_6;
|
||||
end
|
||||
|
||||
|
||||
|
||||
//-------------------------------------累加，delay=1-------------------------------------------------//
|
||||
reg [19:0] acc_01 = 20'd0;
|
||||
reg [19:0] acc_02 = 20'd0;
|
||||
reg [19:0] acc_03 = 20'd0;
|
||||
reg [19:0] acc_04 = 20'd0;
|
||||
|
||||
reg [1:0] cnt_4 =2'd0;
|
||||
reg nd_acc = 1'd0;
|
||||
reg nd_flag = 1'd0;
|
||||
|
||||
reg flag_cnt_0 = 1'd0;
|
||||
|
||||
reg [5:0] cnt_64 = 6'd0;
|
||||
reg [6:0] cnt_128 = 7'd0;
|
||||
reg [7:0] cnt_256 = 8'd0;
|
||||
reg [8:0] cnt_512 = 9'd0;
|
||||
reg [9:0] cnt_1024 = 10'd0;
|
||||
|
||||
reg [2:0] state_tsync4 = 3'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
acc_01 <= 20'd0;
|
||||
acc_02 <= 20'd0;
|
||||
acc_03 <= 20'd0;
|
||||
acc_04 <= 20'd0;
|
||||
|
||||
cnt_4 <= 2'd3;
|
||||
nd_acc <= 1'd0;
|
||||
nd_flag<= 1'd0;
|
||||
|
||||
cnt_64 <= 6'd0;
|
||||
cnt_128 <= 7'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
cnt_512 <= 9'd0;
|
||||
cnt_1024 <= 10'd0;
|
||||
|
||||
flag_cnt_0 <= 1'd0;
|
||||
|
||||
state_tsync4 <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
if(nd_6) cnt_4 <= 4'd0;
|
||||
else cnt_4 <= cnt_4 + 4'd1;
|
||||
|
||||
if (nd_6) nd_flag <= 1'd1;
|
||||
else nd_flag <= nd_flag;
|
||||
|
||||
case(state_tsync4)
|
||||
//等待第一次的数据幅值估计结果（与nd_7对齐）
|
||||
3'd0:begin
|
||||
if(nd_6) state_tsync4 <= 3'd1;
|
||||
else state_tsync4 <= state_tsync4;
|
||||
end
|
||||
//此clk内nd_7、第一次的数据幅值估计结果同时到来，cnt_4结果为4'd0。
|
||||
//累积，直到最后一个累积结束后转至下一状态
|
||||
3'd1:begin
|
||||
if(cnt_4==2'd3) begin
|
||||
cnt_64 <=cnt_64 +6'd1;
|
||||
cnt_128 <=cnt_128 +7'd1;
|
||||
cnt_256 <=cnt_256 +8'd1;
|
||||
cnt_512 <=cnt_512 +9'd1;
|
||||
cnt_1024 <=cnt_1024 +10'd1;
|
||||
|
||||
if(cnt_512==9'd511) flag_cnt_0 <= 1'd1;
|
||||
else flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_64 <= cnt_64;
|
||||
cnt_128 <= cnt_128 ;
|
||||
cnt_256 <= cnt_256 ;
|
||||
cnt_512 <= cnt_512 ;
|
||||
cnt_1024 <= cnt_1024;
|
||||
flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
|
||||
if(cnt_512==9'd0) begin
|
||||
case(cnt_4)
|
||||
2'd0:begin
|
||||
acc_01 <= {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
acc_02 <= {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd2:begin
|
||||
acc_03 <= {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd3:begin
|
||||
acc_04 <= {9'd0,data_Abs};
|
||||
nd_acc <= 1'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
case(cnt_4)
|
||||
2'd0:begin
|
||||
acc_01 <= acc_01 + {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd1:begin
|
||||
acc_02 <= acc_02 + {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd2:begin
|
||||
acc_03 <= acc_03 + {9'd0,data_Abs};
|
||||
nd_acc <= 1'd0;
|
||||
end
|
||||
2'd3:begin
|
||||
acc_04 <= acc_04 + {9'd0,data_Abs};
|
||||
nd_acc <= 1'd1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
if(cnt_512==9'd511&&cnt_4==2'd3) state_tsync4 <= 3'd2;
|
||||
else state_tsync4 <= state_tsync4;
|
||||
end
|
||||
3'd2:begin
|
||||
state_tsync4 <= state_tsync4;
|
||||
flag_cnt_0 <= 1'd0;
|
||||
end
|
||||
default:state_tsync4 <= 3'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
//---------------------------------------排序找最大值，delay=3-------------------------------------------------//
|
||||
|
||||
reg [19:0] temp_1_01 = 20'd0;
|
||||
reg [19:0] temp_1_02 = 20'd0;
|
||||
|
||||
reg [1:0] flag_clk_1_01 =2'd0;
|
||||
reg [1:0] flag_clk_1_02 =2'd0;
|
||||
|
||||
reg nd_acc1 = 1'd0;
|
||||
|
||||
//ila用
|
||||
reg [19:0] acc_01_reg = 20'd0;
|
||||
reg [19:0] acc_02_reg = 20'd0;
|
||||
reg [19:0] acc_03_reg = 20'd0;
|
||||
reg [19:0] acc_04_reg = 20'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
temp_1_01 <= 20'd0;
|
||||
temp_1_02 <= 20'd0;
|
||||
|
||||
flag_clk_1_01 <=2'd0;
|
||||
flag_clk_1_02 <=2'd0;
|
||||
|
||||
nd_acc1 <= 1'd0;
|
||||
|
||||
//ila用
|
||||
acc_01_reg <= 20'd0;
|
||||
acc_02_reg <= 20'd0;
|
||||
acc_03_reg <= 20'd0;
|
||||
acc_04_reg <= 20'd0;
|
||||
end
|
||||
else begin
|
||||
if(nd_acc&&flag_cnt_0) begin
|
||||
nd_acc1 <= 1'd1;
|
||||
|
||||
//ila用
|
||||
acc_01_reg <= acc_01;
|
||||
acc_02_reg <= acc_02;
|
||||
acc_03_reg <= acc_03;
|
||||
acc_04_reg <= acc_04;
|
||||
//ila用
|
||||
|
||||
if(acc_01>=acc_02) begin
|
||||
temp_1_01 <= acc_01;
|
||||
flag_clk_1_01 <= 2'd0;
|
||||
end
|
||||
else begin
|
||||
temp_1_01 <= acc_02;
|
||||
flag_clk_1_01 <= 2'd1;
|
||||
end
|
||||
|
||||
if(acc_03>=acc_04) begin
|
||||
temp_1_02 <= acc_03;
|
||||
flag_clk_1_02 <= 2'd2;
|
||||
end
|
||||
else begin
|
||||
temp_1_02 <= acc_04;
|
||||
flag_clk_1_02 <= 2'd3;
|
||||
end
|
||||
end
|
||||
else nd_acc1 <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------给采样标志,delay=1--------------------------------------//
|
||||
|
||||
reg nd_acc2 = 1'd0;
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
flag_clk4 <= 2'd0;
|
||||
nd_acc2 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
nd_acc2 <= nd_acc1;
|
||||
if(nd_acc1) begin
|
||||
if(temp_1_01>=temp_1_02) begin
|
||||
flag_clk4 <= flag_clk_1_01;
|
||||
end
|
||||
else begin
|
||||
flag_clk4 <= flag_clk_1_02;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
//ila用
|
||||
// reg [6:0] state_check = 7'd0;
|
||||
// always @(posedge clk)begin
|
||||
// if(rst)begin
|
||||
// state_check <= 7'd0;
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// cnt_tsync_shixu <= 4'd0;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= 20'd0;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// else begin
|
||||
// case(state_check)
|
||||
// 7'd0:begin
|
||||
// if(nd_acc4) begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= 7'd1;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd0;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd1:begin
|
||||
// if(flag_save) begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= 7'd2;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd2:begin
|
||||
// if(cnt==2'd3) begin
|
||||
// flag_TSync_check<= 1'd1;
|
||||
// state_check <= 7'd3;
|
||||
// end
|
||||
// else begin
|
||||
// flag_TSync_check<= 1'd0;
|
||||
// state_check <= state_check;
|
||||
// end
|
||||
// cnt_tsync_shixu <= 4'd1 + cnt_tsync_shixu;
|
||||
// flag_tongdao <= 1'd0;
|
||||
// acc_tsync <= acc_tsync;
|
||||
// num_tsync <= num_tsync;
|
||||
// end
|
||||
// 7'd03:begin acc_tsync <= acc_01_reg; num_tsync <= 6'd00; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd04; end
|
||||
// 7'd04:begin acc_tsync <= acc_02_reg; num_tsync <= 6'd01; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd05; end
|
||||
// 7'd05:begin acc_tsync <= acc_03_reg; num_tsync <= 6'd02; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd06; end
|
||||
// 7'd06:begin acc_tsync <= acc_04_reg; num_tsync <= 6'd03; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd07; end
|
||||
// 7'd07:begin acc_tsync <= acc_05_reg; num_tsync <= 6'd04; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd08; end
|
||||
// 7'd08:begin acc_tsync <= acc_06_reg; num_tsync <= 6'd05; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd09; end
|
||||
// 7'd09:begin acc_tsync <= acc_07_reg; num_tsync <= 6'd06; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd10; end
|
||||
// 7'd10:begin acc_tsync <= acc_08_reg; num_tsync <= 6'd07; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd11; end
|
||||
// 7'd11:begin acc_tsync <= acc_09_reg; num_tsync <= 6'd08; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd12; end
|
||||
// 7'd12:begin acc_tsync <= acc_10_reg; num_tsync <= 6'd09; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd13; end
|
||||
// 7'd13:begin acc_tsync <= acc_11_reg; num_tsync <= 6'd10; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd14; end
|
||||
// 7'd14:begin acc_tsync <= acc_12_reg; num_tsync <= 6'd11; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd15; end
|
||||
// 7'd15:begin acc_tsync <= acc_13_reg; num_tsync <= 6'd12; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd16; end
|
||||
// 7'd16:begin acc_tsync <= acc_14_reg; num_tsync <= 6'd13; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd17; end
|
||||
// 7'd17:begin acc_tsync <= acc_15_reg; num_tsync <= 6'd14; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd18; end
|
||||
// 7'd18:begin acc_tsync <= acc_16_reg; num_tsync <= 6'd15; flag_tongdao <= 1'd1; flag_TSync_check<= 1'd0; cnt_tsync_shixu <= 4'd0; state_check <=7'd0; end
|
||||
// endcase
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
|
||||
// reg enable = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("TSyncout_i.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("TSyncout_q.txt","w"); $fclose(handle02);
|
||||
|
||||
// #10;
|
||||
// enable = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable)begin
|
||||
// if(TSyncout_nd)begin
|
||||
// handle01=$fopen("TSyncout_i.txt","a+");$fwrite(handle01,"%d\n",$signed(TSyncout_i));$fclose(handle01);
|
||||
// handle02=$fopen("TSyncout_q.txt","a+");$fwrite(handle02,"%d\n",$signed(TSyncout_q));$fclose(handle02);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,196 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:44 11/14/2019
|
||||
// Design Name:
|
||||
// Module Name: TimeSync_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module TimeSync_top(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input [9:0] dini,
|
||||
input [9:0] dinq,
|
||||
|
||||
output reg rdy = 1'd0,
|
||||
output reg [9:0] douti = 10'd0,
|
||||
output reg [9:0] doutq = 10'd0,
|
||||
|
||||
input vio_tsync_inter16,//12.5
|
||||
input framesync, //帧同步标志
|
||||
output reg framesync_tsync = 1'd0, //帧同步标志
|
||||
|
||||
//debug
|
||||
output reg [1:0] cnt_tsync = 2'd0,//12.5
|
||||
output reg [3:0] flag_clk_4bit = 4'd0//12.5
|
||||
);
|
||||
|
||||
|
||||
wire [9:0] InterpdoutiA;
|
||||
wire [9:0] InterpdoutqA;
|
||||
wire [9:0] InterpdoutiB;
|
||||
wire [9:0] InterpdoutqB;
|
||||
wire [9:0] InterpdoutiC;
|
||||
wire [9:0] InterpdoutqC;
|
||||
wire [9:0] InterpdoutiD;
|
||||
wire [9:0] InterpdoutqD;
|
||||
|
||||
wire framesync_Interpolation;
|
||||
Interpolation Interpolation (
|
||||
.clk(clk),
|
||||
.framesync(framesync),
|
||||
.framesync_Interpolation(framesync_Interpolation),
|
||||
.dini(dini),
|
||||
.dinq(dinq),
|
||||
.doutiA(InterpdoutiA),
|
||||
.doutqA(InterpdoutqA),
|
||||
.doutiB(InterpdoutiB),
|
||||
.doutqB(InterpdoutqB),
|
||||
.doutiC(InterpdoutiC),
|
||||
.doutqC(InterpdoutqC),
|
||||
.doutiD(InterpdoutiD),
|
||||
.doutqD(InterpdoutqD)
|
||||
);
|
||||
|
||||
|
||||
wire rdy_4;
|
||||
wire [9:0] douti_4;
|
||||
wire [9:0] doutq_4;
|
||||
wire [1:0] cnt_4;
|
||||
wire [1:0] flag_clk4;
|
||||
wire framesync_out4;
|
||||
TSync_Abs_new4 TSync_Abs_new4 (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.framesync_Interpolation(framesync),
|
||||
.framesync_out4(framesync_out4),
|
||||
.dataini(dini),
|
||||
.datainq(dinq),
|
||||
.TSyncout_nd(rdy_4),
|
||||
.TSyncout_i(douti_4),
|
||||
.TSyncout_q(doutq_4),
|
||||
|
||||
.cnt(cnt_4),
|
||||
.flag_clk4(flag_clk4)
|
||||
);
|
||||
|
||||
|
||||
wire rdy_16;
|
||||
wire [9:0] douti_16;
|
||||
wire [9:0] doutq_16;
|
||||
wire [1:0] cnt_16;
|
||||
wire [1:0] flag_clk16;
|
||||
wire [1:0] flag_num16;
|
||||
wire framesync_out16;
|
||||
TSync_Abs_new16 TSync_Abs_new16 (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.framesync_Interpolation(framesync_Interpolation),
|
||||
.framesync_out16(framesync_out16),
|
||||
.datain1_i(InterpdoutiA),
|
||||
.datain1_q(InterpdoutqA),
|
||||
.datain2_i(InterpdoutiB),
|
||||
.datain2_q(InterpdoutqB),
|
||||
.datain3_i(InterpdoutiC),
|
||||
.datain3_q(InterpdoutqC),
|
||||
.datain4_i(InterpdoutiD),
|
||||
.datain4_q(InterpdoutqD),
|
||||
.TSyncout_nd(rdy_16),
|
||||
.TSyncout_i(douti_16),
|
||||
.TSyncout_q(doutq_16),
|
||||
|
||||
.cnt(cnt_16),
|
||||
.flag_clk16(flag_clk16),
|
||||
.flag_num16(flag_num16)
|
||||
);
|
||||
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
rdy <= 1'd0;
|
||||
douti <= 10'd0;
|
||||
doutq <= 10'd0;
|
||||
framesync_tsync <= 1'd0;
|
||||
|
||||
cnt_tsync <= 2'd0;
|
||||
flag_clk_4bit <= 4'd0;
|
||||
end
|
||||
else begin
|
||||
if(vio_tsync_inter16) begin
|
||||
rdy <= rdy_16;
|
||||
douti <= douti_16;
|
||||
doutq <= doutq_16;
|
||||
framesync_tsync <= framesync_out16;
|
||||
|
||||
cnt_tsync <= cnt_16;
|
||||
flag_clk_4bit <= {flag_clk16,flag_num16};
|
||||
end
|
||||
else begin
|
||||
rdy <= rdy_4;
|
||||
douti <= douti_4;
|
||||
doutq <= doutq_4;
|
||||
framesync_tsync <= framesync_out4;
|
||||
|
||||
cnt_tsync <= cnt_4;
|
||||
flag_clk_4bit <= {2'd0,flag_clk4};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
// integer handle05;
|
||||
// integer handle06;
|
||||
// integer handle07;
|
||||
// integer handle08;
|
||||
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("InterpdoutiA.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("InterpdoutqA.txt","w"); $fclose(handle02);
|
||||
// handle03=$fopen("InterpdoutiB.txt","w"); $fclose(handle03);
|
||||
// handle04=$fopen("InterpdoutqB.txt","w"); $fclose(handle04);
|
||||
// handle05=$fopen("InterpdoutiC.txt","w"); $fclose(handle05);
|
||||
// handle06=$fopen("InterpdoutqC.txt","w"); $fclose(handle06);
|
||||
// handle07=$fopen("InterpdoutiD.txt","w"); $fclose(handle07);
|
||||
// handle08=$fopen("InterpdoutqD.txt","w"); $fclose(handle08);
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
|
||||
// handle01=$fopen("InterpdoutiA.txt","a+");$fwrite(handle01,"%d\n",$signed(InterpdoutiA));$fclose(handle01);
|
||||
// handle02=$fopen("InterpdoutqA.txt","a+");$fwrite(handle02,"%d\n",$signed(InterpdoutqA));$fclose(handle02);
|
||||
// handle03=$fopen("InterpdoutiB.txt","a+");$fwrite(handle03,"%d\n",$signed(InterpdoutiB));$fclose(handle03);
|
||||
// handle04=$fopen("InterpdoutqB.txt","a+");$fwrite(handle04,"%d\n",$signed(InterpdoutqB));$fclose(handle04);
|
||||
// handle05=$fopen("InterpdoutiC.txt","a+");$fwrite(handle05,"%d\n",$signed(InterpdoutiC));$fclose(handle05);
|
||||
// handle06=$fopen("InterpdoutqC.txt","a+");$fwrite(handle06,"%d\n",$signed(InterpdoutqC));$fclose(handle06);
|
||||
// handle07=$fopen("InterpdoutiD.txt","a+");$fwrite(handle07,"%d\n",$signed(InterpdoutiD));$fclose(handle07);
|
||||
// handle08=$fopen("InterpdoutqD.txt","a+");$fwrite(handle08,"%d\n",$signed(InterpdoutqD));$fclose(handle08);
|
||||
|
||||
// end
|
||||
// end
|
||||
|
||||
endmodule
|
||||
+77
-53
@@ -9,16 +9,16 @@
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Create Date: 2023/12/18
|
||||
// * Update Date: 2024/03/17
|
||||
// * Update Date: 2024/07/24
|
||||
|
||||
// NOTE: 接口中的hop_wait和参数GAP_LEN均是为了等待，hop是为了跳频切换，gap是为了满足帧同步延迟,！！！将hop_wait设置为0并不能去掉改状态
|
||||
module Transmitter #(
|
||||
parameter AGC_HEADER_LEN = 2130,
|
||||
parameter AGC_HEADER_LEN = 10586,
|
||||
parameter FRAME_HEADER_LEN = 512,
|
||||
parameter BLOCK_NUM = 28,
|
||||
parameter PHASE1_LEN = 2112, // (8 cp + 256 sym)* 8 ( total 2048 valid sym)
|
||||
parameter PREFIX_LEN = 8,
|
||||
parameter CHU_SEQ_LEN = 128,
|
||||
parameter BLOCK_NUM = 42,
|
||||
parameter PHASE1_LEN = 2880, // (32 cp + 256 sym)* 10 ( total 2880 valid sym)
|
||||
parameter PREFIX_LEN = 32,
|
||||
parameter CHU_SEQ_LEN = 256,
|
||||
parameter GAP_LEN = 160
|
||||
) (
|
||||
// general
|
||||
@@ -65,10 +65,12 @@ module Transmitter #(
|
||||
|
||||
reg [ 3:0] interp;
|
||||
reg [ 3:0] cnt_interp;
|
||||
reg [13:0] agc_addr;
|
||||
wire [ 1:0] agc_data;
|
||||
reg [ 8:0] mseqs_addr;
|
||||
reg [ 8:0] mseqs_addr_d1;
|
||||
reg [ 8:0] mseqs_addr_d2;
|
||||
reg [ 6:0] chu_seq_addr;
|
||||
reg [ 7:0] chu_seq_addr = 0;
|
||||
wire [31:0] chu_seq;
|
||||
wire mseqs;
|
||||
reg [31:0] bb_wave_out_i; // shape filter result
|
||||
@@ -86,7 +88,7 @@ module Transmitter #(
|
||||
reg [ 3:0] rtz; // return to zero
|
||||
|
||||
reg [12:0] addr_tx_test = 'd0;
|
||||
wire [7:0] data_tx_test;
|
||||
wire [ 7:0] data_tx_test;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
@@ -328,7 +330,11 @@ module Transmitter #(
|
||||
|
||||
// truncation
|
||||
always @(*) begin
|
||||
if (cs == S_SEND_FRAME_HEADER) begin
|
||||
if (cs == S_SEND_AGC) begin
|
||||
m_fir_tdata_i = agc_data[0] ? 16'h8001 : 16'h7FFF;
|
||||
m_fir_tdata_q = agc_data[1] ? 16'h8001 : 16'h7FFF;
|
||||
end
|
||||
else if (cs == S_SEND_FRAME_HEADER) begin
|
||||
m_fir_tdata_i = mseqs ? 16'h8001 : 16'h7FFF;
|
||||
m_fir_tdata_q = mseqs ? 16'h8001 : 16'h7FFF;
|
||||
end
|
||||
@@ -336,7 +342,7 @@ module Transmitter #(
|
||||
m_fir_tdata_i = tx_data_src_tdata[15-:16];
|
||||
m_fir_tdata_q = tx_data_src_tdata[31-:16];
|
||||
end
|
||||
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC) begin
|
||||
else if (cs == S_SEND_CHU_POS) begin
|
||||
m_fir_tdata_i = chu_seq[15-:16];
|
||||
m_fir_tdata_q = chu_seq[31-:16];
|
||||
end
|
||||
@@ -417,11 +423,23 @@ module Transmitter #(
|
||||
end
|
||||
end
|
||||
|
||||
// chu seq addr control
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE) begin
|
||||
agc_addr <= 0;
|
||||
end
|
||||
else if (cs == S_SEND_AGC) begin
|
||||
if (fir_tvalid_in == 1'b1) begin
|
||||
agc_addr <= agc_addr + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// chu seq addr control
|
||||
always @(posedge clk) begin
|
||||
if (ns != cs) begin
|
||||
// chu_seq_addr <= 7'h7F - 7'h7; // 8 cp
|
||||
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 8 cp
|
||||
chu_seq_addr <= CHU_SEQ_LEN - PREFIX_LEN; // 32 cp
|
||||
end
|
||||
else if (cs == S_SEND_CHU_POS || cs == S_SEND_AGC || cs == S_SEND_CHU_NEG) begin
|
||||
if (fir_tvalid_in == 1'b1) begin
|
||||
@@ -456,6 +474,12 @@ module Transmitter #(
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
bram_agc_header u_bram_agc_header (
|
||||
.clka (clk), // input wire clka
|
||||
.addra(agc_addr), // input wire [13 : 0] addra
|
||||
.douta(agc_data) // output wire [1 : 0] douta
|
||||
);
|
||||
|
||||
bram_m_seqs_512 u_bram_m_seqs_512 (
|
||||
.clka (clk),
|
||||
.addra(mseqs_addr),
|
||||
@@ -465,7 +489,7 @@ module Transmitter #(
|
||||
|
||||
bram_chu_seq u_bram_chu_seq (
|
||||
.clka (clk), // input wire clka
|
||||
.addra(chu_seq_addr), // input wire [6 : 0] addra
|
||||
.addra(chu_seq_addr), // input wire [7 : 0] addra
|
||||
.douta(chu_seq) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
@@ -497,55 +521,55 @@ module Transmitter #(
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp16)
|
||||
);
|
||||
|
||||
fir_shape_interp8 u_fir_shape_interp8_i (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_i),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_i_interp8)
|
||||
);
|
||||
// fir_shape_interp8 u_fir_shape_interp8_i (
|
||||
// .aclk (clk),
|
||||
// .s_axis_data_tvalid(fir_tvalid_in),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata (m_fir_tdata_i),
|
||||
// .m_axis_data_tvalid(),
|
||||
// .m_axis_data_tdata (bb_wave_out_i_interp8)
|
||||
// );
|
||||
|
||||
fir_shape_interp8 u_fir_shape_interp8_q (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_q),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp8)
|
||||
);
|
||||
// fir_shape_interp8 u_fir_shape_interp8_q (
|
||||
// .aclk (clk),
|
||||
// .s_axis_data_tvalid(fir_tvalid_in),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata (m_fir_tdata_q),
|
||||
// .m_axis_data_tvalid(),
|
||||
// .m_axis_data_tdata (bb_wave_out_q_interp8)
|
||||
// );
|
||||
|
||||
fir_shape_interp4 u_fir_shape_interp4_i (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_i),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_i_interp4)
|
||||
);
|
||||
// fir_shape_interp4 u_fir_shape_interp4_i (
|
||||
// .aclk (clk),
|
||||
// .s_axis_data_tvalid(fir_tvalid_in),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata (m_fir_tdata_i),
|
||||
// .m_axis_data_tvalid(),
|
||||
// .m_axis_data_tdata (bb_wave_out_i_interp4)
|
||||
// );
|
||||
|
||||
fir_shape_interp4 u_fir_shape_interp4_q (
|
||||
.aclk (clk),
|
||||
.s_axis_data_tvalid(fir_tvalid_in),
|
||||
.s_axis_data_tready(),
|
||||
.s_axis_data_tdata (m_fir_tdata_q),
|
||||
.m_axis_data_tvalid(),
|
||||
.m_axis_data_tdata (bb_wave_out_q_interp4)
|
||||
);
|
||||
// fir_shape_interp4 u_fir_shape_interp4_q (
|
||||
// .aclk (clk),
|
||||
// .s_axis_data_tvalid(fir_tvalid_in),
|
||||
// .s_axis_data_tready(),
|
||||
// .s_axis_data_tdata (m_fir_tdata_q),
|
||||
// .m_axis_data_tvalid(),
|
||||
// .m_axis_data_tdata (bb_wave_out_q_interp4)
|
||||
// );
|
||||
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
ila_transmitter u_ila_transmitter (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(cnt_sym_send), // input wire [15:0] probe0
|
||||
.probe1(cs), // input wire [3:0] probe1
|
||||
.probe2(ns), // input wire [3:0] probe2
|
||||
.probe3(send_data_ready), // input wire [0:0] probe3
|
||||
.probe4(send_start), // input wire [0:0] probe4
|
||||
.probe5(tx_data_src_tvalid) // input wire [0:0] probe5
|
||||
);
|
||||
// ila_transmitter u_ila_transmitter (
|
||||
// .clk (clk), // input wire clk
|
||||
// .probe0(cnt_sym_send), // input wire [15:0] probe0
|
||||
// .probe1(cs), // input wire [3:0] probe1
|
||||
// .probe2(ns), // input wire [3:0] probe2
|
||||
// .probe3(send_data_ready), // input wire [0:0] probe3
|
||||
// .probe4(send_start), // input wire [0:0] probe4
|
||||
// .probe5(tx_data_src_tvalid) // input wire [0:0] probe5
|
||||
// );
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,78 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_1din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_1din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [0:0] dout02_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
|
||||
reg [8:0] sum=9'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
reg [0:0] result_reg4=1'd0;
|
||||
|
||||
reg [8:0] din01_CN_CU_9bit=9'd0;
|
||||
reg [8:0] din02_CHNL_CU_9bit=9'd0;
|
||||
|
||||
reg [7:0] din02_CHNL_CU_reg0=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg1=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg2=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg3=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg4=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg5=8'd0;
|
||||
reg [7:0] din02_CHNL_CU_reg6=8'd0;
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为9bit
|
||||
din01_CN_CU_9bit <= {din01_CN_CU[7],din01_CN_CU[7:0]};
|
||||
din02_CHNL_CU_9bit <= {din02_CHNL_CU[7],din02_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum <= din01_CN_CU_9bit + din02_CHNL_CU_9bit;
|
||||
result_reg0 <= {sum[8]};
|
||||
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
result_reg4 <= result_reg3;
|
||||
dout02_result_CU <= result_reg4;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin
|
||||
din02_CHNL_CU_reg0 <= din02_CHNL_CU;
|
||||
din02_CHNL_CU_reg1 <= din02_CHNL_CU_reg0;
|
||||
din02_CHNL_CU_reg2 <= din02_CHNL_CU_reg1;
|
||||
din02_CHNL_CU_reg3 <= din02_CHNL_CU_reg2;
|
||||
din02_CHNL_CU_reg4 <= din02_CHNL_CU_reg3;
|
||||
din02_CHNL_CU_reg5 <= din02_CHNL_CU_reg4;
|
||||
din02_CHNL_CU_reg6 <= din02_CHNL_CU_reg5;
|
||||
dout01_CU <= din02_CHNL_CU_reg6;
|
||||
end
|
||||
endmodule
|
||||
|
||||
+143
@@ -0,0 +1,143 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_2din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_2din(//注意：所有的输入数据同时进来本模块，即数据clk是对齐的
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din03_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0, //校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0, //校验节点更新输出
|
||||
output reg [0:0] dout03_result_CU=1'd0 //判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
reg [9:0] din01_CN_CU_10bit=10'd0,din01_CN_CU_10bit_reg0=10'd0,din01_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit=10'd0,din02_CN_CU_10bit_reg0=10'd0,din02_CN_CU_10bit_reg1=10'd0;
|
||||
|
||||
|
||||
reg [9:0] din03_CHNL_CU_10bit=10'd0;
|
||||
reg [9:0] din03_CHNL_CU_10bit_reg0=10'd0;
|
||||
|
||||
reg [9:0] sum1=10'd0;
|
||||
reg [9:0] sum=10'd0;
|
||||
|
||||
reg [9:0] minus1=10'd0;
|
||||
reg [9:0] minus2=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg0=10'd0;
|
||||
reg [9:0] minus2_reg0=10'd0;
|
||||
|
||||
|
||||
reg [9:0] minus1_reg1=10'd0;
|
||||
reg [9:0] minus2_reg1=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg2=10'd0;
|
||||
reg [9:0] minus2_reg2=10'd0;
|
||||
|
||||
reg [9:0] minus1_abs=10'd0;
|
||||
reg [9:0] minus2_abs=10'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为10bit
|
||||
din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CHNL_CU_10bit <= {{2{din03_CHNL_CU[7]}},din03_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
|
||||
din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
|
||||
|
||||
din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
|
||||
din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
|
||||
|
||||
din03_CHNL_CU_10bit_reg0 <= din03_CHNL_CU_10bit;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
|
||||
minus1_reg2 <= minus1_reg1;
|
||||
minus2_reg2 <= minus2_reg1;
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk) begin //结果更新过程
|
||||
sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
|
||||
sum <= sum1 + din03_CHNL_CU_10bit_reg0;
|
||||
|
||||
result_reg0 <= {sum[9]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
dout03_result_CU <= result_reg3;
|
||||
|
||||
minus1 <= sum - din01_CN_CU_10bit_reg1;
|
||||
minus2 <= sum - din02_CN_CU_10bit_reg1;
|
||||
|
||||
if(minus1_reg1[9])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg1 + 10'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg1;
|
||||
if(minus1_reg2[9]) begin//限幅操作
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end else begin
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end
|
||||
|
||||
if(minus2_reg1[9])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg1 + 10'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg1;
|
||||
if(minus2_reg2[9]) begin//限幅操作
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end else begin
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+179
@@ -0,0 +1,179 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_3din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_3din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
input [7:0] din03_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din04_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
|
||||
|
||||
output reg [0:0] dout04_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期(8)
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit=10'd0;
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit_reg0=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit_reg0=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit_reg0=10'd0;
|
||||
|
||||
reg [9:0] din01_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din02_CN_CU_10bit_reg1=10'd0;
|
||||
reg [9:0] din03_CN_CU_10bit_reg1=10'd0;
|
||||
|
||||
reg [9:0] din04_CHNL_CU_10bit=10'd0;
|
||||
|
||||
reg [9:0] sum1=10'd0;
|
||||
reg [9:0] sum2=10'd0;
|
||||
reg [9:0] sum=10'd0;
|
||||
|
||||
reg [9:0] minus1=10'd0;
|
||||
reg [9:0] minus2=10'd0;
|
||||
reg [9:0] minus3=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg0=10'd0;
|
||||
reg [9:0] minus2_reg0=10'd0;
|
||||
reg [9:0] minus3_reg0=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg1=10'd0;
|
||||
reg [9:0] minus2_reg1=10'd0;
|
||||
reg [9:0] minus3_reg1=10'd0;
|
||||
|
||||
reg [9:0] minus1_reg2=10'd0;
|
||||
reg [9:0] minus2_reg2=10'd0;
|
||||
reg [9:0] minus3_reg2=10'd0;
|
||||
|
||||
reg [9:0] minus1_abs=10'd0;
|
||||
reg [9:0] minus2_abs=10'd0;
|
||||
reg [9:0] minus3_abs=10'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
reg [0:0] result_reg3=1'd0;
|
||||
always @ (posedge clk) begin//先把输入转换为10bit
|
||||
din01_CN_CU_10bit <= {{2{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_10bit <= {{2{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CN_CU_10bit <= {{2{din03_CN_CU[7]}},din03_CN_CU[7:0]};
|
||||
din04_CHNL_CU_10bit <= {{2{din04_CHNL_CU[7]}},din04_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_10bit_reg0 <= din01_CN_CU_10bit;
|
||||
din02_CN_CU_10bit_reg0 <= din02_CN_CU_10bit;
|
||||
din03_CN_CU_10bit_reg0 <= din03_CN_CU_10bit;
|
||||
|
||||
din01_CN_CU_10bit_reg1 <= din01_CN_CU_10bit_reg0;
|
||||
din02_CN_CU_10bit_reg1 <= din02_CN_CU_10bit_reg0;
|
||||
din03_CN_CU_10bit_reg1 <= din03_CN_CU_10bit_reg0;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
minus3_reg0 <= minus3;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
minus3_reg1 <= minus3_reg0;
|
||||
|
||||
minus1_reg2 <= minus1_reg1;
|
||||
minus2_reg2 <= minus2_reg1;
|
||||
minus3_reg2 <= minus3_reg1;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum1 <= din01_CN_CU_10bit + din02_CN_CU_10bit;
|
||||
sum2 <= din03_CN_CU_10bit + din04_CHNL_CU_10bit;
|
||||
sum <= sum1 + sum2;
|
||||
|
||||
result_reg0 <= {sum[9]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
result_reg3 <= result_reg2;
|
||||
dout04_result_CU <= result_reg3;
|
||||
minus1 <= sum - din01_CN_CU_10bit_reg1;
|
||||
minus2 <= sum - din02_CN_CU_10bit_reg1;
|
||||
minus3 <= sum - din03_CN_CU_10bit_reg1;
|
||||
|
||||
if(minus1_reg1[9])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg1 + 10'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg1;
|
||||
if(minus1_reg2[9]) begin//限幅操作
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end else begin
|
||||
if(minus1_abs>10'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg2[9],minus1_reg2[6:0]};
|
||||
// dout01_CU <= minus1_reg2;
|
||||
end
|
||||
|
||||
if(minus2_reg1[9])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg1 + 10'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg1;
|
||||
if(minus2_reg2[9]) begin//限幅操作
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end else begin
|
||||
if(minus2_abs>10'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg2[9],minus2_reg2[6:0]};
|
||||
// dout02_CU <= minus2_reg2;
|
||||
end
|
||||
|
||||
if(minus3_reg1[9])//限幅前求绝对值操作
|
||||
minus3_abs <= ~minus3_reg1 + 10'd1;
|
||||
else
|
||||
minus3_abs <= minus3_reg1;
|
||||
if(minus3_reg2[9]) begin//限幅操作
|
||||
if(minus3_abs>10'd127)
|
||||
dout03_CU <= -8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
|
||||
// dout03_CU <= minus3_reg2;
|
||||
end else begin
|
||||
if(minus3_abs>10'd127)
|
||||
dout03_CU <= 8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg2[9],minus3_reg2[6:0]};
|
||||
// dout03_CU <= minus3_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
+292
@@ -0,0 +1,292 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VNU_6din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VNU_6din(
|
||||
input clk,
|
||||
input [7:0] din01_CN_CU, //校验节点信息输入
|
||||
input [7:0] din02_CN_CU, //校验节点信息输入
|
||||
input [7:0] din03_CN_CU, //校验节点信息输入
|
||||
input [7:0] din04_CN_CU, //校验节点信息输入
|
||||
input [7:0] din05_CN_CU, //校验节点信息输入
|
||||
input [7:0] din06_CN_CU, //校验节点信息输入
|
||||
|
||||
input [7:0] din07_CHNL_CU, //信道信息输入
|
||||
|
||||
output reg [7:0] dout01_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout02_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout03_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout04_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout05_CU=8'd0,//校验节点更新输出
|
||||
output reg [7:0] dout06_CU=8'd0,//校验节点更新输出
|
||||
|
||||
output reg [0:0] dout07_result_CU=1'd0//判决结果输出
|
||||
);//输出相对输入延时8个周期
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg0=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg0=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg1=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg1=11'd0;
|
||||
|
||||
reg [10:0] din01_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din02_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din03_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din04_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din05_CN_CU_11bit_reg2=11'd0;
|
||||
reg [10:0] din06_CN_CU_11bit_reg2=11'd0;
|
||||
|
||||
reg [10:0] din07_CHNL_CU_11bit=11'd0;
|
||||
reg [10:0] din07_CHNL_CU_11bit_reg0=11'd0;
|
||||
|
||||
|
||||
reg [10:0] sum1=11'd0;
|
||||
reg [10:0] sum2=11'd0;
|
||||
reg [10:0] sum3=11'd0;
|
||||
reg [10:0] sum4=11'd0;
|
||||
reg [10:0] sum5=11'd0;
|
||||
reg [10:0] sum=11'd0;
|
||||
|
||||
reg [10:0] minus1=11'd0;
|
||||
reg [10:0] minus2=11'd0;
|
||||
reg [10:0] minus3=11'd0;
|
||||
reg [10:0] minus4=11'd0;
|
||||
reg [10:0] minus5=11'd0;
|
||||
reg [10:0] minus6=11'd0;
|
||||
|
||||
reg [10:0] minus1_reg0=11'd0;
|
||||
reg [10:0] minus2_reg0=11'd0;
|
||||
reg [10:0] minus3_reg0=11'd0;
|
||||
reg [10:0] minus4_reg0=11'd0;
|
||||
reg [10:0] minus5_reg0=11'd0;
|
||||
reg [10:0] minus6_reg0=11'd0;
|
||||
|
||||
reg [10:0] minus1_reg1=11'd0;
|
||||
reg [10:0] minus2_reg1=11'd0;
|
||||
reg [10:0] minus3_reg1=11'd0;
|
||||
reg [10:0] minus4_reg1=11'd0;
|
||||
reg [10:0] minus5_reg1=11'd0;
|
||||
reg [10:0] minus6_reg1=11'd0;
|
||||
|
||||
reg [10:0] minus1_abs=11'd0;
|
||||
reg [10:0] minus2_abs=11'd0;
|
||||
reg [10:0] minus3_abs=11'd0;
|
||||
reg [10:0] minus4_abs=11'd0;
|
||||
reg [10:0] minus5_abs=11'd0;
|
||||
reg [10:0] minus6_abs=11'd0;
|
||||
|
||||
reg [0:0] result_reg0=1'd0;
|
||||
reg [0:0] result_reg1=1'd0;
|
||||
reg [0:0] result_reg2=1'd0;
|
||||
|
||||
|
||||
always @ (posedge clk) begin//先把输入转换为11bit
|
||||
din01_CN_CU_11bit <= {{3{din01_CN_CU[7]}},din01_CN_CU[7:0]};
|
||||
din02_CN_CU_11bit <= {{3{din02_CN_CU[7]}},din02_CN_CU[7:0]};
|
||||
din03_CN_CU_11bit <= {{3{din03_CN_CU[7]}},din03_CN_CU[7:0]};
|
||||
din04_CN_CU_11bit <= {{3{din04_CN_CU[7]}},din04_CN_CU[7:0]};
|
||||
din05_CN_CU_11bit <= {{3{din05_CN_CU[7]}},din05_CN_CU[7:0]};
|
||||
din06_CN_CU_11bit <= {{3{din06_CN_CU[7]}},din06_CN_CU[7:0]};
|
||||
din07_CHNL_CU_11bit <= {{3{din07_CHNL_CU[7]}},din07_CHNL_CU[7:0]};
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//流水延时过程
|
||||
din01_CN_CU_11bit_reg0 <= din01_CN_CU_11bit;
|
||||
din02_CN_CU_11bit_reg0 <= din02_CN_CU_11bit;
|
||||
din03_CN_CU_11bit_reg0 <= din03_CN_CU_11bit;
|
||||
din04_CN_CU_11bit_reg0 <= din04_CN_CU_11bit;
|
||||
din05_CN_CU_11bit_reg0 <= din05_CN_CU_11bit;
|
||||
din06_CN_CU_11bit_reg0 <= din06_CN_CU_11bit;
|
||||
din07_CHNL_CU_11bit_reg0 <= din07_CHNL_CU_11bit;
|
||||
|
||||
din01_CN_CU_11bit_reg1 <= din01_CN_CU_11bit_reg0;
|
||||
din02_CN_CU_11bit_reg1 <= din02_CN_CU_11bit_reg0;
|
||||
din03_CN_CU_11bit_reg1 <= din03_CN_CU_11bit_reg0;
|
||||
din04_CN_CU_11bit_reg1 <= din04_CN_CU_11bit_reg0;
|
||||
din05_CN_CU_11bit_reg1 <= din05_CN_CU_11bit_reg0;
|
||||
din06_CN_CU_11bit_reg1 <= din06_CN_CU_11bit_reg0;
|
||||
|
||||
din01_CN_CU_11bit_reg2 <= din01_CN_CU_11bit_reg1;
|
||||
din02_CN_CU_11bit_reg2 <= din02_CN_CU_11bit_reg1;
|
||||
din03_CN_CU_11bit_reg2 <= din03_CN_CU_11bit_reg1;
|
||||
din04_CN_CU_11bit_reg2 <= din04_CN_CU_11bit_reg1;
|
||||
din05_CN_CU_11bit_reg2 <= din05_CN_CU_11bit_reg1;
|
||||
din06_CN_CU_11bit_reg2 <= din06_CN_CU_11bit_reg1;
|
||||
|
||||
minus1_reg0 <= minus1;
|
||||
minus2_reg0 <= minus2;
|
||||
minus3_reg0 <= minus3;
|
||||
minus4_reg0 <= minus4;
|
||||
minus5_reg0 <= minus5;
|
||||
minus6_reg0 <= minus6;
|
||||
|
||||
minus1_reg1 <= minus1_reg0;
|
||||
minus2_reg1 <= minus2_reg0;
|
||||
minus3_reg1 <= minus3_reg0;
|
||||
minus4_reg1 <= minus4_reg0;
|
||||
minus5_reg1 <= minus5_reg0;
|
||||
minus6_reg1 <= minus6_reg0;
|
||||
end
|
||||
|
||||
always @ (posedge clk) begin//结果更新过程
|
||||
sum1 <= din01_CN_CU_11bit + din02_CN_CU_11bit;
|
||||
sum2 <= din03_CN_CU_11bit + din04_CN_CU_11bit;
|
||||
sum3 <= din05_CN_CU_11bit + din06_CN_CU_11bit;
|
||||
sum4 <= sum1 + sum2;
|
||||
sum5 <= sum3 + din07_CHNL_CU_11bit_reg0;
|
||||
sum <= sum4 + sum5;
|
||||
|
||||
result_reg0 <= {sum[10]};
|
||||
result_reg1 <= result_reg0;
|
||||
result_reg2 <= result_reg1;
|
||||
dout07_result_CU <= result_reg2;
|
||||
minus1 <= sum - din01_CN_CU_11bit_reg2;
|
||||
minus2 <= sum - din02_CN_CU_11bit_reg2;
|
||||
minus3 <= sum - din03_CN_CU_11bit_reg2;
|
||||
minus4 <= sum - din04_CN_CU_11bit_reg2;
|
||||
minus5 <= sum - din05_CN_CU_11bit_reg2;
|
||||
minus6 <= sum - din06_CN_CU_11bit_reg2;
|
||||
|
||||
if(minus1_reg0[10])//限幅前求绝对值操作
|
||||
minus1_abs <= ~minus1_reg0 + 11'd1;
|
||||
else
|
||||
minus1_abs <= minus1_reg0;
|
||||
if(minus1_reg1[10]) begin//限幅操作
|
||||
if(minus1_abs>11'd127)
|
||||
dout01_CU <= -8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
|
||||
// dout01_CU <= minus1_reg1;
|
||||
end else begin
|
||||
if(minus1_abs>11'd127)
|
||||
dout01_CU <= 8'd127;
|
||||
else
|
||||
dout01_CU <= {minus1_reg1[10],minus1_reg1[6:0]};
|
||||
// dout01_CU <= minus1_reg1;
|
||||
end
|
||||
|
||||
if(minus2_reg0[10])//限幅前求绝对值操作
|
||||
minus2_abs <= ~minus2_reg0 + 11'd1;
|
||||
else
|
||||
minus2_abs <= minus2_reg0;
|
||||
if(minus2_reg1[10]) begin//限幅操作
|
||||
if(minus2_abs>11'd127)
|
||||
dout02_CU <= -8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
|
||||
// dout02_CU <= minus2_reg1;
|
||||
end else begin
|
||||
if(minus2_abs>11'd127)
|
||||
dout02_CU <= 8'd127;
|
||||
else
|
||||
dout02_CU <= {minus2_reg1[10],minus2_reg1[6:0]};
|
||||
// dout02_CU <= minus2_reg1;
|
||||
end
|
||||
|
||||
if(minus3_reg0[10])//限幅前求绝对值操作
|
||||
minus3_abs <= ~minus3_reg0 + 11'd1;
|
||||
else
|
||||
minus3_abs <= minus3_reg0;
|
||||
if(minus3_reg1[10]) begin//限幅操作
|
||||
if(minus3_abs>11'd127)
|
||||
dout03_CU <= -8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
|
||||
// dout03_CU <= minus3_reg1;
|
||||
end else begin
|
||||
if(minus3_abs>11'd127)
|
||||
dout03_CU <= 8'd127;
|
||||
else
|
||||
dout03_CU <= {minus3_reg1[10],minus3_reg1[6:0]};
|
||||
// dout03_CU <= minus3_reg1;
|
||||
end
|
||||
|
||||
if(minus4_reg0[10])//限幅前求绝对值操作
|
||||
minus4_abs <= ~minus4_reg0 + 11'd1;
|
||||
else
|
||||
minus4_abs <= minus4_reg0;
|
||||
if(minus4_reg1[10]) begin//限幅操作
|
||||
if(minus4_abs>11'd127)
|
||||
dout04_CU <= -8'd127;
|
||||
else
|
||||
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
|
||||
// dout04_CU <= minus4_reg1;
|
||||
end else begin
|
||||
if(minus4_abs>11'd127)
|
||||
dout04_CU <= 8'd127;
|
||||
else
|
||||
dout04_CU <= {minus4_reg1[10],minus4_reg1[6:0]};
|
||||
// dout04_CU <= minus4_reg1;
|
||||
end
|
||||
|
||||
if(minus5_reg0[10])//限幅前求绝对值操作
|
||||
minus5_abs <= ~minus5_reg0 + 11'd1;
|
||||
else
|
||||
minus5_abs <= minus5_reg0;
|
||||
if(minus5_reg1[10]) begin//限幅操作
|
||||
if(minus5_abs>11'd127)
|
||||
dout05_CU <= -8'd127;
|
||||
else
|
||||
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
|
||||
// dout05_CU <= minus5_reg1;
|
||||
end else begin
|
||||
if(minus5_abs>11'd127)
|
||||
dout05_CU <= 8'd127;
|
||||
else
|
||||
dout05_CU <= {minus5_reg1[10],minus5_reg1[6:0]};
|
||||
// dout05_CU <= minus5_reg1;
|
||||
end
|
||||
|
||||
if(minus6_reg0[10])//限幅前求绝对值操作
|
||||
minus6_abs <= ~minus6_reg0 + 11'd1;
|
||||
else
|
||||
minus6_abs <= minus6_reg0;
|
||||
if(minus6_reg1[10]) begin//限幅操作
|
||||
if(minus6_abs>11'd127)
|
||||
dout06_CU <= -8'd127;
|
||||
else
|
||||
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
|
||||
// dout06_CU <= minus6_reg1;
|
||||
end else begin
|
||||
if(minus6_abs>11'd127)
|
||||
dout06_CU <= 8'd127;
|
||||
else
|
||||
dout06_CU <= {minus6_reg1[10],minus6_reg1[6:0]};
|
||||
// dout06_CU <= minus6_reg1;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
+937
@@ -0,0 +1,937 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/11/18 23:18:07
|
||||
// Design Name:
|
||||
// Module Name: VN_PRO
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module VN_PRO
|
||||
#(
|
||||
parameter MAX_ITER_NUM = 6'd14, //最大迭代次数
|
||||
parameter WIDTH = 4'd8
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rst_VN,
|
||||
input start_VN, // VN更新启动脉冲
|
||||
input start_frame_VN, // VN更新启动脉冲(新的1帧的开始)
|
||||
|
||||
input [WIDTH-1:0] CHNL_dout_01,//信道信息输入
|
||||
input [WIDTH-1:0] CHNL_dout_02,
|
||||
input [WIDTH-1:0] CHNL_dout_03,
|
||||
input [WIDTH-1:0] CHNL_dout_04,
|
||||
|
||||
//校验节点信息输入，H阵第１行
|
||||
input [WIDTH-1:0] CN1_dout_01_00,
|
||||
input [WIDTH-1:0] CN1_dout_02_00, //后面的00代表H阵原模图的IM
|
||||
input [WIDTH-1:0] CN1_dout_02_01, //后面的01代表H阵原模图的II1
|
||||
|
||||
|
||||
input [WIDTH-1:0] CN2_dout_01_00,
|
||||
input [WIDTH-1:0] CN2_dout_02_00,
|
||||
input [WIDTH-1:0] CN2_dout_03_00,
|
||||
input [WIDTH-1:0] CN2_dout_04_02, //后面的02代表H阵原模图的II2
|
||||
input [WIDTH-1:0] CN2_dout_04_03, //后面的03代表H阵原模图的II3
|
||||
input [WIDTH-1:0] CN2_dout_04_04, //后面的04代表H阵原模图的II4
|
||||
//校验节点信息输入，H阵第３行
|
||||
input [WIDTH-1:0] CN3_dout_01_00,
|
||||
input [WIDTH-1:0] CN3_dout_02_05, //后面的05代表H阵原模图的II5
|
||||
input [WIDTH-1:0] CN3_dout_02_06, //后面的06代表H阵原模图的II6
|
||||
input [WIDTH-1:0] CN3_dout_03_07, //后面的07代表H阵原模图的II7
|
||||
input [WIDTH-1:0] CN3_dout_03_08, //后面的08代表H阵原模图的II8
|
||||
input [WIDTH-1:0] CN3_dout_04_00,
|
||||
|
||||
|
||||
output ask_din, //向数据缓存区请求信道数据
|
||||
|
||||
//校验节点信息读地址，H阵第１行
|
||||
output reg [8:0] CN1_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] CN1_addr_rd_02_00=10'd1023,
|
||||
output reg [9:0] CN1_addr_rd_02_01=10'd511,
|
||||
|
||||
//校验节点信息读地址，H阵第２行
|
||||
output reg [8:0] CN2_addr_rd_01_00=9'd511,
|
||||
output reg [8:0] CN2_addr_rd_02_00=9'd511,
|
||||
output reg [8:0] CN2_addr_rd_03_00=9'd511,
|
||||
output reg [9:0] CN2_addr_rd_04_02=10'd1023,
|
||||
output reg [9:0] CN2_addr_rd_04_03=10'd511,
|
||||
output reg [8:0] CN2_addr_rd_04_04=9'd511,
|
||||
|
||||
//校验节点信息读地址，H阵第３行
|
||||
output reg [8:0] CN3_addr_rd_01_00=9'd511,
|
||||
output reg [9:0] CN3_addr_rd_02_05=10'd1023,
|
||||
output reg [9:0] CN3_addr_rd_02_06=10'd511,
|
||||
output reg [9:0] CN3_addr_rd_03_07=10'd1023,
|
||||
output reg [9:0] CN3_addr_rd_03_08=10'd511,
|
||||
output reg [8:0] CN3_addr_rd_04_00=9'd511,
|
||||
|
||||
//变量节点写使能
|
||||
output reg [0:0] VN_wea=1'd0,
|
||||
|
||||
//变量节点写地址，H阵第１行
|
||||
output reg [8:0] VN1_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] VN1_addr_wr_02_00=10'd1023,
|
||||
output reg [9:0] VN1_addr_wr_02_01=10'd511,
|
||||
|
||||
//变量节点写地址，H阵第２行
|
||||
output reg [8:0] VN2_addr_wr_01_00=9'd511,
|
||||
output reg [8:0] VN2_addr_wr_02_00=9'd511,
|
||||
output reg [8:0] VN2_addr_wr_03_00=9'd511,
|
||||
output reg [9:0] VN2_addr_wr_04_02=10'd1023,
|
||||
output reg [9:0] VN2_addr_wr_04_03=10'd511,
|
||||
output reg [8:0] VN2_addr_wr_04_04=9'd511,
|
||||
|
||||
//变量节点写地址，H阵第３行
|
||||
output reg [8:0] VN3_addr_wr_01_00=9'd511,
|
||||
output reg [9:0] VN3_addr_wr_02_05=10'd1023,
|
||||
output reg [9:0] VN3_addr_wr_02_06=10'd511,
|
||||
output reg [9:0] VN3_addr_wr_03_07=10'd1023,
|
||||
output reg [9:0] VN3_addr_wr_03_08=10'd511,
|
||||
output reg [8:0] VN3_addr_wr_04_00=9'd511,
|
||||
|
||||
|
||||
//变量节点写数据，H阵第１行
|
||||
output reg [WIDTH-1:0] VN1_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN1_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN1_din_02_01=8'd0,
|
||||
|
||||
//变量节点写数据，H阵第２行
|
||||
output reg [WIDTH-1:0] VN2_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_02_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_03_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_02=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_03=8'd0,
|
||||
output reg [WIDTH-1:0] VN2_din_04_04=8'd0,
|
||||
|
||||
//变量节点写数据，H阵第３行
|
||||
output reg [WIDTH-1:0] VN3_din_01_00=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_02_05=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_02_06=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_03_07=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_03_08=8'd0,
|
||||
output reg [WIDTH-1:0] VN3_din_04_00=8'd0,
|
||||
|
||||
//判决结果写使能
|
||||
output reg [0:0] DR_wea=8'd0,
|
||||
|
||||
//判决结果写地址
|
||||
output reg [8:0] DR_addr_wr=9'd511,
|
||||
|
||||
output reg [0:0] DR_din_01=1'd0, //判决结果写数据
|
||||
output reg [0:0] DR_din_02=1'd0,
|
||||
output reg [0:0] DR_din_03=1'd0,
|
||||
output reg [0:0] DR_din_04=1'd0,
|
||||
output reg [0:0] DR_din_05=1'd0,
|
||||
|
||||
|
||||
output data_start_ck_VN, //产生判决结果数据开始存储标志，高脉冲
|
||||
output data_start_VN, //产生判决结果数据可以输出标志，高脉冲
|
||||
output end_VN //模块结束标志，高脉冲
|
||||
);
|
||||
|
||||
assign ask_din = (rst_VN) ? 1'd0 : ((start_VN) ? 1'd1:1'd0);
|
||||
|
||||
reg [5:0] iter_num = 6'd0;
|
||||
// 迭代次数控制
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN || start_frame_VN) begin
|
||||
iter_num <= 6'd0;
|
||||
end else begin
|
||||
if(end_VN)
|
||||
if (iter_num < MAX_ITER_NUM)
|
||||
iter_num <= iter_num + 6'd1;
|
||||
else
|
||||
iter_num <= iter_num;
|
||||
else
|
||||
iter_num <= iter_num;
|
||||
end
|
||||
end
|
||||
|
||||
reg [10:0] cnt_VN= 11'd0,cnt_2_VN= 11'd0;
|
||||
reg flag_VN=1'd0;
|
||||
// 产生该模块的计数基准
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
cnt_VN <= 11'd0;
|
||||
cnt_2_VN <= 11'd0;
|
||||
flag_VN <= 1'b0;
|
||||
end else begin
|
||||
if(start_VN) begin
|
||||
flag_VN <= 1'b1;
|
||||
cnt_VN <= 11'd0;
|
||||
cnt_2_VN <= 11'd0;
|
||||
end else begin
|
||||
if(flag_VN) begin
|
||||
if(cnt_VN<11'd560)begin
|
||||
flag_VN <= flag_VN;
|
||||
cnt_VN <= cnt_VN + 11'd1;
|
||||
end else begin
|
||||
cnt_VN <= cnt_VN;
|
||||
flag_VN<= 1'b0;
|
||||
end
|
||||
if(cnt_2_VN<11'd560)begin
|
||||
flag_VN <= flag_VN;
|
||||
cnt_2_VN <= cnt_2_VN + 11'd1;
|
||||
end else begin
|
||||
cnt_2_VN <= cnt_2_VN;
|
||||
flag_VN<= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
cnt_VN <= cnt_VN;
|
||||
cnt_2_VN <= cnt_2_VN;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
parameter DELAY_RD = 11'd3;
|
||||
|
||||
// 对所有IM进行CN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
CN1_addr_rd_01_00 <= 9'd511;
|
||||
CN1_addr_rd_02_00 <= 10'd1023;
|
||||
CN2_addr_rd_01_00 <= 9'd511;
|
||||
CN2_addr_rd_02_00 <= 9'd511;
|
||||
CN2_addr_rd_03_00 <= 9'd511;
|
||||
CN3_addr_rd_01_00 <= 9'd511;
|
||||
CN3_addr_rd_04_00 <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin
|
||||
CN1_addr_rd_01_00 <= CN1_addr_rd_01_00 + 9'd1;
|
||||
CN1_addr_rd_02_00 <= CN1_addr_rd_02_00 + 10'd1;
|
||||
CN2_addr_rd_01_00 <= CN2_addr_rd_01_00 + 9'd1;
|
||||
CN2_addr_rd_02_00 <= CN2_addr_rd_02_00 + 9'd1;
|
||||
CN2_addr_rd_03_00 <= CN2_addr_rd_03_00 + 9'd1;
|
||||
CN3_addr_rd_01_00 <= CN3_addr_rd_01_00 + 9'd1;
|
||||
CN3_addr_rd_04_00 <= CN3_addr_rd_04_00 + 9'd1;
|
||||
end else begin
|
||||
CN1_addr_rd_01_00 <= 9'd511;
|
||||
CN1_addr_rd_02_00 <= 10'd1023;
|
||||
CN2_addr_rd_01_00 <= 9'd511;
|
||||
CN2_addr_rd_02_00 <= 9'd511;
|
||||
CN2_addr_rd_03_00 <= 9'd511;
|
||||
CN3_addr_rd_01_00 <= 9'd511;
|
||||
CN3_addr_rd_04_00 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg first_flag_cn_01=1'd1,first_flag_cn_02=1'd1,first_flag_cn_03=1'd1,first_flag_cn_04=1'd1;
|
||||
reg first_flag_cn_05=1'd1,first_flag_cn_06=1'd1,first_flag_cn_07=1'd1,first_flag_cn_08=1'd1;
|
||||
reg first_flag_vn_01=1'd1,first_flag_vn_02=1'd1,first_flag_vn_03=1'd1,first_flag_vn_04=1'd1;
|
||||
reg first_flag_vn_05=1'd1,first_flag_vn_06=1'd1,first_flag_vn_07=1'd1,first_flag_vn_08=1'd1;
|
||||
|
||||
// 对II1-II8进行CN地址操作
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
CN1_addr_rd_02_01 <= 10'd639;
|
||||
CN2_addr_rd_04_02 <= 10'd24;
|
||||
CN2_addr_rd_04_03 <= 10'd926;
|
||||
CN2_addr_rd_04_04 <= 9'd294;
|
||||
CN3_addr_rd_02_05 <= 10'd352;
|
||||
CN3_addr_rd_02_06 <= 10'd639;
|
||||
CN3_addr_rd_03_07 <= 10'd12;
|
||||
CN3_addr_rd_03_08 <= 10'd929;
|
||||
first_flag_cn_01 <= 1'd1;
|
||||
first_flag_cn_02 <= 1'd1;
|
||||
first_flag_cn_03 <= 1'd1;
|
||||
first_flag_cn_04 <= 1'd1;
|
||||
first_flag_cn_05 <= 1'd1;
|
||||
first_flag_cn_06 <= 1'd1;
|
||||
first_flag_cn_07 <= 1'd1;
|
||||
first_flag_cn_08 <= 1'd1;
|
||||
end else begin
|
||||
if (cnt_VN >= 11'd1 + DELAY_RD && cnt_VN <= 11'd512 + DELAY_RD) begin
|
||||
//对II1地址进行操作，确保初始化地址先加1
|
||||
if (first_flag_cn_05) begin
|
||||
CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1;
|
||||
first_flag_cn_05 <= 1'd0;
|
||||
end else begin
|
||||
if (CN1_addr_rd_02_01 == 10'd1023)
|
||||
CN1_addr_rd_02_01 <= 10'd624;
|
||||
else if (CN1_addr_rd_02_01 == 10'd639)
|
||||
CN1_addr_rd_02_01 <= 10'd512;
|
||||
else
|
||||
CN1_addr_rd_02_01 <= CN1_addr_rd_02_01 + 10'd1;
|
||||
end
|
||||
// 对II2地址进行操作
|
||||
if (first_flag_cn_06) begin
|
||||
CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1;
|
||||
first_flag_cn_06<= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_02 == 10'd127)
|
||||
CN2_addr_rd_04_02 <= 10'd0;
|
||||
else if (CN2_addr_rd_04_02 == 10'd24)
|
||||
CN2_addr_rd_04_02 <= 10'd203;
|
||||
else if (CN2_addr_rd_04_02 == 10'd255)
|
||||
CN2_addr_rd_04_02 <= 10'd128;
|
||||
else if (CN2_addr_rd_04_02 == 10'd202)
|
||||
CN2_addr_rd_04_02 <= 10'd376;
|
||||
else if (CN2_addr_rd_04_02 == 10'd383)
|
||||
CN2_addr_rd_04_02 <= 10'd256;
|
||||
else if (CN2_addr_rd_04_02 == 10'd375)
|
||||
CN2_addr_rd_04_02 <= 10'd477;
|
||||
else if (CN2_addr_rd_04_02 == 10'd511)
|
||||
CN2_addr_rd_04_02 <= 10'd384;
|
||||
else
|
||||
CN2_addr_rd_04_02 <= CN2_addr_rd_04_02 + 10'd1;
|
||||
end
|
||||
// 对II3地址进行操作
|
||||
if (first_flag_cn_07) begin
|
||||
CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1;
|
||||
first_flag_cn_07 <= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_03 == 10'd1023)
|
||||
CN2_addr_rd_04_03 <= 10'd896;
|
||||
else if (CN2_addr_rd_04_03 == 10'd926)
|
||||
CN2_addr_rd_04_03 <= 10'd535;
|
||||
else if (CN2_addr_rd_04_03 == 10'd639)
|
||||
CN2_addr_rd_04_03 <= 10'd512;
|
||||
else if (CN2_addr_rd_04_03 == 10'd534)
|
||||
CN2_addr_rd_04_03 <= 10'd694;
|
||||
else if (CN2_addr_rd_04_03 == 10'd767)
|
||||
CN2_addr_rd_04_03 <= 10'd640;
|
||||
else if (CN2_addr_rd_04_03 == 10'd693)
|
||||
CN2_addr_rd_04_03 <= 10'd777;
|
||||
else if (CN2_addr_rd_04_03 == 10'd895)
|
||||
CN2_addr_rd_04_03 <= 10'd768;
|
||||
else
|
||||
CN2_addr_rd_04_03 <= CN2_addr_rd_04_03 + 10'd1;
|
||||
end
|
||||
// 对II4地址进行操作
|
||||
if (first_flag_cn_08) begin
|
||||
CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1;
|
||||
first_flag_cn_08 <= 1'd0;
|
||||
end else begin
|
||||
if (CN2_addr_rd_04_04 == 9'd383)
|
||||
CN2_addr_rd_04_04 <= 9'd256;
|
||||
else if (CN2_addr_rd_04_04 == 9'd294)
|
||||
CN2_addr_rd_04_04 <= 9'd400;
|
||||
else if (CN2_addr_rd_04_04 == 9'd511)
|
||||
CN2_addr_rd_04_04 <= 9'd384;
|
||||
else if (CN2_addr_rd_04_04 == 9'd399)
|
||||
CN2_addr_rd_04_04 <= 9'd0;
|
||||
else if (CN2_addr_rd_04_04 == 9'd127)
|
||||
CN2_addr_rd_04_04 <= 9'd211;
|
||||
else if (CN2_addr_rd_04_04 == 9'd255)
|
||||
CN2_addr_rd_04_04 <= 9'd128;
|
||||
else
|
||||
CN2_addr_rd_04_04 <= CN2_addr_rd_04_04 + 9'd1;
|
||||
end
|
||||
// 对II5地址进行操作
|
||||
if (first_flag_cn_01) begin //确保初始化地址先加1
|
||||
CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1;
|
||||
first_flag_cn_01 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_02_05 == 10'd383)
|
||||
CN3_addr_rd_02_05 <= 10'd256;
|
||||
else if (CN3_addr_rd_02_05 == 10'd352)
|
||||
CN3_addr_rd_02_05 <= 10'd448;
|
||||
else if (CN3_addr_rd_02_05 == 10'd511)
|
||||
CN3_addr_rd_02_05 <= 10'd384;
|
||||
else if (CN3_addr_rd_02_05 == 10'd447)
|
||||
CN3_addr_rd_02_05 <= 10'd78;
|
||||
else if (CN3_addr_rd_02_05 == 10'd127)
|
||||
CN3_addr_rd_02_05 <= 10'd0;
|
||||
else if (CN3_addr_rd_02_05 == 10'd77)
|
||||
CN3_addr_rd_02_05 <= 10'd209;
|
||||
else if (CN3_addr_rd_02_05 == 10'd255)
|
||||
CN3_addr_rd_02_05 <= 10'd128;
|
||||
else
|
||||
CN3_addr_rd_02_05 <= CN3_addr_rd_02_05 + 10'd1;
|
||||
end
|
||||
// 对II6地址进行操作
|
||||
if (first_flag_cn_02) begin
|
||||
CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1;
|
||||
first_flag_cn_02 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_02_06 == 10'd767)
|
||||
CN3_addr_rd_02_06 <= 10'd774;
|
||||
else if (CN3_addr_rd_02_06 == 10'd895)
|
||||
CN3_addr_rd_02_06 <= 10'd768;
|
||||
else if (CN3_addr_rd_02_06 == 10'd773)
|
||||
CN3_addr_rd_02_06 <= 10'd931;
|
||||
else if (CN3_addr_rd_02_06 == 10'd1023)
|
||||
CN3_addr_rd_02_06 <= 10'd896;
|
||||
else if (CN3_addr_rd_02_06 == 10'd930)
|
||||
CN3_addr_rd_02_06 <= 10'd611;
|
||||
else if (CN3_addr_rd_02_06 == 10'd639)
|
||||
CN3_addr_rd_02_06 <= 10'd512;
|
||||
else
|
||||
CN3_addr_rd_02_06 <= CN3_addr_rd_02_06 + 10'd1;
|
||||
end
|
||||
// 对II7地址进行操作
|
||||
if (first_flag_cn_03) begin //确保初始化地址先加1
|
||||
CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1;
|
||||
first_flag_cn_03 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_03_07 == 10'd127)
|
||||
CN3_addr_rd_03_07 <= 10'd0;
|
||||
else if (CN3_addr_rd_03_07 == 10'd12)
|
||||
CN3_addr_rd_03_07 <= 10'd197;
|
||||
else if (CN3_addr_rd_03_07 == 10'd255)
|
||||
CN3_addr_rd_03_07 <= 10'd128;
|
||||
else if (CN3_addr_rd_03_07 == 10'd196)
|
||||
CN3_addr_rd_03_07 <= 10'd383;
|
||||
else if (CN3_addr_rd_03_07 == 10'd383)
|
||||
CN3_addr_rd_03_07 <= 10'd256;
|
||||
else if (CN3_addr_rd_03_07 == 10'd382)
|
||||
CN3_addr_rd_03_07 <= 10'd413;
|
||||
else if (CN3_addr_rd_03_07 == 10'd511)
|
||||
CN3_addr_rd_03_07 <= 10'd384;
|
||||
else
|
||||
CN3_addr_rd_03_07 <= CN3_addr_rd_03_07 + 10'd1;
|
||||
end
|
||||
// 对II8地址进行操作
|
||||
if (first_flag_cn_04) begin
|
||||
CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1;
|
||||
first_flag_cn_04 <= 1'd0;
|
||||
end else begin
|
||||
if (CN3_addr_rd_03_08 == 10'd1023)
|
||||
CN3_addr_rd_03_08 <= 10'd896;
|
||||
else if (CN3_addr_rd_03_08 == 10'd929)
|
||||
CN3_addr_rd_03_08 <= 10'd610;
|
||||
else if (CN3_addr_rd_03_08 == 10'd639)
|
||||
CN3_addr_rd_03_08 <= 10'd512;
|
||||
else if (CN3_addr_rd_03_08 == 10'd609)
|
||||
CN3_addr_rd_03_08 <= 10'd666;
|
||||
else if (CN3_addr_rd_03_08 == 10'd767)
|
||||
CN3_addr_rd_03_08 <= 10'd640;
|
||||
else if (CN3_addr_rd_03_08 == 10'd665)
|
||||
CN3_addr_rd_03_08 <= 10'd827;
|
||||
else if (CN3_addr_rd_03_08 == 10'd895)
|
||||
CN3_addr_rd_03_08 <= 10'd768;
|
||||
else
|
||||
CN3_addr_rd_03_08 <= CN3_addr_rd_03_08 + 10'd1;
|
||||
end
|
||||
end else begin
|
||||
CN1_addr_rd_02_01 <= 10'd639;
|
||||
CN2_addr_rd_04_02 <= 10'd24;
|
||||
CN2_addr_rd_04_03 <= 10'd926;
|
||||
CN2_addr_rd_04_04 <= 9'd294;
|
||||
CN3_addr_rd_02_05 <= 10'd352;
|
||||
CN3_addr_rd_02_06 <= 10'd639;
|
||||
CN3_addr_rd_03_07 <= 10'd12;
|
||||
CN3_addr_rd_03_08 <= 10'd929;
|
||||
first_flag_cn_01 <= 1'd1;
|
||||
first_flag_cn_02 <= 1'd1;
|
||||
first_flag_cn_03 <= 1'd1;
|
||||
first_flag_cn_04 <= 1'd1;
|
||||
first_flag_cn_05 <= 1'd1;
|
||||
first_flag_cn_06 <= 1'd1;
|
||||
first_flag_cn_07 <= 1'd1;
|
||||
first_flag_cn_08 <= 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU01; //第1列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU01;
|
||||
wire [WIDTH-1:0] din03_CHNL_CU01;
|
||||
wire [WIDTH-1:0] dout01_CU01;
|
||||
wire [WIDTH-1:0] dout02_CU01;
|
||||
wire [0:0] dout03_result_CU01;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU02; //第2列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU02;
|
||||
wire [WIDTH-1:0] din03_CN_CU02;
|
||||
wire [WIDTH-1:0] din04_CHNL_CU02;
|
||||
wire [WIDTH-1:0] dout01_CU02;
|
||||
wire [WIDTH-1:0] dout02_CU02;
|
||||
wire [WIDTH-1:0] dout03_CU02;
|
||||
wire [0:0] dout04_result_CU02;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU03; //第3列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CHNL_CU03;
|
||||
wire [WIDTH-1:0] dout01_CU03;
|
||||
wire [0:0] dout02_result_CU03;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU04; //第4列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU04;
|
||||
wire [WIDTH-1:0] din03_CN_CU04;
|
||||
wire [WIDTH-1:0] din04_CHNL_CU04;
|
||||
wire [WIDTH-1:0] dout01_CU04;
|
||||
wire [WIDTH-1:0] dout02_CU04;
|
||||
wire [WIDTH-1:0] dout03_CU04;
|
||||
wire [0:0] dout04_result_CU04;
|
||||
|
||||
wire [WIDTH-1:0] din01_CN_CU05; //第5列更新处理单元信号定义
|
||||
wire [WIDTH-1:0] din02_CN_CU05;
|
||||
wire [WIDTH-1:0] din03_CN_CU05;
|
||||
wire [WIDTH-1:0] din04_CN_CU05;
|
||||
wire [WIDTH-1:0] din05_CN_CU05;
|
||||
wire [WIDTH-1:0] din06_CN_CU05;
|
||||
wire [WIDTH-1:0] din07_CHNL_CU05;
|
||||
wire [WIDTH-1:0] dout01_CU05;
|
||||
wire [WIDTH-1:0] dout02_CU05;
|
||||
wire [WIDTH-1:0] dout03_CU05;
|
||||
wire [WIDTH-1:0] dout04_CU05;
|
||||
wire [WIDTH-1:0] dout05_CU05;
|
||||
wire [WIDTH-1:0] dout06_CU05;
|
||||
wire [0:0] dout07_result_CU05;
|
||||
|
||||
// CU模块的输入
|
||||
assign din01_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_01_00;
|
||||
assign din02_CN_CU01 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_01_00;
|
||||
|
||||
assign din01_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_02_00;
|
||||
assign din02_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_05;
|
||||
assign din03_CN_CU02 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_02_06;
|
||||
|
||||
assign din01_CN_CU03 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_01_00;
|
||||
|
||||
assign din01_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_03_00;
|
||||
assign din02_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_07;
|
||||
assign din03_CN_CU04 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_03_08;
|
||||
|
||||
assign din01_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_00;
|
||||
assign din02_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN1_dout_02_01;
|
||||
assign din03_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_02;
|
||||
assign din04_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_03;
|
||||
assign din05_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN2_dout_04_04;
|
||||
assign din06_CN_CU05 = (iter_num == 6'd0) ? 8'd0 : CN3_dout_04_00;
|
||||
|
||||
assign din03_CHNL_CU01 = CHNL_dout_01;
|
||||
assign din04_CHNL_CU02 = CHNL_dout_02;
|
||||
assign din02_CHNL_CU03 = CHNL_dout_03;
|
||||
assign din04_CHNL_CU04 = CHNL_dout_04;
|
||||
assign din07_CHNL_CU05 = 8'd0; //信道传输的数据只有2048bit，这里H矩阵是2560bit，所以在后512位上补0
|
||||
|
||||
|
||||
|
||||
VNU_2din CU_01 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU01),
|
||||
.din02_CN_CU(din02_CN_CU01),
|
||||
.din03_CHNL_CU(din03_CHNL_CU01),
|
||||
.dout01_CU(dout01_CU01),
|
||||
.dout02_CU(dout02_CU01),
|
||||
.dout03_result_CU(dout03_result_CU01));
|
||||
|
||||
VNU_3din CU_02 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU02),
|
||||
.din02_CN_CU(din02_CN_CU02),
|
||||
.din03_CN_CU(din03_CN_CU02),
|
||||
.din04_CHNL_CU(din04_CHNL_CU02),
|
||||
.dout01_CU(dout01_CU02),
|
||||
.dout02_CU(dout02_CU02),
|
||||
.dout03_CU(dout03_CU02),
|
||||
.dout04_result_CU(dout04_result_CU02)
|
||||
);
|
||||
|
||||
VNU_1din CU_03 (.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU03),
|
||||
.din02_CHNL_CU(din02_CHNL_CU03),
|
||||
.dout01_CU(dout01_CU03),
|
||||
.dout02_result_CU(dout02_result_CU03));
|
||||
|
||||
VNU_3din CU_04 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU04),
|
||||
.din02_CN_CU(din02_CN_CU04),
|
||||
.din03_CN_CU(din03_CN_CU04),
|
||||
.din04_CHNL_CU(din04_CHNL_CU04),
|
||||
.dout01_CU(dout01_CU04),
|
||||
.dout02_CU(dout02_CU04),
|
||||
.dout03_CU(dout03_CU04),
|
||||
.dout04_result_CU(dout04_result_CU04)
|
||||
);
|
||||
|
||||
VNU_6din CU_05 (
|
||||
.clk(clk),
|
||||
.din01_CN_CU(din01_CN_CU05),
|
||||
.din02_CN_CU(din02_CN_CU05),
|
||||
.din03_CN_CU(din03_CN_CU05),
|
||||
.din04_CN_CU(din04_CN_CU05),
|
||||
.din05_CN_CU(din05_CN_CU05),
|
||||
.din06_CN_CU(din06_CN_CU05),
|
||||
.din07_CHNL_CU(din07_CHNL_CU05),
|
||||
.dout01_CU(dout01_CU05),
|
||||
.dout02_CU(dout02_CU05),
|
||||
.dout03_CU(dout03_CU05),
|
||||
.dout04_CU(dout04_CU05),
|
||||
.dout05_CU(dout05_CU05),
|
||||
.dout06_CU(dout06_CU05),
|
||||
.dout07_result_CU(dout07_result_CU05)
|
||||
);
|
||||
|
||||
|
||||
// 设置写操作的时延
|
||||
parameter DELAY_WR = 11'd17;
|
||||
|
||||
// 控制VN的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
VN_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR)
|
||||
VN_wea <= 1'd1;
|
||||
else
|
||||
VN_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN存储的写地址(所有IM)
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_addr_wr_01_00 <= 9'd511;
|
||||
VN1_addr_wr_02_00 <= 10'd1023;
|
||||
VN2_addr_wr_01_00 <= 9'd511;
|
||||
VN2_addr_wr_02_00 <= 9'd511;
|
||||
VN2_addr_wr_03_00 <= 9'd511;
|
||||
VN3_addr_wr_01_00 <= 9'd511;
|
||||
VN3_addr_wr_04_00 <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
VN1_addr_wr_01_00 <= VN1_addr_wr_01_00 + 9'd1;
|
||||
VN1_addr_wr_02_00 <= VN1_addr_wr_02_00 + 10'd1;
|
||||
VN2_addr_wr_01_00 <= VN2_addr_wr_01_00 + 9'd1;
|
||||
VN2_addr_wr_02_00 <= VN2_addr_wr_02_00 + 9'd1;
|
||||
VN2_addr_wr_03_00 <= VN2_addr_wr_03_00 + 9'd1;
|
||||
VN3_addr_wr_01_00 <= VN3_addr_wr_01_00 + 9'd1;
|
||||
VN3_addr_wr_04_00 <= VN3_addr_wr_04_00 + 9'd1;
|
||||
end else begin
|
||||
VN1_addr_wr_01_00 <= 9'd511;
|
||||
VN1_addr_wr_02_00 <= 10'd1023;
|
||||
VN2_addr_wr_01_00 <= 9'd511;
|
||||
VN2_addr_wr_02_00 <= 9'd511;
|
||||
VN2_addr_wr_03_00 <= 9'd511;
|
||||
VN3_addr_wr_01_00 <= 9'd511;
|
||||
VN3_addr_wr_04_00 <= 9'd511;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN存储的写地址(II1-II8)
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_addr_wr_02_01 <= 10'd639;
|
||||
VN2_addr_wr_04_02 <= 10'd24;
|
||||
VN2_addr_wr_04_03 <= 10'd926;
|
||||
VN2_addr_wr_04_04 <= 9'd294;
|
||||
VN3_addr_wr_02_05 <= 10'd352;
|
||||
VN3_addr_wr_02_06 <= 10'd639;
|
||||
VN3_addr_wr_03_07 <= 10'd12;
|
||||
VN3_addr_wr_03_08 <= 10'd929;
|
||||
first_flag_vn_01 <= 1'd1;
|
||||
first_flag_vn_02 <= 1'd1;
|
||||
first_flag_vn_03 <= 1'd1;
|
||||
first_flag_vn_04 <= 1'd1;
|
||||
first_flag_vn_05 <= 1'd1;
|
||||
first_flag_vn_06 <= 1'd1;
|
||||
first_flag_vn_07 <= 1'd1;
|
||||
first_flag_vn_08 <= 1'd1;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
//对II1地址进行操作，确保初始化地址先加1
|
||||
if (first_flag_vn_05) begin
|
||||
VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1;
|
||||
first_flag_vn_05 <= 1'd0;
|
||||
end else begin
|
||||
if (VN1_addr_wr_02_01 == 10'd1023)
|
||||
VN1_addr_wr_02_01 <= 10'd624;
|
||||
else if (VN1_addr_wr_02_01 == 10'd639)
|
||||
VN1_addr_wr_02_01 <= 10'd512;
|
||||
else
|
||||
VN1_addr_wr_02_01 <= VN1_addr_wr_02_01 + 10'd1;
|
||||
end
|
||||
// 对II2地址进行操作
|
||||
if (first_flag_vn_06) begin
|
||||
VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1;
|
||||
first_flag_vn_06<= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_02 == 10'd127)
|
||||
VN2_addr_wr_04_02 <= 10'd0;
|
||||
else if (VN2_addr_wr_04_02 == 10'd24)
|
||||
VN2_addr_wr_04_02 <= 10'd203;
|
||||
else if (VN2_addr_wr_04_02 == 10'd255)
|
||||
VN2_addr_wr_04_02 <= 10'd128;
|
||||
else if (VN2_addr_wr_04_02 == 10'd202)
|
||||
VN2_addr_wr_04_02 <= 10'd376;
|
||||
else if (VN2_addr_wr_04_02 == 10'd383)
|
||||
VN2_addr_wr_04_02 <= 10'd256;
|
||||
else if (VN2_addr_wr_04_02 == 10'd375)
|
||||
VN2_addr_wr_04_02 <= 10'd477;
|
||||
else if (VN2_addr_wr_04_02 == 10'd511)
|
||||
VN2_addr_wr_04_02 <= 10'd384;
|
||||
else
|
||||
VN2_addr_wr_04_02 <= VN2_addr_wr_04_02 + 10'd1;
|
||||
end
|
||||
// 对II3地址进行操作
|
||||
if (first_flag_vn_07) begin
|
||||
VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1;
|
||||
first_flag_vn_07 <= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_03 == 10'd1023)
|
||||
VN2_addr_wr_04_03 <= 10'd896;
|
||||
else if (VN2_addr_wr_04_03 == 10'd926)
|
||||
VN2_addr_wr_04_03 <= 10'd535;
|
||||
else if (VN2_addr_wr_04_03 == 10'd639)
|
||||
VN2_addr_wr_04_03 <= 10'd512;
|
||||
else if (VN2_addr_wr_04_03 == 10'd534)
|
||||
VN2_addr_wr_04_03 <= 10'd694;
|
||||
else if (VN2_addr_wr_04_03 == 10'd767)
|
||||
VN2_addr_wr_04_03 <= 10'd640;
|
||||
else if (VN2_addr_wr_04_03 == 10'd693)
|
||||
VN2_addr_wr_04_03 <= 10'd777;
|
||||
else if (VN2_addr_wr_04_03 == 10'd895)
|
||||
VN2_addr_wr_04_03 <= 10'd768;
|
||||
else
|
||||
VN2_addr_wr_04_03 <= VN2_addr_wr_04_03 + 10'd1;
|
||||
end
|
||||
// 对II4地址进行操作
|
||||
if (first_flag_vn_08) begin
|
||||
VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1;
|
||||
first_flag_vn_08 <= 1'd0;
|
||||
end else begin
|
||||
if (VN2_addr_wr_04_04 == 9'd383)
|
||||
VN2_addr_wr_04_04 <= 9'd256;
|
||||
else if (VN2_addr_wr_04_04 == 9'd294)
|
||||
VN2_addr_wr_04_04 <= 9'd400;
|
||||
else if (VN2_addr_wr_04_04 == 9'd511)
|
||||
VN2_addr_wr_04_04 <= 9'd384;
|
||||
else if (VN2_addr_wr_04_04 == 9'd399)
|
||||
VN2_addr_wr_04_04 <= 9'd0;
|
||||
else if (VN2_addr_wr_04_04 == 9'd127)
|
||||
VN2_addr_wr_04_04 <= 9'd211;
|
||||
else if (VN2_addr_wr_04_04 == 9'd255)
|
||||
VN2_addr_wr_04_04 <= 9'd128;
|
||||
else
|
||||
VN2_addr_wr_04_04 <= VN2_addr_wr_04_04 + 9'd1;
|
||||
end
|
||||
// 对II5地址进行操作
|
||||
if (first_flag_vn_01) begin //确保初始化地址先加1
|
||||
VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1;
|
||||
first_flag_vn_01 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_02_05 == 10'd383)
|
||||
VN3_addr_wr_02_05 <= 10'd256;
|
||||
else if (VN3_addr_wr_02_05 == 10'd352)
|
||||
VN3_addr_wr_02_05 <= 10'd448;
|
||||
else if (VN3_addr_wr_02_05 == 10'd511)
|
||||
VN3_addr_wr_02_05 <= 10'd384;
|
||||
else if (VN3_addr_wr_02_05 == 10'd447)
|
||||
VN3_addr_wr_02_05 <= 10'd78;
|
||||
else if (VN3_addr_wr_02_05 == 10'd127)
|
||||
VN3_addr_wr_02_05 <= 10'd0;
|
||||
else if (VN3_addr_wr_02_05 == 10'd77)
|
||||
VN3_addr_wr_02_05 <= 10'd209;
|
||||
else if (VN3_addr_wr_02_05 == 10'd255)
|
||||
VN3_addr_wr_02_05 <= 10'd128;
|
||||
else
|
||||
VN3_addr_wr_02_05 <= VN3_addr_wr_02_05 + 10'd1;
|
||||
end
|
||||
// 对II6地址进行操作
|
||||
if (first_flag_vn_02) begin
|
||||
VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1;
|
||||
first_flag_vn_02 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_02_06 == 10'd767)
|
||||
VN3_addr_wr_02_06 <= 10'd774;
|
||||
else if (VN3_addr_wr_02_06 == 10'd895)
|
||||
VN3_addr_wr_02_06 <= 10'd768;
|
||||
else if (VN3_addr_wr_02_06 == 10'd773)
|
||||
VN3_addr_wr_02_06 <= 10'd931;
|
||||
else if (VN3_addr_wr_02_06 == 10'd1023)
|
||||
VN3_addr_wr_02_06 <= 10'd896;
|
||||
else if (VN3_addr_wr_02_06 == 10'd930)
|
||||
VN3_addr_wr_02_06 <= 10'd611;
|
||||
else if (VN3_addr_wr_02_06 == 10'd639)
|
||||
VN3_addr_wr_02_06 <= 10'd512;
|
||||
else
|
||||
VN3_addr_wr_02_06 <= VN3_addr_wr_02_06 + 10'd1;
|
||||
end
|
||||
// 对II7地址进行操作
|
||||
if (first_flag_vn_03) begin //确保初始化地址先加1
|
||||
VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1;
|
||||
first_flag_vn_03 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_03_07 == 10'd127)
|
||||
VN3_addr_wr_03_07 <= 10'd0;
|
||||
else if (VN3_addr_wr_03_07 == 10'd12)
|
||||
VN3_addr_wr_03_07 <= 10'd197;
|
||||
else if (VN3_addr_wr_03_07 == 10'd255)
|
||||
VN3_addr_wr_03_07 <= 10'd128;
|
||||
else if (VN3_addr_wr_03_07 == 10'd196)
|
||||
VN3_addr_wr_03_07 <= 10'd383;
|
||||
else if (VN3_addr_wr_03_07 == 10'd383)
|
||||
VN3_addr_wr_03_07 <= 10'd256;
|
||||
else if (VN3_addr_wr_03_07 == 10'd382)
|
||||
VN3_addr_wr_03_07 <= 10'd413;
|
||||
else if (VN3_addr_wr_03_07 == 10'd511)
|
||||
VN3_addr_wr_03_07 <= 10'd384;
|
||||
else
|
||||
VN3_addr_wr_03_07 <= VN3_addr_wr_03_07 + 10'd1;
|
||||
end
|
||||
// 对II8地址进行操作
|
||||
if (first_flag_vn_04) begin
|
||||
VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1;
|
||||
first_flag_vn_04 <= 1'd0;
|
||||
end else begin
|
||||
if (VN3_addr_wr_03_08 == 10'd1023)
|
||||
VN3_addr_wr_03_08 <= 10'd896;
|
||||
else if (VN3_addr_wr_03_08 == 10'd929)
|
||||
VN3_addr_wr_03_08 <= 10'd610;
|
||||
else if (VN3_addr_wr_03_08 == 10'd639)
|
||||
VN3_addr_wr_03_08 <= 10'd512;
|
||||
else if (VN3_addr_wr_03_08 == 10'd609)
|
||||
VN3_addr_wr_03_08 <= 10'd666;
|
||||
else if (VN3_addr_wr_03_08 == 10'd767)
|
||||
VN3_addr_wr_03_08 <= 10'd640;
|
||||
else if (VN3_addr_wr_03_08 == 10'd665)
|
||||
VN3_addr_wr_03_08 <= 10'd827;
|
||||
else if (VN3_addr_wr_03_08 == 10'd895)
|
||||
VN3_addr_wr_03_08 <= 10'd768;
|
||||
else
|
||||
VN3_addr_wr_03_08 <= VN3_addr_wr_03_08 + 10'd1;
|
||||
end
|
||||
end else begin
|
||||
VN1_addr_wr_02_01 <= 10'd639;
|
||||
VN2_addr_wr_04_02 <= 10'd24;
|
||||
VN2_addr_wr_04_03 <= 10'd926;
|
||||
VN2_addr_wr_04_04 <= 9'd294;
|
||||
VN3_addr_wr_02_05 <= 10'd352;
|
||||
VN3_addr_wr_02_06 <= 10'd639;
|
||||
VN3_addr_wr_03_07 <= 10'd12;
|
||||
VN3_addr_wr_03_08 <= 10'd929;
|
||||
first_flag_vn_01 <= 1'd1;
|
||||
first_flag_vn_02 <= 1'd1;
|
||||
first_flag_vn_03 <= 1'd1;
|
||||
first_flag_vn_04 <= 1'd1;
|
||||
first_flag_vn_05 <= 1'd1;
|
||||
first_flag_vn_06 <= 1'd1;
|
||||
first_flag_vn_07 <= 1'd1;
|
||||
first_flag_vn_08 <= 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制VN的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
VN1_din_01_00 <= 8'd0;
|
||||
VN1_din_02_00 <= 8'd0;
|
||||
VN2_din_01_00 <= 8'd0;
|
||||
VN2_din_02_00 <= 8'd0;
|
||||
VN2_din_03_00 <= 8'd0;
|
||||
VN3_din_01_00 <= 8'd0;
|
||||
VN3_din_04_00 <= 8'd0;
|
||||
VN1_din_02_01 <= 8'd0;
|
||||
VN2_din_04_02 <= 8'd0;
|
||||
VN2_din_04_03 <= 8'd0;
|
||||
VN2_din_04_04 <= 8'd0;
|
||||
VN3_din_02_05 <= 8'd0;
|
||||
VN3_din_02_06 <= 8'd0;
|
||||
VN3_din_03_07 <= 8'd0;
|
||||
VN3_din_03_08 <= 8'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
VN1_din_01_00 <= dout01_CU03;
|
||||
VN1_din_02_00 <= dout01_CU05;
|
||||
VN2_din_01_00 <= dout01_CU01;
|
||||
VN2_din_02_00 <= dout01_CU02;
|
||||
VN2_din_03_00 <= dout01_CU04;
|
||||
VN3_din_01_00 <= dout02_CU01;
|
||||
VN3_din_04_00 <= dout06_CU05;
|
||||
VN1_din_02_01 <= dout02_CU05;
|
||||
VN2_din_04_02 <= dout03_CU05;
|
||||
VN2_din_04_03 <= dout04_CU05;
|
||||
VN2_din_04_04 <= dout05_CU05;
|
||||
VN3_din_02_05 <= dout02_CU02;
|
||||
VN3_din_02_06 <= dout03_CU02;
|
||||
VN3_din_03_07 <= dout02_CU04;
|
||||
VN3_din_03_08 <= dout03_CU04;
|
||||
end else begin
|
||||
VN1_din_01_00 <= 8'd0;
|
||||
VN1_din_02_00 <= 8'd0;
|
||||
VN2_din_01_00 <= 8'd0;
|
||||
VN2_din_02_00 <= 8'd0;
|
||||
VN2_din_03_00 <= 8'd0;
|
||||
VN3_din_01_00 <= 8'd0;
|
||||
VN3_din_04_00 <= 8'd0;
|
||||
VN1_din_02_01 <= 8'd0;
|
||||
VN2_din_04_02 <= 8'd0;
|
||||
VN2_din_04_03 <= 8'd0;
|
||||
VN2_din_04_04 <= 8'd0;
|
||||
VN3_din_02_05 <= 8'd0;
|
||||
VN3_din_02_06 <= 8'd0;
|
||||
VN3_din_03_07 <= 8'd0;
|
||||
VN3_din_03_08 <= 8'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR的写使能
|
||||
always @ (posedge clk) begin
|
||||
if(rst_VN) begin
|
||||
DR_wea <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR && iter_num == MAX_ITER_NUM - 1)
|
||||
// 对写全能用迭代次数进行限制，防止输出译码结果时有新的数据写入
|
||||
DR_wea <= 1'd1;
|
||||
else
|
||||
DR_wea <= 1'd0;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR存储的写地址
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
DR_addr_wr <= 9'd511;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR)
|
||||
DR_addr_wr <= DR_addr_wr + 9'd1;
|
||||
else
|
||||
DR_addr_wr <= 9'd511;
|
||||
end
|
||||
end
|
||||
|
||||
// 控制DR存储的写数据
|
||||
always @ (posedge clk) begin
|
||||
if (rst_VN) begin
|
||||
DR_din_01 <= 1'd0;
|
||||
DR_din_02 <= 1'd0;
|
||||
DR_din_03 <= 1'd0;
|
||||
DR_din_04 <= 1'd0;
|
||||
DR_din_05 <= 1'd0;
|
||||
end else begin
|
||||
if (cnt_2_VN >= 11'd1 + DELAY_WR && cnt_2_VN <= 11'd512 + DELAY_WR) begin
|
||||
DR_din_01 <= dout03_result_CU01;
|
||||
DR_din_02 <= dout04_result_CU02;
|
||||
DR_din_03 <= dout02_result_CU03;
|
||||
DR_din_04 <= dout04_result_CU04;
|
||||
DR_din_05 <= dout07_result_CU05;
|
||||
end else begin
|
||||
DR_din_01 <= 1'd0;
|
||||
DR_din_02 <= 1'd0;
|
||||
DR_din_03 <= 1'd0;
|
||||
DR_din_04 <= 1'd0;
|
||||
DR_din_05 <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//状态指示
|
||||
assign data_start_ck_VN = (cnt_VN == 11'd1 + DELAY_WR - 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0;
|
||||
assign data_start_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd1 && iter_num == MAX_ITER_NUM - 1) ? 1'd1 : 1'd0;
|
||||
assign end_VN = (cnt_VN == 11'd512 + DELAY_WR + 11'd2 && iter_num <= MAX_ITER_NUM - 2) ? 1'd1 : 1'd0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 21:36:07 01/20/2018
|
||||
// Design Name:
|
||||
// Module Name: abs_min_4din
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module abs_min_4din #(
|
||||
parameter WIDTH = 4'd8
|
||||
) (
|
||||
input clk,
|
||||
input [WIDTH-1:0] din01, //din01<din02
|
||||
input [WIDTH-1:0] din02,
|
||||
input [WIDTH-1:0] din03, //din03<din04
|
||||
input [WIDTH-1:0] din04,
|
||||
output reg [WIDTH-1:0] dout_min = 8'd0,
|
||||
output reg [WIDTH-1:0] dout_sec = 8'd0
|
||||
); //输出相对输入延时1个周期
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (din02 <= din03) begin
|
||||
dout_min <= din01;
|
||||
dout_sec <= din02;
|
||||
end
|
||||
else begin
|
||||
if (din01 <= din03) begin
|
||||
dout_min <= din01;
|
||||
dout_sec <= din03;
|
||||
end
|
||||
else begin
|
||||
dout_min <= din03;
|
||||
dout_sec <= (din01 < din04) ? din01 : din04;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer: liu yongxin
|
||||
|
||||
+56
-32
@@ -16,11 +16,13 @@
|
||||
module ad9361_mgc_pin_ctrl (
|
||||
input clk,
|
||||
input rst,
|
||||
// input start,
|
||||
input start,
|
||||
input [11:0] rx_data_i,
|
||||
input [11:0] rx_data_q,
|
||||
// this port is from zynq to ad9361
|
||||
output wire [ 3:0] ad9361_ctrl_in
|
||||
output wire [ 3:0] ad9361_ctrl_in,
|
||||
output wire flag_mgc_done_pulse, // active high pulse signal
|
||||
output reg flag_mgc_done = 0 // active high level signal
|
||||
|
||||
);
|
||||
|
||||
@@ -32,7 +34,6 @@ module ad9361_mgc_pin_ctrl (
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
wire start;
|
||||
reg start_d1;
|
||||
wire start_posedge;
|
||||
wire inc_pulse;
|
||||
@@ -41,6 +42,9 @@ module ad9361_mgc_pin_ctrl (
|
||||
wire flag_too_low; // low amplitude
|
||||
wire flag_adjust;
|
||||
reg [3:0] cnt_pulse_width;
|
||||
// indicating the mgc done ready
|
||||
wire power_measure_done_pulse;
|
||||
|
||||
|
||||
// adjust fsm
|
||||
localparam S_IDLE = 0;
|
||||
@@ -51,14 +55,15 @@ module ad9361_mgc_pin_ctrl (
|
||||
reg [2:0] ns;
|
||||
|
||||
// ******** Assingment ********
|
||||
assign ad9361_ctrl_in[0] = inc_pulse;
|
||||
assign ad9361_ctrl_in[1] = dec_pulse;
|
||||
assign ad9361_ctrl_in[0] = inc_pulse;
|
||||
assign ad9361_ctrl_in[1] = dec_pulse;
|
||||
|
||||
assign flag_adjust = flag_too_high | flag_too_low;
|
||||
assign inc_pulse = (cs == S_INC);
|
||||
assign dec_pulse = (cs == S_DEC);
|
||||
assign flag_adjust = flag_too_high | flag_too_low;
|
||||
assign inc_pulse = (cs == S_INC);
|
||||
assign dec_pulse = (cs == S_DEC);
|
||||
|
||||
assign start_posedge = start & ~start_d1;
|
||||
assign start_posedge = start & ~start_d1;
|
||||
assign flag_mgc_done_pulse = power_measure_done_pulse;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
@@ -76,6 +81,15 @@ module ad9361_mgc_pin_ctrl (
|
||||
start_d1 <= start;
|
||||
end
|
||||
|
||||
// single pulse to level signal
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_mgc_done <= 0;
|
||||
end
|
||||
else if (power_measure_done_pulse) begin
|
||||
flag_mgc_done <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
// FSM
|
||||
always @(posedge clk) begin
|
||||
@@ -105,15 +119,24 @@ module ad9361_mgc_pin_ctrl (
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_DEC: begin
|
||||
if (cnt_pulse_width == 0) begin
|
||||
ns = S_DONE;
|
||||
end
|
||||
else begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
S_DONE: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
@@ -122,34 +145,35 @@ module ad9361_mgc_pin_ctrl (
|
||||
// measuring the signal power
|
||||
// two cases, amplitute too high or amplitude too low
|
||||
power_measure u_power_measure (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (start_posedge),
|
||||
.data_i (rx_data_i),
|
||||
.data_q (rx_data_q),
|
||||
.flag_too_high(flag_too_high),
|
||||
.flag_too_low (flag_too_low)
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.start (start_posedge),
|
||||
.data_i (rx_data_i),
|
||||
.data_q (rx_data_q),
|
||||
.flag_too_high (flag_too_high),
|
||||
.flag_too_low (flag_too_low),
|
||||
.power_measure_done_pulse(power_measure_done_pulse)
|
||||
);
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
vio_mgc_control_in u_vio_mgc_control_in (
|
||||
.clk (clk), // input wire clk
|
||||
.probe_out0(start) // output wire [0 : 0] probe_out0
|
||||
);
|
||||
// vio_mgc_control_in u_vio_mgc_control_in (
|
||||
// .clk (clk), // input wire clk
|
||||
// .probe_out0(start) // output wire [0 : 0] probe_out0
|
||||
// );
|
||||
|
||||
ila_ad9361_mgc u_ila_ad9361_mgc (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(start_posedge), // input wire [0:0] probe0
|
||||
.probe1(rx_data_i), // input wire [11:0] probe1
|
||||
.probe2(u_power_measure.cs), // input wire [2:0] probe2
|
||||
.probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
|
||||
.probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
|
||||
.probe5(flag_too_high), // input wire [0:0] probe5
|
||||
.probe6(flag_too_low), // input wire [0:0] probe6
|
||||
.probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
|
||||
.probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
|
||||
);
|
||||
// ila_ad9361_mgc u_ila_ad9361_mgc (
|
||||
// .clk (clk), // input wire clk
|
||||
// .probe0(start_posedge), // input wire [0:0] probe0
|
||||
// .probe1(rx_data_i), // input wire [11:0] probe1
|
||||
// .probe2(u_power_measure.cs), // input wire [2:0] probe2
|
||||
// .probe3(u_power_measure.sign_bit_num_i), // input wire [3:0] probe3
|
||||
// .probe4(u_power_measure.sign_bit_num_min_i), // input wire [3:0] probe4
|
||||
// .probe5(flag_too_high), // input wire [0:0] probe5
|
||||
// .probe6(flag_too_low), // input wire [0:0] probe6
|
||||
// .probe7(u_power_measure.cnt_amp_too_high), // input wire [0:0] probe6
|
||||
// .probe8(u_power_measure.cnt_startup) // input wire [11:0] probe6
|
||||
// );
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@ module add_prefix #(
|
||||
//! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
|
||||
parameter WIDTH = 2,
|
||||
parameter DATA_LEN = 256,
|
||||
parameter PREFIX_LEN = 8
|
||||
parameter PREFIX_LEN = 32
|
||||
) (
|
||||
input clk,
|
||||
input start,
|
||||
|
||||
@@ -0,0 +1,624 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/01/04 21:09:20
|
||||
// Design Name:
|
||||
// Module Name: data_equalizer
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module data_equalizer(
|
||||
input clk,
|
||||
input rst,
|
||||
input EQUenable_vio,
|
||||
|
||||
input nd_pilot2,
|
||||
input flag_ChnEstFFT_done, //信道估计两次fft输入完毕后拉高1clk(Chn_Estimate给出)
|
||||
|
||||
//数据的fifo，4个
|
||||
input [9:0] dout_data1i,
|
||||
input [9:0] dout_data1q,
|
||||
output reg rd_en_data1 = 1'd0,
|
||||
input [9:0] dout_data2i,
|
||||
input [9:0] dout_data2q,
|
||||
output reg rd_en_data2 = 1'd0,
|
||||
input flag_dataow, //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||||
|
||||
//fft核
|
||||
input [25:0] fft_out_i,
|
||||
input [25:0] fft_out_q,
|
||||
input fft_out_nd,
|
||||
input [7:0] fft_index,
|
||||
output reg [16:0] fft_in_i = 17'd0,
|
||||
output reg [16:0] fft_in_q = 17'd0,
|
||||
output reg fft_in_nd = 1'd0,
|
||||
|
||||
//ifft核
|
||||
input [28:0] ifft_out_i,
|
||||
input [28:0] ifft_out_q,
|
||||
input ifft_out_nd,
|
||||
input [7:0] ifft_index,
|
||||
output reg [19:0] ifft_in_i = 20'd0,
|
||||
output reg [19:0] ifft_in_q = 20'd0,
|
||||
output reg ifft_in_nd = 1'd0,
|
||||
|
||||
//MMSE信道估计结果RAM
|
||||
output reg [7:0] addrout_MMSE = 8'd0,
|
||||
input [21:0] dout_MMSE,
|
||||
|
||||
//均衡结果输出
|
||||
output reg nd_SC_FDE_dout = 1'd0,
|
||||
output reg [9:0] SC_FDE_douti = 10'd0,
|
||||
output reg [9:0] SC_FDE_doutq = 10'd0,
|
||||
|
||||
//debug,溢出标志
|
||||
output reg flagoverflow_ifftindata_28to20i = 1'd0, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output reg flagoverflow_ifftindata_28to20q = 1'd0, //均衡完毕后（频域结果）的截位，即乘法器输出结果的截位，28截到20
|
||||
output reg flagoverflow_fftdata_26to16i = 1'd0, //数据段ow的fft输出截位，26截到16
|
||||
output reg flagoverflow_fftdata_26to16q = 1'd0, //数据段ow的fft输出截位，26截到16
|
||||
output reg flagoverflow_FDE_dataout_29to10i = 1'd0, //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
output reg flagoverflow_FDE_dataout_29to10q = 1'd0 //ifft结果截位，即均衡结果处，结果先除掉低8位，29-7=22截到10
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------fft的输入控制状态机---------------------------------------------------------//
|
||||
reg [3:0] state_fftin = 4'd0;
|
||||
reg [7:0] cnt_256 = 8'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
state_fftin <= 4'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
|
||||
rd_en_data1 <= 1'd0;
|
||||
rd_en_data2 <= 1'd0;
|
||||
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_fftin)
|
||||
//帧间复位结束后，等待nd_pilot2,即导频部分全部到达
|
||||
4'd0:begin
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
if(nd_pilot2) state_fftin <= state_fftin + 4'd1;
|
||||
else state_fftin <= state_fftin;
|
||||
end
|
||||
|
||||
//等待flag_ChnEstFFT_done,即信道估计的两次fft输入全部完成
|
||||
4'd1:begin
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
if(flag_ChnEstFFT_done) state_fftin <= state_fftin + 4'd1;
|
||||
else state_fftin <= state_fftin;
|
||||
end
|
||||
|
||||
//计数60clk,开始输入第一组data的ow给fft，保证其输出的时候MMSE信道估计结果已全部准备完毕
|
||||
4'd2:begin
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
rd_en_data2 <= 1'd0;
|
||||
if(cnt_256==8'd60) begin
|
||||
rd_en_data1 <= 1'd1;
|
||||
cnt_256 <= 8'd0;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
else begin
|
||||
rd_en_data1 <= 1'd0;
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
state_fftin <= state_fftin;
|
||||
end
|
||||
end
|
||||
|
||||
//从rd_en_data1为1的第一个clk开始，输出第0组数据。rd_en_data1保持有效共需256clk，即最后一个clk的数据出到出口时仍需一个读nd（用于读空fifo）
|
||||
4'd3:begin
|
||||
rd_en_data2 <= 1'd0;
|
||||
if(cnt_256==8'd254) begin
|
||||
rd_en_data1 <= 1'd1;
|
||||
fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
|
||||
fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= 6'd0;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
else begin
|
||||
rd_en_data1 <= 1'd1;
|
||||
fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
|
||||
fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= cnt_256 + 6'd1;
|
||||
state_fftin <= state_fftin;
|
||||
end
|
||||
end
|
||||
4'd4:begin
|
||||
rd_en_data2 <= 1'd0;
|
||||
rd_en_data1 <= 1'd0;
|
||||
fft_in_i <= {{7{dout_data1i[9]}},dout_data1i};
|
||||
fft_in_q <= {{7{dout_data1q[9]}},dout_data1q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= 6'd0;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
|
||||
//data1读空，等待flag_dataow，说明下一个256数据段缓存完毕，可以取用
|
||||
4'd5:begin
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
rd_en_data1 <= 1'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
if(flag_dataow) begin
|
||||
rd_en_data2 <= 1'd1;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
else begin
|
||||
rd_en_data2 <= 1'd0;
|
||||
state_fftin <= state_fftin;
|
||||
end
|
||||
end
|
||||
|
||||
//从rd_en_data2为1的第一个clk开始，输出第0组数据。rd_en_data2保持有效共需256clk，即最后一个clk的数据出到出口时仍需一个读nd（用于读空fifo）
|
||||
4'd6:begin
|
||||
rd_en_data1 <= 1'd0;
|
||||
if(cnt_256==8'd254) begin
|
||||
rd_en_data2 <= 1'd1;
|
||||
fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
|
||||
fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= 6'd0;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
else begin
|
||||
rd_en_data2 <= 1'd1;
|
||||
fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
|
||||
fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= cnt_256 + 6'd1;
|
||||
state_fftin <= state_fftin;
|
||||
end
|
||||
end
|
||||
4'd7:begin
|
||||
rd_en_data2 <= 1'd0;
|
||||
rd_en_data1 <= 1'd0;
|
||||
fft_in_i <= {{7{dout_data2i[9]}},dout_data2i};
|
||||
fft_in_q <= {{7{dout_data2q[9]}},dout_data2q};
|
||||
fft_in_nd <= 1'd1;
|
||||
cnt_256 <= 6'd0;
|
||||
state_fftin <= state_fftin + 4'd1;
|
||||
end
|
||||
|
||||
//data2读空，等待flag_dataow，说明下一个256数据段缓存完毕，可以取用；或等待nd_pilot2，说明本数据段结束，下一数据段的导频缓存完毕
|
||||
4'd8:begin
|
||||
fft_in_i <= 17'd0;
|
||||
fft_in_q <= 17'd0;
|
||||
fft_in_nd <= 1'd0;
|
||||
rd_en_data2 <= 1'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
if(flag_dataow) begin
|
||||
rd_en_data1 <= 1'd1;
|
||||
state_fftin <= 4'd3;
|
||||
end
|
||||
else begin
|
||||
if(nd_pilot2) begin
|
||||
rd_en_data1 <= 1'd0;
|
||||
state_fftin <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
rd_en_data1 <= 1'd0;
|
||||
state_fftin <= state_fftin;
|
||||
end
|
||||
end
|
||||
end
|
||||
default:state_fftin <= 4'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------fft的输出控制状态机---------------------------------------------------------//
|
||||
reg [1:0] state_fftout = 2'd0;
|
||||
reg fft_out_nd_d1 = 1'd0;
|
||||
reg [25:0] fft_out_i_d1 = 26'd0;
|
||||
reg [25:0] fft_out_q_d1 = 26'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
state_fftout <= 2'd0;
|
||||
|
||||
fft_out_nd_d1 <= 1'd0;
|
||||
fft_out_i_d1 <= 26'd0;
|
||||
fft_out_q_d1 <= 26'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_fftout)
|
||||
//帧间复位结束后，等待nd_pilot2,即导频部分全部到达
|
||||
2'd0:begin
|
||||
fft_out_nd_d1 <= 1'd0;
|
||||
fft_out_i_d1 <= 26'd0;
|
||||
fft_out_q_d1 <= 26'd0;
|
||||
if(nd_pilot2) state_fftout <= state_fftout + 2'd1;
|
||||
else state_fftout <= state_fftout;
|
||||
end
|
||||
|
||||
//等待flag_ChnEstFFT_done,即信道估计的两次fft输入全部完成
|
||||
2'd1:begin
|
||||
fft_out_nd_d1 <= 1'd0;
|
||||
fft_out_i_d1 <= 26'd0;
|
||||
fft_out_q_d1 <= 26'd0;
|
||||
if(flag_ChnEstFFT_done) state_fftout <= state_fftout + 2'd1;
|
||||
else state_fftout <= state_fftout;
|
||||
end
|
||||
|
||||
//等待第一组fft结果输出完毕。此组结果应为信道估计的第二次fft结果，本模块不取用
|
||||
2'd2:begin
|
||||
fft_out_nd_d1 <= 1'd0;
|
||||
fft_out_i_d1 <= 26'd0;
|
||||
fft_out_q_d1 <= 26'd0;
|
||||
if(fft_index==8'd255) state_fftout <= state_fftout + 2'd1;
|
||||
else state_fftout <= state_fftout;
|
||||
|
||||
end
|
||||
|
||||
//fft_out_nd指示fft结果有效。将fft输出延时1clk。nd_pilot2有效说明下一帧的导频部分输入完毕，转回状态1
|
||||
2'd3:begin
|
||||
fft_out_nd_d1 <= fft_out_nd;
|
||||
fft_out_i_d1 <= fft_out_i;
|
||||
fft_out_q_d1 <= fft_out_q;
|
||||
if(nd_pilot2) state_fftout <= 2'd1;
|
||||
else state_fftout <= state_fftout;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------复数乘法器+输出截位及溢出标志---------------------------------------------------------//
|
||||
reg mulin_nd = 1'd0;
|
||||
reg [15:0] mulin_ai = 16'd0;
|
||||
reg [15:0] mulin_aq = 16'd0;
|
||||
reg [10:0] mulin_bi = 11'd0;
|
||||
reg [10:0] mulin_bq = 11'd0;
|
||||
wire mulout_nd;
|
||||
wire[63:0] mulout_data;
|
||||
|
||||
SC_FDE_commul SC_FDE_commul (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_a_tvalid (mulin_nd), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata ({mulin_aq,mulin_ai}), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (mulin_nd), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata ({5'd0,mulin_bq,5'd0,mulin_bi}), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid (mulout_nd), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (mulout_data) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
wire [27:0] mulout_datai;
|
||||
wire [27:0] mulout_dataq;
|
||||
assign mulout_datai = mulout_data[27:0];
|
||||
assign mulout_dataq = mulout_data[59:32];
|
||||
|
||||
|
||||
|
||||
|
||||
reg mulifft_nd = 1'd0;
|
||||
reg [19:0] mulifft_datai = 20'd0;
|
||||
reg [19:0] mulifft_dataq = 20'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
mulifft_nd <= 1'd0;
|
||||
mulifft_datai <= 20'd0;
|
||||
mulifft_dataq <= 20'd0;
|
||||
flagoverflow_ifftindata_28to20i <= 1'd0;
|
||||
flagoverflow_ifftindata_28to20q <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(mulout_nd) begin
|
||||
mulifft_nd <= 1'd1;
|
||||
if(mulout_datai[27:19]!=9'd511&&mulout_datai[27:19]!=9'd0) begin
|
||||
flagoverflow_ifftindata_28to20i <= 1'd1;
|
||||
mulifft_datai <= (mulout_datai[27])? 20'b1000_0000_0000_0000_0000 : 20'b0111_1111_1111_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_ifftindata_28to20i <= 1'd0;
|
||||
mulifft_datai <= mulout_datai[19:0];
|
||||
end
|
||||
if(mulout_dataq[27:19]!=9'd511&&mulout_dataq[27:19]!=9'd0) begin
|
||||
flagoverflow_ifftindata_28to20q <= 1'd1;
|
||||
mulifft_dataq <= (mulout_dataq[27])? 20'b1000_0000_0000_0000_0000 : 20'b0111_1111_1111_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_ifftindata_28to20q <= 1'd0;
|
||||
mulifft_dataq <= mulout_dataq[19:0];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
mulifft_nd <= 1'd0;
|
||||
mulifft_datai <= 20'd0;
|
||||
mulifft_dataq <= 20'd0;
|
||||
flagoverflow_ifftindata_28to20i <= 1'd0;
|
||||
flagoverflow_ifftindata_28to20q <= 1'd0;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------------------复数乘法器输入控制状态机---------------------------------------------------------//
|
||||
reg mulin_nd_d0 = 1'd0;
|
||||
reg [15:0] mulin_i_d0 = 16'd0;
|
||||
reg [15:0] mulin_q_d0 = 16'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
addrout_MMSE <= 8'd0;
|
||||
mulin_nd_d0 <= 1'd0;
|
||||
mulin_i_d0 <= 16'd0;
|
||||
mulin_q_d0 <= 16'd0;
|
||||
flagoverflow_fftdata_26to16i <= 1'd0;
|
||||
flagoverflow_fftdata_26to16q <= 1'd0;
|
||||
|
||||
mulin_nd <= 1'd0;
|
||||
mulin_ai <= 16'd0;
|
||||
mulin_aq <= 16'd0;
|
||||
mulin_bi <= 11'd0;
|
||||
mulin_bq <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
//fft输出再延时1clk，利用这个延时取出mmse信道估计结果。截位到16bit，设置溢出标志
|
||||
if(fft_out_nd_d1) begin
|
||||
addrout_MMSE <= addrout_MMSE + 8'd1;
|
||||
mulin_nd_d0 <= 1'd1;
|
||||
if(fft_out_i_d1[25:15]!=11'd2047&&fft_out_i_d1[25:15]!=11'd0) begin
|
||||
flagoverflow_fftdata_26to16i <= 1'd1;
|
||||
mulin_i_d0 <= (fft_out_i_d1[25])? 16'b1000_0000_0000_0000 : 16'b0111_1111_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_fftdata_26to16i <= 1'd0;
|
||||
mulin_i_d0 <= fft_out_i_d1[15:0];
|
||||
end
|
||||
if(fft_out_q_d1[25:15]!=11'd2047&&fft_out_q_d1[25:15]!=11'd0) begin
|
||||
flagoverflow_fftdata_26to16q <= 1'd1;
|
||||
mulin_q_d0 <= (fft_out_q_d1[25])? 16'b1000_0000_0000_0000 : 16'b0111_1111_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_fftdata_26to16q <= 1'd0;
|
||||
mulin_q_d0 <= fft_out_q_d1[15:0];
|
||||
end
|
||||
end
|
||||
else begin
|
||||
addrout_MMSE <= 8'd0;
|
||||
mulin_nd_d0 <= 1'd0;
|
||||
mulin_i_d0 <= 16'd0;
|
||||
mulin_q_d0 <= 16'd0;
|
||||
flagoverflow_fftdata_26to16i <= 1'd0;
|
||||
flagoverflow_fftdata_26to16q <= 1'd0;
|
||||
end
|
||||
|
||||
if(mulin_nd_d0) begin
|
||||
mulin_nd <= 1'd1;
|
||||
mulin_ai <= mulin_i_d0;
|
||||
mulin_aq <= mulin_q_d0;
|
||||
if(EQUenable_vio) begin
|
||||
mulin_bi <= dout_MMSE[10:0];
|
||||
mulin_bq <= dout_MMSE[21:11];
|
||||
end
|
||||
else begin
|
||||
mulin_bi <= 11'd1;
|
||||
mulin_bq <= 11'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
mulin_nd <= 1'd0;
|
||||
mulin_ai <= 16'd0;
|
||||
mulin_aq <= 16'd0;
|
||||
mulin_bi <= 11'd0;
|
||||
mulin_bq <= 11'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------乘法器输出->ifft的输入控制------------------------------------------------------//
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
ifft_in_i <= 20'd0;
|
||||
ifft_in_q <= 20'd0;
|
||||
ifft_in_nd <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(mulifft_nd) begin
|
||||
ifft_in_i <= mulifft_datai;
|
||||
ifft_in_q <= mulifft_dataq;
|
||||
ifft_in_nd <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
ifft_in_i <= 20'd0;
|
||||
ifft_in_q <= 20'd0;
|
||||
ifft_in_nd <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------ifft的输出控制+截位+溢出标志设置--------------------------------------------------//
|
||||
reg ifft_out_ce = 1'd0;
|
||||
reg ifft_out_nd_d1 = 1'd0;
|
||||
reg [28:0] ifft_out_i_d1 = 29'd0;
|
||||
reg [28:0] ifft_out_q_d1 = 29'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
ifft_out_ce <= 1'd0;
|
||||
ifft_out_nd_d1 <= 1'd0;
|
||||
ifft_out_i_d1 <= 29'd0;
|
||||
ifft_out_q_d1 <= 29'd0;
|
||||
end
|
||||
else begin
|
||||
if(ifft_out_ce==1'd0) begin
|
||||
if(flag_ChnEstFFT_done) begin
|
||||
ifft_out_ce <= 1'd1;
|
||||
end
|
||||
else begin
|
||||
ifft_out_ce <= 1'd0;
|
||||
end
|
||||
ifft_out_nd_d1 <= 1'd0;
|
||||
ifft_out_i_d1 <= 29'd0;
|
||||
ifft_out_q_d1 <= 29'd0;
|
||||
end
|
||||
else begin
|
||||
if(nd_pilot2) begin
|
||||
ifft_out_ce <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
ifft_out_ce <= 1'd1;
|
||||
end
|
||||
ifft_out_nd_d1 <= ifft_out_nd;
|
||||
ifft_out_i_d1 <= ifft_out_i;
|
||||
ifft_out_q_d1 <= ifft_out_q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
nd_SC_FDE_dout <= 1'd0;
|
||||
SC_FDE_douti <= 10'd0;
|
||||
SC_FDE_doutq <= 10'd0;
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
if(ifft_out_nd_d1) begin
|
||||
nd_SC_FDE_dout <= 1'd1;
|
||||
if(EQUenable_vio) begin //均衡开启，结果保留10bit，低位截掉8+5=13bit
|
||||
if(ifft_out_i_d1[28:22]!=7'd127&&ifft_out_i_d1[28:22]!=7'd0) begin
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd1;
|
||||
SC_FDE_douti <= (ifft_out_i_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||||
SC_FDE_douti <= ifft_out_i_d1[22:13];
|
||||
end
|
||||
if(ifft_out_q_d1[28:22]!=7'd127&&ifft_out_q_d1[28:22]!=7'd0) begin
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd1;
|
||||
SC_FDE_doutq <= (ifft_out_q_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||||
SC_FDE_doutq <= ifft_out_q_d1[22:13];
|
||||
end
|
||||
end
|
||||
else begin //均衡关闭，结果保留10bit，低位截掉8bit（结果应与输入相同）
|
||||
if(ifft_out_i_d1[28:17]!=12'd4095&&ifft_out_i_d1[28:17]!=12'd0) begin
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd1;
|
||||
SC_FDE_douti <= (ifft_out_i_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||||
SC_FDE_douti <= ifft_out_i_d1[17:8];
|
||||
end
|
||||
if(ifft_out_q_d1[28:17]!=12'd4095&&ifft_out_q_d1[28:17]!=12'd0) begin
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd1;
|
||||
SC_FDE_doutq <= (ifft_out_q_d1[28])? 10'b100000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
else begin
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||||
SC_FDE_doutq <= ifft_out_q_d1[17:8];
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
nd_SC_FDE_dout <= 1'd0;
|
||||
SC_FDE_douti <= 10'd0;
|
||||
SC_FDE_doutq <= 10'd0;
|
||||
flagoverflow_FDE_dataout_29to10i <= 1'd0;
|
||||
flagoverflow_FDE_dataout_29to10q <= 1'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//------------------------------------------------------仿真文件保存---------------------------------------------------//
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
// integer handle05;
|
||||
// integer handle06;
|
||||
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
|
||||
// handle01=$fopen("mulin_ai.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("mulin_aq.txt","w"); $fclose(handle02);
|
||||
// handle03=$fopen("mulin_bi.txt","w"); $fclose(handle03);
|
||||
// handle04=$fopen("mulin_bq.txt","w"); $fclose(handle04);
|
||||
// handle05=$fopen("mulout_datai.txt","w"); $fclose(handle05);
|
||||
// handle06=$fopen("mulout_dataq.txt","w"); $fclose(handle06);
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
|
||||
// if(mulin_nd)begin
|
||||
// handle01=$fopen("mulin_ai.txt","a+");$fwrite(handle01,"%d\n",$signed(mulin_ai));$fclose(handle01);
|
||||
// handle02=$fopen("mulin_aq.txt","a+");$fwrite(handle02,"%d\n",$signed(mulin_aq));$fclose(handle02);
|
||||
// handle03=$fopen("mulin_bi.txt","a+");$fwrite(handle03,"%d\n",$signed(mulin_bi));$fclose(handle03);
|
||||
// handle04=$fopen("mulin_bq.txt","a+");$fwrite(handle04,"%d\n",$signed(mulin_bq));$fclose(handle04);
|
||||
// end
|
||||
// if(mulout_nd)begin
|
||||
// handle05=$fopen("mulout_datai.txt","a+");$fwrite(handle05,"%d\n",$signed(mulout_datai));$fclose(handle05);
|
||||
// handle06=$fopen("mulout_dataq.txt","a+");$fwrite(handle06,"%d\n",$signed(mulout_dataq));$fclose(handle06);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+542
@@ -0,0 +1,542 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/12/19 16:14:42
|
||||
// Design Name:
|
||||
// Module Name: data_ow
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module data_ow(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input flag_ow_left,
|
||||
input nd,
|
||||
input [9:0] dini,
|
||||
input [9:0] dinq,
|
||||
|
||||
//数据的fifo，4个
|
||||
output reg [9:0] din_data1i = 10'd0,
|
||||
output reg [9:0] din_data1q = 10'd0,
|
||||
output reg wr_en_data1 = 1'd0,
|
||||
output reg [9:0] din_data2i = 10'd0,
|
||||
output reg [9:0] din_data2q = 10'd0,
|
||||
output reg wr_en_data2 = 1'd0,
|
||||
output reg flag_dataow = 1'd0, //拉高1clk，说明一段数据ow存储完毕，后端可开始连续读取
|
||||
|
||||
//正负导频段的加减结果
|
||||
output reg nd_pilot2 = 1'd0,
|
||||
output reg [9:0] pilot_datai = 10'd0,
|
||||
output reg [9:0] pilot_dataq = 10'd0,
|
||||
output reg [9:0] pilot_noisei = 10'd0,
|
||||
output reg [9:0] pilot_noiseq = 10'd0
|
||||
);
|
||||
|
||||
//导频的fifo，4个
|
||||
reg [9:0] din_pilot1i = 10'd0;
|
||||
reg wr_en_pilot1 = 1'd0;
|
||||
reg rd_en_pilot = 1'd0;
|
||||
wire [9:0] dout_pilot1i;
|
||||
wire full_pilot1i;
|
||||
wire empty_pilot1i;
|
||||
fifo_ow256 fifo_pilot_ow1i (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk (clk), // input wire wr_clk
|
||||
.rd_clk (clk), // input wire rd_clk
|
||||
.din (din_pilot1i), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_pilot1), // input wire wr_en
|
||||
.rd_en (rd_en_pilot), // input wire rd_en
|
||||
.dout (dout_pilot1i), // output wire [9 : 0] dout
|
||||
.full (full_pilot1i), // output wire full
|
||||
.empty (empty_pilot1i) // output wire empty
|
||||
);
|
||||
|
||||
reg [9:0] din_pilot1q = 10'd0;
|
||||
// reg wr_en_pilot1q = 1'd0;
|
||||
// reg rd_en_pilot1q = 1'd0;
|
||||
wire [9:0] dout_pilot1q;
|
||||
wire full_pilot1q;
|
||||
wire empty_pilot1q;
|
||||
fifo_ow256 fifo_pilot_ow1q (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk (clk), // input wire wr_clk
|
||||
.rd_clk (clk), // input wire rd_clk
|
||||
.din (din_pilot1q), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_pilot1), // input wire wr_en
|
||||
.rd_en (rd_en_pilot), // input wire rd_en
|
||||
.dout (dout_pilot1q), // output wire [9 : 0] dout
|
||||
.full (full_pilot1q), // output wire full
|
||||
.empty (empty_pilot1q) // output wire empty
|
||||
);
|
||||
|
||||
reg [9:0] din_pilot2i = 10'd0;
|
||||
reg wr_en_pilot2 = 1'd0;
|
||||
// reg rd_en_pilot2 = 1'd0;
|
||||
wire [9:0] dout_pilot2i;
|
||||
wire full_pilot2i;
|
||||
wire empty_pilot2i;
|
||||
fifo_ow256 fifo_pilot_ow2i (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk (clk), // input wire wr_clk
|
||||
.rd_clk (clk), // input wire rd_clk
|
||||
.din (din_pilot2i), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_pilot2), // input wire wr_en
|
||||
.rd_en (rd_en_pilot), // input wire rd_en
|
||||
.dout (dout_pilot2i), // output wire [9 : 0] dout
|
||||
.full (full_pilot2i), // output wire full
|
||||
.empty (empty_pilot2i) // output wire empty
|
||||
);
|
||||
|
||||
reg [9:0] din_pilot2q = 10'd0;
|
||||
// reg wr_en_pilot2q = 1'd0;
|
||||
// reg rd_en_pilot2q = 1'd0;
|
||||
wire [9:0] dout_pilot2q;
|
||||
wire full_pilot2q;
|
||||
wire empty_pilot2q;
|
||||
fifo_ow256 fifo_pilot_ow2q (
|
||||
.rst (rst), // input wire rst
|
||||
.wr_clk (clk), // input wire wr_clk
|
||||
.rd_clk (clk), // input wire rd_clk
|
||||
.din (din_pilot2q), // input wire [9 : 0] din
|
||||
.wr_en (wr_en_pilot2), // input wire wr_en
|
||||
.rd_en (rd_en_pilot), // input wire rd_en
|
||||
.dout (dout_pilot2q), // output wire [9 : 0] dout
|
||||
.full (full_pilot2q), // output wire full
|
||||
.empty (empty_pilot2q) // output wire empty
|
||||
);
|
||||
|
||||
|
||||
reg [4:0] state_ow = 5'd0;
|
||||
reg [7:0] cnt_256 = 8'd0;
|
||||
reg [0:0] flag_pilot = 1'd0;
|
||||
reg [3:0] cnt_10data = 1'd0;
|
||||
reg [5:0] cnt_42block = 6'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
state_ow <= 5'd0;
|
||||
cnt_256 <= 8'd0;
|
||||
flag_pilot <= 1'd0;
|
||||
flag_dataow <= 1'd0;
|
||||
cnt_10data <= 4'd0;
|
||||
cnt_42block <= 6'd0;
|
||||
|
||||
din_pilot1i <= 10'd0;
|
||||
din_pilot1q <= 10'd0;
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
din_pilot2i <= 10'd0;
|
||||
din_pilot2q <= 10'd0;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
din_data1i <= 10'd0;
|
||||
din_data1q <= 10'd0;
|
||||
wr_en_data1 <= 1'd0;
|
||||
din_data2i <= 10'd0;
|
||||
din_data2q <= 10'd0;
|
||||
wr_en_data2 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_ow)
|
||||
//等待帧同步指示。flag_ow_left与正导频段OW的左边界对齐。（要求flag_ow_left为高时nd也需有效）
|
||||
5'd0:begin
|
||||
if(flag_ow_left) begin
|
||||
din_pilot1i <= dini;
|
||||
din_pilot1q <= dinq;
|
||||
wr_en_pilot1 <= 1'd1;
|
||||
din_pilot2i <= din_pilot2i;
|
||||
din_pilot2q <= din_pilot2q;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
state_ow <= state_ow + 5'd1;
|
||||
end
|
||||
else begin
|
||||
din_pilot1i <= din_pilot1i;
|
||||
din_pilot1q <= din_pilot1q;
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
din_pilot2i <= din_pilot2i;
|
||||
din_pilot2q <= din_pilot2q;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
cnt_256 <= 8'd0;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
din_data1i <= din_data1i;
|
||||
din_data1q <= din_data1q;
|
||||
wr_en_data1 <= 1'd0;
|
||||
din_data2i <= din_data2i;
|
||||
din_data2q <= din_data2q;
|
||||
wr_en_data2 <= 1'd0;
|
||||
flag_pilot <= 1'd0;
|
||||
cnt_10data <= 4'd0;
|
||||
cnt_42block <= 6'd0;
|
||||
end
|
||||
|
||||
//等待正导频头全部存储完毕，256个nd
|
||||
5'd1:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd255) state_ow <= state_ow + 5'd1;
|
||||
else state_ow <= state_ow;
|
||||
din_pilot1i <= dini;
|
||||
din_pilot1q <= dinq;
|
||||
wr_en_pilot1 <= 1'd1;
|
||||
din_pilot2i <= din_pilot2i;
|
||||
din_pilot2q <= din_pilot2q;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
end
|
||||
else begin
|
||||
din_pilot1i <= din_pilot1i;
|
||||
din_pilot1q <= din_pilot1q;
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
din_pilot2i <= din_pilot2i;
|
||||
din_pilot2q <= din_pilot2q;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
flag_pilot <= 1'd0;
|
||||
cnt_10data <= 4'd0;
|
||||
cnt_42block <= cnt_42block;
|
||||
end
|
||||
|
||||
//计数数过32cp间隔
|
||||
5'd2:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd31) begin
|
||||
cnt_256 <= 8'd0;
|
||||
state_ow <= state_ow + 5'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
wr_en_data1 <= 1'd0;
|
||||
wr_en_data2 <= 1'd0;
|
||||
end
|
||||
|
||||
//存储第二段导频头（负导频头），长度256。导频缓存全部结束，给出flag_pilot,指示另一状态机：信道估计可以开始
|
||||
5'd3:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd255) begin
|
||||
flag_pilot <= 1'd1;
|
||||
state_ow <= state_ow + 5'd1;
|
||||
end
|
||||
else begin
|
||||
flag_pilot <= 1'd0;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
din_pilot1i <= din_pilot1i;
|
||||
din_pilot1q <= din_pilot1q;
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
din_pilot2i <= dini;
|
||||
din_pilot2q <= dinq;
|
||||
wr_en_pilot2 <= 1'd1;
|
||||
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
end
|
||||
else begin
|
||||
din_pilot1i <= din_pilot1i;
|
||||
din_pilot1q <= din_pilot1q;
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
din_pilot2i <= din_pilot2i;
|
||||
din_pilot2q <= din_pilot2q;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
|
||||
flag_pilot <= 1'd0;
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
end
|
||||
|
||||
//计数数过32cp间隔
|
||||
5'd4:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd31) begin
|
||||
cnt_10data <= cnt_10data + 4'd1; //cnt_10data代表接下来要存储的数据段为第几段（从1到10计数）
|
||||
cnt_256 <= 8'd0;
|
||||
state_ow <= state_ow + 5'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_10data <= cnt_10data;
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_10data <= cnt_10data;
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
wr_en_data1 <= 1'd0;
|
||||
wr_en_data2 <= 1'd0;
|
||||
flag_pilot <= 1'd0;
|
||||
flag_dataow <= 1'd0;
|
||||
end
|
||||
|
||||
//存储数据段，长度256
|
||||
5'd5:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd255) state_ow <= state_ow + 5'd1;
|
||||
else state_ow <= state_ow;
|
||||
if(cnt_10data[0]==1'd1) begin
|
||||
din_data1i <= dini;
|
||||
din_data1q <= dinq;
|
||||
wr_en_data1 <= 1'd1;
|
||||
din_data2i <= din_data2i;
|
||||
din_data2q <= din_data2q;
|
||||
wr_en_data2 <= 1'd0;
|
||||
end
|
||||
else begin
|
||||
din_data1i <= din_data1i;
|
||||
din_data1q <= din_data1q;
|
||||
wr_en_data1 <= 1'd0;
|
||||
din_data2i <= dini;
|
||||
din_data2q <= dinq;
|
||||
wr_en_data2 <= 1'd1;
|
||||
end
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
end
|
||||
else begin
|
||||
din_data1i <= din_data1i;
|
||||
din_data1q <= din_data1q;
|
||||
wr_en_data1 <= 1'd0;
|
||||
din_data2i <= din_data2i;
|
||||
din_data2q <= din_data2q;
|
||||
wr_en_data2 <= 1'd0;
|
||||
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
end
|
||||
|
||||
//数据段最后一个nd的下一clk，此刻一定没有nd。利用这一时钟判断是否为数据段内最后一段256数据
|
||||
//同时利用这一时段给出flag_dataow，标志一段数据段ow存储完毕，后端可开始连续读取
|
||||
5'd6:begin
|
||||
if(cnt_10data==4'd10) begin //第10个256,当前数据段结束
|
||||
if(cnt_42block==6'd41) begin //42个数据段，当前帧结束，转至末尾状态31等待帧间复位即可
|
||||
cnt_42block <= 6'd0;
|
||||
state_ow <= 5'd31;
|
||||
end
|
||||
else begin
|
||||
cnt_42block <= cnt_42block + 6'd1;
|
||||
state_ow <= state_ow + 5'd1;
|
||||
end
|
||||
cnt_10data <= 4'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_10data <= cnt_10data;
|
||||
cnt_42block <= cnt_42block;
|
||||
state_ow <= 5'd4;
|
||||
end
|
||||
wr_en_data1 <= 1'd0;
|
||||
wr_en_data2 <= 1'd0;
|
||||
flag_dataow <= 1'd1;
|
||||
end
|
||||
|
||||
//计数数过32cp间隔，之后来到正导频头缓存状态
|
||||
5'd7:begin
|
||||
if(nd) begin
|
||||
if(cnt_256==8'd31) begin
|
||||
cnt_10data <= cnt_10data; //cnt_10data代表接下来要存储的数据段为第几段（从1到10计数）
|
||||
cnt_256 <= 8'd0;
|
||||
state_ow <= 5'd1;
|
||||
end
|
||||
else begin
|
||||
cnt_10data <= cnt_10data;
|
||||
cnt_256 <= cnt_256 + 8'd1;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_10data <= cnt_10data;
|
||||
cnt_256 <= cnt_256;
|
||||
state_ow <= state_ow;
|
||||
end
|
||||
wr_en_pilot1 <= 1'd0;
|
||||
wr_en_pilot2 <= 1'd0;
|
||||
wr_en_data1 <= 1'd0;
|
||||
wr_en_data2 <= 1'd0;
|
||||
flag_pilot <= 1'd0;
|
||||
flag_dataow <= 1'd0;
|
||||
end
|
||||
|
||||
//一帧结束，等待复位
|
||||
5'd31:begin
|
||||
state_ow <= 5'd31;
|
||||
flag_pilot <= 1'd0;
|
||||
flag_dataow <= 1'd0;
|
||||
end
|
||||
|
||||
default:state_ow<= 5'd31;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
reg [2:0] state_pilot = 3'd0;
|
||||
reg [7:0] cnt_256pilot = 8'd0;
|
||||
reg [0:0] nd_pilot = 1'd0;
|
||||
reg [10:0] pilot_sumi = 11'd0;
|
||||
reg [10:0] pilot_sumq = 11'd0;
|
||||
reg [10:0] pilot_diffi = 11'd0;
|
||||
reg [10:0] pilot_diffq = 11'd0;
|
||||
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
state_pilot <= 3'd0;
|
||||
cnt_256pilot <= 8'd0;
|
||||
rd_en_pilot <= 1'd0;
|
||||
nd_pilot <= 1'd0;
|
||||
pilot_sumi <= 11'd0;
|
||||
pilot_sumq <= 11'd0;
|
||||
pilot_diffi <= 11'd0;
|
||||
pilot_diffq <= 11'd0;
|
||||
end
|
||||
else begin
|
||||
case(state_pilot)
|
||||
//等待flag_pilot指示。说明两段导频缓存完毕
|
||||
3'd0:begin
|
||||
if(flag_pilot) begin
|
||||
nd_pilot <= 1'd0;
|
||||
rd_en_pilot <= 1'd1;
|
||||
pilot_sumi <= pilot_sumi;
|
||||
pilot_sumq <= pilot_sumq;
|
||||
pilot_diffi <= pilot_diffi;
|
||||
pilot_diffq <= pilot_diffq;
|
||||
cnt_256pilot <= 8'd0;
|
||||
state_pilot <= state_pilot + 3'd1;
|
||||
end
|
||||
else begin
|
||||
nd_pilot <= 1'd0;
|
||||
rd_en_pilot <= 1'd0;
|
||||
pilot_sumi <= pilot_sumi;
|
||||
pilot_sumq <= pilot_sumq;
|
||||
pilot_diffi <= pilot_diffi;
|
||||
pilot_diffq <= pilot_diffq;
|
||||
cnt_256pilot <= 8'd0;
|
||||
state_pilot <= state_pilot;
|
||||
end
|
||||
end
|
||||
|
||||
//从rd_en_pilot为1的第一个clk开始，输出第0组数据。rd_en_pilot保持有效共需256clk，即最后一个clk的数据出到出口时仍需一个读nd（用读空fifo）
|
||||
3'd1:begin
|
||||
if(cnt_256pilot==8'd254) begin
|
||||
nd_pilot <= 1'd1;
|
||||
rd_en_pilot <= 1'd1;
|
||||
pilot_sumi <= {dout_pilot1i[9],dout_pilot1i} + {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_sumq <= {dout_pilot1q[9],dout_pilot1q} + {dout_pilot2q[9],dout_pilot2q};
|
||||
pilot_diffi <= {dout_pilot1i[9],dout_pilot1i} - {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_diffq <= {dout_pilot1q[9],dout_pilot1q} - {dout_pilot2q[9],dout_pilot2q};
|
||||
cnt_256pilot <= 8'd0;
|
||||
state_pilot <= state_pilot + 3'd1;
|
||||
end
|
||||
else begin
|
||||
nd_pilot <= 1'd1;
|
||||
rd_en_pilot <= 1'd1;
|
||||
pilot_sumi <= {dout_pilot1i[9],dout_pilot1i} + {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_sumq <= {dout_pilot1q[9],dout_pilot1q} + {dout_pilot2q[9],dout_pilot2q};
|
||||
pilot_diffi <= {dout_pilot1i[9],dout_pilot1i} - {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_diffq <= {dout_pilot1q[9],dout_pilot1q} - {dout_pilot2q[9],dout_pilot2q};
|
||||
cnt_256pilot <= cnt_256pilot + 8'd1;
|
||||
state_pilot <= state_pilot;
|
||||
end
|
||||
end
|
||||
|
||||
//最后一个数据：第255读完后转回0状态等待下一个数据段的导频。
|
||||
3'd2:begin
|
||||
nd_pilot <= 1'd1;
|
||||
rd_en_pilot <= 1'd0;
|
||||
pilot_sumi <= {dout_pilot1i[9],dout_pilot1i} + {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_sumq <= {dout_pilot1q[9],dout_pilot1q} + {dout_pilot2q[9],dout_pilot2q};
|
||||
pilot_diffi <= {dout_pilot1i[9],dout_pilot1i} - {dout_pilot2i[9],dout_pilot2i};
|
||||
pilot_diffq <= {dout_pilot1q[9],dout_pilot1q} - {dout_pilot2q[9],dout_pilot2q};
|
||||
cnt_256pilot <= 8'd0;
|
||||
state_pilot <= 3'd0;
|
||||
end
|
||||
|
||||
default:state_pilot <= 3'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//正负导频段的加减结果
|
||||
always @(posedge clk)begin
|
||||
if(rst)begin
|
||||
nd_pilot2 <= 1'd0;
|
||||
pilot_datai <= 10'd0;
|
||||
pilot_dataq <= 10'd0;
|
||||
pilot_noisei <= 10'd0;
|
||||
pilot_noiseq <= 10'd0;
|
||||
end
|
||||
else begin
|
||||
nd_pilot2 <= nd_pilot;
|
||||
pilot_noisei <= pilot_sumi[10:1];
|
||||
pilot_noiseq <= pilot_sumq[10:1];
|
||||
pilot_datai <= pilot_diffi[10:1];
|
||||
pilot_dataq <= pilot_diffq[10:1];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------写测试文件---------------------------------------------------------------------//
|
||||
// integer handle01;
|
||||
// integer handle02;
|
||||
// integer handle03;
|
||||
// integer handle04;
|
||||
|
||||
// reg enable1 = 0;
|
||||
// initial begin
|
||||
// handle01=$fopen("din_pilot1i.txt","w"); $fclose(handle01);
|
||||
// handle02=$fopen("din_pilot1q.txt","w"); $fclose(handle02);
|
||||
// handle03=$fopen("din_pilot2i.txt","w"); $fclose(handle03);
|
||||
// handle04=$fopen("din_pilot2q.txt","w"); $fclose(handle04);
|
||||
|
||||
|
||||
// #10;
|
||||
// enable1 = 1;
|
||||
// end
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(enable1)begin
|
||||
// if(wr_en_pilot1)begin
|
||||
// handle01=$fopen("din_pilot1i.txt","a+");$fwrite(handle01,"%d\n",$signed(din_pilot1i));$fclose(handle01);
|
||||
// handle02=$fopen("din_pilot1q.txt","a+");$fwrite(handle02,"%d\n",$signed(din_pilot1q));$fclose(handle02);
|
||||
// end
|
||||
// if(wr_en_pilot2)begin
|
||||
// handle03=$fopen("din_pilot2i.txt","a+");$fwrite(handle03,"%d\n",$signed(din_pilot2i));$fclose(handle03);
|
||||
// handle04=$fopen("din_pilot2q.txt","a+");$fwrite(handle04,"%d\n",$signed(din_pilot2q));$fclose(handle04);
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+18
-4
@@ -109,7 +109,7 @@ module enc_control #(
|
||||
|
||||
assign fifo_enc_out_dout_i = (fifo_enc_out_dout[0] == 1'b0) ? 16'h7FFF : 16'h8001;
|
||||
assign fifo_enc_out_dout_q = (fifo_enc_out_dout[1] == 1'b0) ? 16'h7FFF : 16'h8001;
|
||||
assign fifo_enc_out_dout_map = {fifo_enc_out_dout_q, fifo_enc_out_dout_i};
|
||||
assign fifo_enc_out_dout_map = {fifo_enc_out_dout_i, fifo_enc_out_dout_q};
|
||||
assign wc_data_in = s_axis_fifo_tdata;
|
||||
|
||||
// ******** Logic Block ********
|
||||
@@ -134,7 +134,7 @@ module enc_control #(
|
||||
// and the width convert fifo is empty
|
||||
// and the finally stage fifo is almost empty
|
||||
// TODO:check the conditions, done 2024年5月27日
|
||||
if (s_axis_fifo_tvalid && data_src_count != 0 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
|
||||
if (s_axis_fifo_tvalid && data_src_count >= 32 && fifo_enc_out_prog_empty && ~data_add_prefix_in_ready && ~data_add_prefix_out_valid) begin
|
||||
ns = S_START;
|
||||
end
|
||||
else begin
|
||||
@@ -297,8 +297,8 @@ module enc_control #(
|
||||
|
||||
add_prefix #(
|
||||
.WIDTH (2), // ! if this parameter is changed, make sure the shift IP inside is also changed
|
||||
.DATA_LEN (256),
|
||||
.PREFIX_LEN(8)
|
||||
.DATA_LEN (256), //! if the WIDTH or DATA_LEN parameter is changed, make sure the shift IP inside is also changed
|
||||
.PREFIX_LEN(32)
|
||||
) u_add_prefix (
|
||||
.clk (clk),
|
||||
.start (add_prefix_start),
|
||||
@@ -338,4 +338,18 @@ module enc_control #(
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
// ila_enc_control u_ila_enc_control (
|
||||
// .clk (clk),
|
||||
// .probe0(s_axis_fifo_tvalid), // width: 1
|
||||
// .probe1(s_axis_fifo_tready), // width: 1
|
||||
// .probe2(s_axis_fifo_tdata), // width: 32
|
||||
// .probe3(data_src_count), // width: 32
|
||||
// .probe4(cs), // width: 4
|
||||
// .probe5(wc_data_in_ready), // width: 1
|
||||
// .probe6(wc_data_in_valid), // width: 1
|
||||
// .probe7(wc_data_out_valid), // width: 1
|
||||
// .probe8(data_add_prefix_in_ready), // width: 1
|
||||
// .probe9(data_add_prefix_out_valid) // width: 1
|
||||
// );
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
module extract_mac_frame (
|
||||
input clk,
|
||||
input rst,
|
||||
// ldpc out
|
||||
input ldpc_dec_out_start,
|
||||
input ldpc_dec_out_valid,
|
||||
input ldpc_dec_out_data,
|
||||
// axis
|
||||
output wire m_axis_mac_frame_tvalid,
|
||||
output wire [31:0] m_axis_mac_frame_tdata,
|
||||
input m_axis_mac_frame_tready,
|
||||
output reg m_axis_mac_frame_tlast
|
||||
|
||||
);
|
||||
// NOTE: module 1bit --> 32bit
|
||||
// transfer 1bit serial to 32bit and sent to axis fifo
|
||||
//
|
||||
|
||||
localparam MAC_FRAME_LEN_BIT = 107520;
|
||||
localparam MAC_FRAME_LEN_BYTE = 13440;
|
||||
localparam MAC_FRAME_LEN_QUAD_BYTE = 3360;
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
reg [15:0] cnt_axis_out;
|
||||
wire flag_handshake;
|
||||
// serial input
|
||||
wire ser;
|
||||
wire ser_valid;
|
||||
wire [31:0] par;
|
||||
wire par_valid;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign ser = ldpc_dec_out_data;
|
||||
assign ser_valid = ldpc_dec_out_valid;
|
||||
assign m_axis_mac_frame_tvalid = par_valid;
|
||||
assign m_axis_mac_frame_tdata = par;
|
||||
|
||||
assign flag_handshake = m_axis_mac_frame_tvalid & m_axis_mac_frame_tready;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_axis_out <= 0;
|
||||
end
|
||||
else if (flag_handshake) begin
|
||||
cnt_axis_out <= cnt_axis_out + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (cnt_axis_out == MAC_FRAME_LEN_QUAD_BYTE - 1 && flag_handshake) begin
|
||||
m_axis_mac_frame_tlast = 1;
|
||||
end
|
||||
else begin
|
||||
m_axis_mac_frame_tlast = 0;
|
||||
end
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// serial 1bit --> 32bit
|
||||
ser2par u_ser2par (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.ser (ser),
|
||||
.ser_valid(ser_valid),
|
||||
.par (par),
|
||||
.par_valid(par_valid)
|
||||
);
|
||||
|
||||
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/12/23 17:06:52
|
||||
// Design Name:
|
||||
// Module Name: freqestm
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module freqestm (
|
||||
input clk,
|
||||
input rst,
|
||||
input framesync,
|
||||
input mgc_rdy,
|
||||
input [9:0] datain_i,
|
||||
input [9:0] datain_q,
|
||||
output reg [9:0] dataout_i,
|
||||
output reg [9:0] dataout_q,
|
||||
output reg framesync_delay,
|
||||
output reg data_save,
|
||||
output reg rst_freq
|
||||
);
|
||||
|
||||
wire [19:0] datain_01;
|
||||
wire [19:0] datain_02;
|
||||
wire [19:0] datain_03;
|
||||
wire framesync_d2;
|
||||
wire framesync_d3;
|
||||
|
||||
wire [19:0] dataout_16;
|
||||
|
||||
assign datain_01 = {datain_q, datain_i};
|
||||
|
||||
shiftram_freq shiftram_freq_01 (
|
||||
.CLK(clk),
|
||||
.D (datain_01),
|
||||
.Q (datain_02)
|
||||
);
|
||||
shiftram_freq shiftram_freq_02 (
|
||||
.CLK(clk),
|
||||
.D (datain_02),
|
||||
.Q (datain_03)
|
||||
);
|
||||
wire empty;
|
||||
wire full;
|
||||
reg rd_en;
|
||||
reg wr_en;
|
||||
|
||||
fifo_freq fifo_freq (
|
||||
.clk (clk),
|
||||
.srst (rst),
|
||||
.din (datain_03),
|
||||
.wr_en(wr_en),
|
||||
.full (full),
|
||||
.rd_en(rd_en),
|
||||
.empty(empty),
|
||||
.dout (dataout_16)
|
||||
|
||||
);
|
||||
reg [15:0] cnt_fifo;
|
||||
reg [ 2:0] state_fifo;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_fifo <= 16'd0;
|
||||
wr_en <= 1'b0;
|
||||
rd_en <= 1'b0;
|
||||
state_fifo <= 3'd0;
|
||||
end
|
||||
else begin
|
||||
case (state_fifo)
|
||||
3'd0: begin
|
||||
if (mgc_rdy) begin
|
||||
state_fifo <= 3'd1;
|
||||
end
|
||||
else begin
|
||||
state_fifo <= state_fifo;
|
||||
end
|
||||
end
|
||||
3'd1: begin
|
||||
if (cnt_fifo == 16'd2175) begin
|
||||
wr_en <= 1'b1;
|
||||
cnt_fifo <= cnt_fifo + 16'd1;
|
||||
end
|
||||
else if (cnt_fifo == 16'd18065) begin
|
||||
rd_en <= 1'b1;
|
||||
cnt_fifo <= cnt_fifo;
|
||||
end
|
||||
else begin
|
||||
cnt_fifo <= cnt_fifo + 16'd1;
|
||||
wr_en <= wr_en;
|
||||
rd_en <= rd_en;
|
||||
end
|
||||
state_fifo <= state_fifo;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [11:0] cnt_pilot;
|
||||
reg [14:0] cnt_frame;
|
||||
reg [ 7:0] cnt_bag;
|
||||
reg [11:0] cnt_cp;
|
||||
reg [11:0] cnt_process;
|
||||
reg [11:0] addra_pilot01;
|
||||
reg [11:0] addrb_pilot01;
|
||||
reg [11:0] addra_pilot02;
|
||||
reg [11:0] addrb_pilot02;
|
||||
reg [ 4:0] state_freq;
|
||||
|
||||
reg [19:0] din_pilot01;
|
||||
reg [19:0] din_pilot02;
|
||||
wire [19:0] dout_pilot01;
|
||||
wire [19:0] dout_pilot02;
|
||||
|
||||
reg framesync_delay_d1 = 1'b0;
|
||||
reg framesync_delay_d2 = 1'b0;
|
||||
reg framesync_delay_d3 = 1'b0;
|
||||
reg framesync_delay_d4 = 1'b0;
|
||||
reg framesync_delay_d5 = 1'b0;
|
||||
reg framesync_delay_d6 = 1'b0;
|
||||
reg framesync_delay_d7 = 1'b0;
|
||||
reg framesync_delay_d8 = 1'b0;
|
||||
reg framesync_delay_d9 = 1'b0;
|
||||
|
||||
|
||||
reg wea_01;
|
||||
reg wea_02;
|
||||
|
||||
ram_pilot ram_pilota (
|
||||
.clka (clk),
|
||||
.clkb (clk),
|
||||
.addra(addra_pilot01),
|
||||
.addrb(addrb_pilot01),
|
||||
.dina (din_pilot01),
|
||||
.doutb(dout_pilot01),
|
||||
.wea (wea_01)
|
||||
);
|
||||
|
||||
ram_pilot ram_pilotb (
|
||||
.clka (clk),
|
||||
.clkb (clk),
|
||||
.addra(addra_pilot02),
|
||||
.addrb(addrb_pilot02),
|
||||
.dina (din_pilot02),
|
||||
.doutb(dout_pilot02),
|
||||
.wea (wea_02)
|
||||
);
|
||||
|
||||
wire [ 2:0] Multouti01_head;
|
||||
wire [ 2:0] Multoutq01_head;
|
||||
wire [20:0] Multouti01;
|
||||
wire [20:0] Multoutq01;
|
||||
reg acc_rdy;
|
||||
|
||||
com_freq com_freq (
|
||||
.aclk (clk),
|
||||
.s_axis_a_tvalid (1'd1),
|
||||
.s_axis_a_tdata ({6'd0, dout_pilot01[19:10], 6'd0, dout_pilot01[9:0]}),
|
||||
.s_axis_b_tvalid (1'd1),
|
||||
.s_axis_b_tdata ({6'd0, dout_pilot02[19:10], 6'd0, dout_pilot02[9:0]}),
|
||||
.m_axis_dout_tvalid(m_axis_dout_tvalid01),
|
||||
.m_axis_dout_tdata ({Multoutq01_head, Multoutq01, Multouti01_head, Multouti01})
|
||||
);
|
||||
|
||||
|
||||
reg dfreq_word_nd_DDS;
|
||||
reg [31:0] acc_com_i;
|
||||
reg [31:0] acc_com_q;
|
||||
reg [ 9:0] phase_reg;
|
||||
reg [13:0] freq_out;
|
||||
wire [ 9:0] phase_out;
|
||||
wire [ 5:0] phase_out_head;
|
||||
wire phaserdy;
|
||||
reg [ 3:0] cnt_6;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
//dataout_i <= 12'd0;
|
||||
//dataout_q <= 12'd0;
|
||||
framesync_delay_d2 <= 1'b0;
|
||||
framesync_delay_d3 <= 1'b0;
|
||||
framesync_delay_d4 <= 1'b0;
|
||||
framesync_delay_d5 <= 1'b0;
|
||||
framesync_delay_d6 <= 1'b0;
|
||||
framesync_delay_d7 <= 1'b0;
|
||||
framesync_delay_d8 <= 1'b0;
|
||||
framesync_delay <= 1'b0;
|
||||
state_freq <= 5'd0;
|
||||
framesync_delay_d1 <= 1'b0;
|
||||
cnt_bag <= 8'd0;
|
||||
acc_com_i <= 32'd0;
|
||||
acc_com_q <= 32'd0;
|
||||
phase_reg <= 10'd0;
|
||||
freq_out <= 14'd0;
|
||||
cnt_pilot <= 12'd0;
|
||||
cnt_frame <= 15'd0;
|
||||
cnt_process <= 12'd0;
|
||||
addra_pilot01 <= 12'd0;
|
||||
addra_pilot02 <= 12'd0;
|
||||
addrb_pilot01 <= 12'd0;
|
||||
addrb_pilot02 <= 12'd0;
|
||||
din_pilot01 <= 20'd0;
|
||||
din_pilot02 <= 20'd0;
|
||||
cnt_cp <= 12'd0;
|
||||
wea_01 <= 1'b0;
|
||||
wea_02 <= 1'b0;
|
||||
acc_rdy <= 1'b0;
|
||||
data_save <= 1'b0;
|
||||
dfreq_word_nd_DDS <= 1'b0;
|
||||
cnt_6 <= 4'd0;
|
||||
end
|
||||
else begin
|
||||
framesync_delay_d2 <= data_save;
|
||||
framesync_delay_d3 <= framesync_delay_d2;
|
||||
framesync_delay_d4 <= framesync_delay_d3;
|
||||
framesync_delay_d5 <= framesync_delay_d4;
|
||||
framesync_delay_d6 <= framesync_delay_d5;
|
||||
framesync_delay_d7 <= framesync_delay_d6;
|
||||
framesync_delay_d8 <= framesync_delay_d7;
|
||||
framesync_delay <= framesync_delay_d8;
|
||||
case (state_freq)
|
||||
5'd0: begin
|
||||
if (framesync) begin
|
||||
state_freq <= 5'd1;
|
||||
wea_01 <= 1'b1;
|
||||
if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -datain_q;
|
||||
|
||||
din_pilot01[9:0] <= datain_i[9:0];
|
||||
end
|
||||
else begin
|
||||
state_freq <= 5'd0;
|
||||
end
|
||||
//dataout_i <= 12'd0;
|
||||
//dataout_q <= 12'd0;
|
||||
framesync_delay_d1 <= 1'b0;
|
||||
cnt_bag <= 8'd0;
|
||||
acc_com_i <= 32'd0;
|
||||
acc_com_q <= 32'd0;
|
||||
phase_reg <= 10'd0;
|
||||
freq_out <= 14'd0;
|
||||
cnt_pilot <= 12'd0;
|
||||
cnt_frame <= 15'd0;
|
||||
cnt_process <= 12'd0;
|
||||
addra_pilot01 <= 12'd0;
|
||||
addra_pilot02 <= 12'd0;
|
||||
addrb_pilot01 <= 12'd0;
|
||||
addrb_pilot02 <= 12'd0;
|
||||
din_pilot01 <= 20'd0;
|
||||
din_pilot02 <= 20'd0;
|
||||
cnt_cp <= 12'd0;
|
||||
wea_01 <= 1'b0;
|
||||
wea_02 <= 1'b0;
|
||||
acc_rdy <= 1'b0;
|
||||
dfreq_word_nd_DDS <= 1'b0;
|
||||
end
|
||||
|
||||
5'd1: begin
|
||||
if (cnt_pilot == 12'd1023) begin
|
||||
addra_pilot01 <= addra_pilot01;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 5'd11;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
|
||||
wea_01 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -datain_q;
|
||||
|
||||
din_pilot01[9:0] <= datain_i[9:0];
|
||||
addra_pilot01 <= addra_pilot01 + 12'd1;
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_01 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd2: begin
|
||||
if (cnt_frame == 15'd13823) begin
|
||||
state_freq <= 5'd3;
|
||||
cnt_frame <= 15'd0;
|
||||
wea_02 <= 1'b1;
|
||||
din_pilot02 <= {datain_q, datain_i};
|
||||
end
|
||||
else begin
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd3: begin
|
||||
if (cnt_pilot == 12'd1023) begin
|
||||
addra_pilot02 <= addra_pilot02;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 5'd13;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag + 8'd1;
|
||||
wea_02 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
din_pilot02 <= {datain_q, datain_i};
|
||||
addra_pilot02 <= addra_pilot02 + 12'd1;
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_02 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd4: begin
|
||||
state_freq <= 5'd5;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
acc_com_i <= 32'd0;
|
||||
acc_com_q <= 32'd0;
|
||||
end
|
||||
|
||||
5'd5: begin
|
||||
if (cnt_6 == 4'd6) begin
|
||||
if (Multouti01[20] == 1'b1) acc_com_i <= acc_com_i + {11'b11111111111, Multouti01};
|
||||
else acc_com_i <= acc_com_i + {11'b00000000000, Multouti01};
|
||||
if (Multoutq01[20] == 1'b1) acc_com_q <= acc_com_q + {11'b11111111111, Multoutq01};
|
||||
else acc_com_q <= acc_com_q + {11'b00000000000, Multoutq01};
|
||||
cnt_6 <= cnt_6;
|
||||
end
|
||||
else begin
|
||||
acc_com_q <= acc_com_q;
|
||||
acc_com_i <= acc_com_i;
|
||||
cnt_6 <= cnt_6 + 4'd1;
|
||||
end
|
||||
if (cnt_pilot >= 12'd2047) begin
|
||||
addrb_pilot01 <= 12'd0;
|
||||
addrb_pilot02 <= 12'd0;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
if (cnt_pilot == 12'd2053) begin
|
||||
acc_rdy <= 1'b1;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 5'd6;
|
||||
cnt_6 <= 4'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
addrb_pilot01 <= addrb_pilot01 + 12'd1;
|
||||
addrb_pilot02 <= addrb_pilot02 + 12'd1;
|
||||
acc_rdy <= 1'b0;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd6: begin
|
||||
acc_rdy <= 1'b0;
|
||||
if (phaserdy) begin
|
||||
phase_reg <= phase_out;
|
||||
state_freq <= 5'd7;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
wea_01 <= 1'b1;
|
||||
|
||||
if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -dout_pilot02[19:10];
|
||||
din_pilot01[9:0] <= dout_pilot02[9:0];
|
||||
|
||||
addrb_pilot02 <= addrb_pilot02 + 12'd1;
|
||||
end
|
||||
else begin
|
||||
phase_reg <= phase_reg;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd7: begin
|
||||
state_freq <= 5'd8;
|
||||
data_save <= 1'b1;
|
||||
|
||||
if (phase_reg[9] == 1'b1) freq_out <= {3'b111, phase_reg, 1'b0} + {4'b1111, phase_reg};
|
||||
else freq_out <= {3'b000, phase_reg, 1'b0} + {4'b0000, phase_reg};
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
dfreq_word_nd_DDS <= 1'b1;
|
||||
if (cnt_bag == 8'd1) framesync_delay_d1 <= 1'b1;
|
||||
else framesync_delay_d1 <= 1'b0;
|
||||
|
||||
wea_01 <= 1'b1;
|
||||
|
||||
if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -dout_pilot02[19:10];
|
||||
din_pilot01[9:0] <= dout_pilot02[9:0];
|
||||
|
||||
addrb_pilot02 <= addrb_pilot02 + 12'd1;
|
||||
end
|
||||
|
||||
5'd8: begin
|
||||
dfreq_word_nd_DDS <= 1'b0;
|
||||
framesync_delay_d1 <= 1'b0;
|
||||
if (cnt_pilot >= 12'd2045) begin
|
||||
|
||||
addrb_pilot02 <= 12'd0;
|
||||
if (cnt_pilot == 12'd2047) begin
|
||||
addra_pilot01 <= 12'd0;
|
||||
addrb_pilot02 <= 12'd0;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 5'd9;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
wea_01 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -dout_pilot02[19:10];
|
||||
din_pilot01[9:0] <= dout_pilot02[9:0];
|
||||
|
||||
addra_pilot01 <= addra_pilot01 + 12'd1;
|
||||
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
wea_01 <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (dout_pilot02[19:10] == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -dout_pilot02[19:10];
|
||||
din_pilot01[9:0] <= dout_pilot02[9:0];
|
||||
|
||||
addra_pilot01 <= addra_pilot01 + 12'd1;
|
||||
addrb_pilot02 <= addrb_pilot02 + 12'd1;
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
wea_01 <= 1'b1;
|
||||
end
|
||||
end
|
||||
5'd9: begin
|
||||
if (cnt_frame == 15'd13823) begin
|
||||
|
||||
if (cnt_bag == 8'd40) begin
|
||||
state_freq <= 5'd10;
|
||||
cnt_bag <= cnt_bag + 8'd1;
|
||||
end
|
||||
else begin
|
||||
state_freq <= 5'd3;
|
||||
wea_02 <= 1'b1;
|
||||
din_pilot02 <= {datain_q, datain_i};
|
||||
|
||||
end
|
||||
|
||||
cnt_frame <= 15'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd10: begin
|
||||
if (cnt_frame == 15'd13695) begin
|
||||
cnt_frame <= 15'd0;
|
||||
state_freq <= 5'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
5'd11: begin
|
||||
if (cnt_cp == 12'd127) begin
|
||||
state_freq <= 5'd12;
|
||||
cnt_cp <= 12'd0;
|
||||
wea_01 <= 1'b1;
|
||||
addra_pilot01 <= addra_pilot01 + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -datain_q;
|
||||
|
||||
din_pilot01[9:0] <= datain_i[9:0];
|
||||
end
|
||||
else begin
|
||||
cnt_cp <= cnt_cp + 12'd1;
|
||||
state_freq <= state_freq;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
5'd12: begin
|
||||
if (cnt_pilot == 12'd1023) begin
|
||||
addra_pilot01 <= 12'd0;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 12'd2;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_01 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (datain_q == 10'd512) din_pilot01[19:10] <= 10'd511;
|
||||
else din_pilot01[19:10] <= -datain_q;
|
||||
|
||||
din_pilot01[9:0] <= datain_i[9:0];
|
||||
addra_pilot01 <= addra_pilot01 + 12'd1;
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_01 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
5'd13: begin
|
||||
if (cnt_cp == 12'd127) begin
|
||||
state_freq <= 5'd14;
|
||||
cnt_cp <= 12'd0;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
din_pilot02 <= {datain_q, datain_i};
|
||||
addra_pilot02 <= addra_pilot02 + 12'd1;
|
||||
wea_02 <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_cp <= cnt_cp + 12'd1;
|
||||
state_freq <= state_freq;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
5'd14: begin
|
||||
if (cnt_pilot == 12'd1023) begin
|
||||
addra_pilot02 <= 12'd0;
|
||||
cnt_pilot <= 12'd0;
|
||||
state_freq <= 5'd4;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_02 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
din_pilot02 <= {datain_q, datain_i};
|
||||
addra_pilot02 <= addra_pilot02 + 12'd1;
|
||||
cnt_pilot <= cnt_pilot + 12'd1;
|
||||
cnt_frame <= cnt_frame + 15'd1;
|
||||
cnt_bag <= cnt_bag;
|
||||
wea_02 <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
atan2_freq atan2_freq (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_cartesian_tvalid(acc_rdy), // input wire s_axis_cartesian_tvalid
|
||||
.s_axis_cartesian_tdata ({acc_com_q, acc_com_i}), // input wire [47 : 0] s_axis_cartesian_tdata
|
||||
.m_axis_dout_tvalid (phaserdy), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata ({phase_out_head, phase_out}) // output wire [15 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
wire [11:0] DDS_trunc_i;
|
||||
wire [11:0] DDS_trunc_q;
|
||||
wire DDS_trunc_nd;
|
||||
wire Demod_ovrflw;
|
||||
|
||||
|
||||
|
||||
reg [11:0] DDSin_i;
|
||||
reg [11:0] DDSin_q;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (dataout_16[19] == 1'b1) DDSin_q <= {2'b11, dataout_16[19:10]};
|
||||
else DDSin_q <= {2'b00, dataout_16[19:10]};
|
||||
if (dataout_16[9] == 1'b1) DDSin_i <= {2'b11, dataout_16[9:0]};
|
||||
else DDSin_i <= {2'b00, dataout_16[9:0]};
|
||||
end
|
||||
|
||||
|
||||
DDS_compensate DDS_compensate_mx (
|
||||
.clk (clk),
|
||||
.rst (rst), //捕获模块复位受到发端影响，测试捕获情冿
|
||||
.din_nd (1'd1),
|
||||
.din_i (DDSin_i),
|
||||
.din_q (DDSin_q),
|
||||
.acq_nd (1'b0), // 捕获信息 //捕获到了复位丿欿
|
||||
.dfreq_word_nd (dfreq_word_nd_DDS), // 频偏NCO信息
|
||||
.dfreq_word (freq_out),
|
||||
.framesync_success(framesync), // 帧同步标志，用于切码
|
||||
.demod_trunc_i (DDS_trunc_i),
|
||||
.demod_trunc_q (DDS_trunc_q),
|
||||
.demod_trunc_nd (DDS_trunc_nd),
|
||||
.Demod_ovrflw (Demod_ovrflw)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (DDS_trunc_i[11:9] == 3'b000 || DDS_trunc_i[11:9] == 3'b111) begin
|
||||
dataout_i <= DDS_trunc_i[9:0];
|
||||
end
|
||||
else begin
|
||||
dataout_i <= (DDS_trunc_i[11] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
if (DDS_trunc_q[11:9] == 3'b000 || DDS_trunc_q[11:9] == 3'b111) begin
|
||||
dataout_q <= DDS_trunc_q[9:0];
|
||||
end
|
||||
else begin
|
||||
dataout_q <= (DDS_trunc_q[11] == 1'b1) ? 10'b10_0000_0000 : 10'b01_1111_1111;
|
||||
end
|
||||
end
|
||||
|
||||
reg [19:0] cnt_rst = 20'd0;
|
||||
always @(posedge clk) begin
|
||||
if (framesync_delay_d8 && !framesync_delay) begin
|
||||
cnt_rst <= 20'd0;
|
||||
rst_freq <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_rst == 20'd580620) begin
|
||||
rst_freq <= 1'b1;
|
||||
cnt_rst <= cnt_rst + 20'd1;
|
||||
end
|
||||
else if (cnt_rst == 20'd580621) begin
|
||||
rst_freq <= 1'b0;
|
||||
cnt_rst <= cnt_rst;
|
||||
end
|
||||
else begin
|
||||
cnt_rst <= cnt_rst + 20'd1;
|
||||
rst_freq <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
+417
@@ -0,0 +1,417 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module net_city (
|
||||
// basic
|
||||
input clk,
|
||||
input rst_initial,
|
||||
input rst_manual, //manual
|
||||
// tx signal
|
||||
output reg tx_start = 1'b0, // pulse
|
||||
output reg [63:0] trans_net_data = 64'd0,
|
||||
output reg flag_video_send = 1'b0,
|
||||
output reg [07:0] recv_id = 8'd0,
|
||||
// rx signal
|
||||
input frame_sync,
|
||||
// input recv_net_data_nd,
|
||||
// input [63:0] recv_net_data,
|
||||
// net parameter
|
||||
input [31:0] frame_sync_time,
|
||||
input [07:0] id_num,
|
||||
input [07:0] max_slot_num,
|
||||
input [07:0] video_id01,
|
||||
input [07:0] video_id02,
|
||||
input [07:0] video_id03,
|
||||
// net state
|
||||
output reg is_net = 1'b0,
|
||||
output reg flag_to_uc = 1'b0,
|
||||
// intr 2 ps
|
||||
output wire intr_ps,
|
||||
output reg rx_rst,
|
||||
input wire tx_done
|
||||
);
|
||||
//----------parameter----------
|
||||
localparam SLOT_TIME = 750000; // 15ms
|
||||
|
||||
//----------rst----------
|
||||
wire rst;
|
||||
assign rst = rst_initial || rst_manual;
|
||||
|
||||
//----------counter_1s----------
|
||||
reg [31:0] cnt_1s = 32'd0;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_1s <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_1s == 32'd49999999) begin
|
||||
cnt_1s <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_1s <= cnt_1s + 32'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//----------flag_tx----------
|
||||
|
||||
|
||||
//----------state_net----------
|
||||
reg [07:0] state_net = 8'd0;
|
||||
reg [31:0] cnt_trans_slot = 32'd0;
|
||||
reg [31:0] cnt_inter_slot = 32'd0;
|
||||
reg [07:0] cur_slot = 8'd0;
|
||||
reg [07:0] cnt_video_slot = 8'd0;
|
||||
reg [31:0] cnt_other = 32'd0;
|
||||
|
||||
reg [07:0] connect_node = 8'd0;
|
||||
reg [63:0] trans_net_data_reg = 64'd0;
|
||||
reg [07:0] recv_connect_node = 8'd0;
|
||||
reg [07:0] recv_video_id01 = 8'd0;
|
||||
reg [07:0] recv_video_id02 = 8'd0;
|
||||
reg [07:0] recv_video_id03 = 8'd0;
|
||||
|
||||
// if u dont understand this code blew, plz contact NanzZ 😊
|
||||
assign intr_ps = (cnt_trans_slot == SLOT_TIME - 50000) && ((id_num == 1 && (cur_slot == max_slot_num - 1)) || (id_num != 1 && (cur_slot == id_num - 8'd2)));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_rst <= 0;
|
||||
end
|
||||
else if (tx_start) begin
|
||||
rx_rst <= 1;
|
||||
end
|
||||
else if (tx_done) begin
|
||||
rx_rst <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_net <= 8'd0;
|
||||
cnt_trans_slot <= 32'd0;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
cnt_other <= 32'd0;
|
||||
recv_id <= 8'd0;
|
||||
recv_connect_node <= 8'd0;
|
||||
recv_video_id01 <= 8'd0;
|
||||
recv_video_id02 <= 8'd0;
|
||||
recv_video_id03 <= 8'd0;
|
||||
tx_start <= 1'b0;
|
||||
trans_net_data <= 64'd0;
|
||||
is_net <= 1'b0;
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case (state_net)
|
||||
8'd0: begin
|
||||
state_net <= 8'd1;
|
||||
cnt_trans_slot <= 32'd0;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
cnt_other <= 32'd0;
|
||||
recv_id <= recv_id;
|
||||
recv_connect_node <= 8'd0;
|
||||
recv_video_id01 <= recv_video_id01;
|
||||
recv_video_id02 <= recv_video_id02;
|
||||
recv_video_id03 <= recv_video_id03;
|
||||
tx_start <= 1'b0;
|
||||
trans_net_data <= 64'd0;
|
||||
is_net <= 1'b0;
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
8'd1: begin
|
||||
state_net <= 8'd2;
|
||||
end
|
||||
8'd2: begin
|
||||
if (frame_sync) begin
|
||||
state_net <= 8'd50;
|
||||
cnt_other <= 32'd0;
|
||||
cnt_trans_slot <= frame_sync_time;
|
||||
cnt_inter_slot <= cnt_trans_slot + 32'd1;
|
||||
end
|
||||
else if (cnt_other == 32'd49999999) begin
|
||||
cnt_other <= 32'd0;
|
||||
state_net <= 8'd100;
|
||||
is_net <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_other <= cnt_other + 32'd1;
|
||||
end
|
||||
end
|
||||
|
||||
8'd100: begin // _tx
|
||||
state_net <= 8'd101;
|
||||
tx_start <= 1'b1;
|
||||
trans_net_data <= trans_net_data_reg;
|
||||
cnt_trans_slot <= 32'd0;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
end
|
||||
8'd101: begin
|
||||
state_net <= 8'd200;
|
||||
tx_start <= 1'b0;
|
||||
cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
end
|
||||
|
||||
8'd200: begin // wait
|
||||
if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num == 1 && (cur_slot == max_slot_num - 1))) begin
|
||||
state_net <= 8'd100;
|
||||
cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
end
|
||||
else if ((cnt_trans_slot == SLOT_TIME - 2) && (id_num != 1 && (cur_slot == id_num - 8'd2))) begin
|
||||
state_net <= 8'd100;
|
||||
cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
end
|
||||
else if (frame_sync) begin
|
||||
state_net <= 8'd50;
|
||||
cnt_trans_slot <= frame_sync_time;
|
||||
cnt_inter_slot <= cnt_trans_slot + 32'd1;
|
||||
end
|
||||
else begin
|
||||
if (cnt_trans_slot == SLOT_TIME - 1) begin
|
||||
cnt_trans_slot <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
end
|
||||
cnt_inter_slot <= 32'd0;
|
||||
end
|
||||
|
||||
case (id_num)
|
||||
recv_video_id01: begin
|
||||
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd0) begin
|
||||
flag_video_send <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
recv_video_id02: begin
|
||||
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd1) begin
|
||||
flag_video_send <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
recv_video_id03: begin
|
||||
if (cnt_trans_slot == SLOT_TIME - 2 && cnt_video_slot == 8'd2) begin
|
||||
flag_video_send <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
8'd50: begin
|
||||
// if (recv_net_data_nd) begin
|
||||
// if (recv_net_data[23:00] == 24'h7e5a33) begin
|
||||
state_net <= 8'd51;
|
||||
is_net <= 1'b1;
|
||||
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
|
||||
// recv_id <= recv_net_data[63:56];
|
||||
// recv_video_id01 <= recv_net_data[55:48];
|
||||
// recv_video_id02 <= recv_net_data[47:40];
|
||||
// recv_video_id03 <= recv_net_data[39:32];
|
||||
// recv_connect_node <= recv_net_data[31:24];
|
||||
// end
|
||||
// else begin
|
||||
// state_net <= 8'd200;
|
||||
// is_net <= 1'b0;
|
||||
|
||||
// cnt_trans_slot <= cnt_inter_slot + 32'd1;
|
||||
// end
|
||||
// end
|
||||
// else begin
|
||||
// cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
// cnt_inter_slot <= cnt_inter_slot + 32'd1;
|
||||
// end
|
||||
end
|
||||
8'd51: begin
|
||||
state_net <= 8'd200;
|
||||
cnt_trans_slot <= cnt_trans_slot + 32'd1;
|
||||
end
|
||||
|
||||
default: begin
|
||||
state_net <= 8'd0;
|
||||
cnt_trans_slot <= 32'd0;
|
||||
cnt_inter_slot <= 32'd0;
|
||||
cnt_other <= 32'd0;
|
||||
recv_id <= recv_id;
|
||||
recv_connect_node <= 8'd0;
|
||||
recv_video_id01 <= recv_video_id01;
|
||||
recv_video_id02 <= recv_video_id02;
|
||||
recv_video_id03 <= recv_video_id03;
|
||||
tx_start <= 1'b0;
|
||||
trans_net_data <= 64'd0;
|
||||
is_net <= 1'b0;
|
||||
flag_video_send <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//----------connect_node----------
|
||||
// always @(posedge clk) begin
|
||||
// if (rst) begin
|
||||
// connect_node <= 8'd0;
|
||||
// end else begin
|
||||
// if (state_net == 8'd51) begin
|
||||
// case (recv_id)
|
||||
// 8'd1: begin
|
||||
// connect_node[07:06] <= 2'b11;
|
||||
// end
|
||||
// 8'd2: begin
|
||||
// connect_node[05:04] <= 2'b11;
|
||||
// end
|
||||
// 8'd3: begin
|
||||
// connect_node[03:02] <= 2'b11;
|
||||
// end
|
||||
// 8'd4: begin
|
||||
// connect_node[01:00] <= 2'b11;
|
||||
// end
|
||||
// default: begin
|
||||
// connect_node <= 8'd0;
|
||||
// end
|
||||
// endcase
|
||||
// end else if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num) begin
|
||||
// connect_node <= 8'd0;
|
||||
// end else begin
|
||||
// connect_node <= connect_node;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
//----------trans_net_data_reg----------
|
||||
reg [07:0] trans_video_id01;
|
||||
reg [07:0] trans_video_id02;
|
||||
reg [07:0] trans_video_id03;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
trans_video_id01 <= 8'd0;
|
||||
trans_video_id02 <= 8'd0;
|
||||
trans_video_id03 <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (id_num == 8'd1) begin //主节点
|
||||
trans_video_id01 <= video_id01;
|
||||
trans_video_id02 <= video_id02;
|
||||
trans_video_id03 <= video_id03;
|
||||
end
|
||||
else if (recv_id == 8'd1) begin //从节点只听从主节点命令
|
||||
trans_video_id01 <= recv_video_id01;
|
||||
trans_video_id02 <= recv_video_id02;
|
||||
trans_video_id03 <= recv_video_id03;
|
||||
end
|
||||
else begin
|
||||
trans_video_id01 <= trans_video_id01;
|
||||
trans_video_id02 <= trans_video_id02;
|
||||
trans_video_id03 <= trans_video_id03;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
trans_net_data_reg <= 64'd0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_trans_slot == SLOT_TIME / 2 && cur_slot == id_num - 8'd1) begin
|
||||
trans_net_data_reg[63:56] <= id_num;
|
||||
trans_net_data_reg[55:48] <= trans_video_id01;
|
||||
trans_net_data_reg[47:40] <= trans_video_id02;
|
||||
trans_net_data_reg[39:32] <= trans_video_id03;
|
||||
trans_net_data_reg[31:24] <= connect_node;
|
||||
trans_net_data_reg[23:00] <= 24'h7e5a33;
|
||||
end
|
||||
else begin
|
||||
trans_net_data_reg <= trans_net_data_reg;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//----------cur_slot----------
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cur_slot <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (state_net == 8'd51) begin
|
||||
if (recv_id <= max_slot_num) begin
|
||||
cur_slot <= recv_id - 8'd1;
|
||||
end
|
||||
else begin
|
||||
cur_slot <= cur_slot;
|
||||
end
|
||||
end
|
||||
else if (cnt_trans_slot == SLOT_TIME - 1) begin
|
||||
if (cur_slot == max_slot_num - 8'd1) begin
|
||||
cur_slot <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
cur_slot <= cur_slot + 8'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cur_slot <= cur_slot;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//----------cnt_video_slot----------
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_video_slot <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_trans_slot == SLOT_TIME - 1) begin
|
||||
if (cnt_video_slot == 8'd2) begin
|
||||
cnt_video_slot <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_video_slot <= cnt_video_slot + 8'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_video_slot <= cnt_video_slot;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_to_uc <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (cnt_trans_slot == SLOT_TIME / 2 - 1) begin
|
||||
flag_to_uc <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
flag_to_uc <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
ila_MAC ila_MAC (
|
||||
.clk (clk),
|
||||
.probe0 (tx_start),
|
||||
.probe1 (connect_node),
|
||||
.probe2 (cnt_trans_slot),
|
||||
.probe3 (recv_net_data),
|
||||
.probe4 (state_net),
|
||||
.probe5 (recv_id),
|
||||
.probe6 (cur_slot),
|
||||
.probe7 (id_num),
|
||||
.probe8 (frame_sync),
|
||||
.probe9 (max_slot_num),
|
||||
.probe10(recv_net_data_nd),
|
||||
.probe11(trans_net_data)
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,261 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/12/14 14:44:05
|
||||
// Design Name:
|
||||
// Module Name: phase_adjust
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module phase_adjust (
|
||||
input clk,
|
||||
input rst,
|
||||
input [9:0] din_i,
|
||||
input [9:0] din_q,
|
||||
input nd,
|
||||
input framesync,
|
||||
output reg rdy,
|
||||
output [9:0] dout_i,
|
||||
output [9:0] dout_q
|
||||
);
|
||||
|
||||
|
||||
reg [ 7:0] addra = 8'd0;
|
||||
reg [19:0] dina = 20'd0;
|
||||
reg [ 7:0] addrb = 8'd0;
|
||||
wire [19:0] doutb;
|
||||
RAM_phase RAM_phase (
|
||||
.clka (clk), // input clka
|
||||
.wea (1'b1), // input [0 : 0] wea
|
||||
.addra(addra), // input [9 : 0] addra
|
||||
.dina (dina), // input [15 : 0] dina
|
||||
.clkb (clk), // input clkb
|
||||
.addrb(addrb), // input [10 : 0] addrb
|
||||
.doutb(doutb) // output [7 : 0] doutb
|
||||
);
|
||||
|
||||
|
||||
wire [10:0] squarei;
|
||||
wire [10:0] squareq;
|
||||
wire [47:0] m_axis_dout_tdata;
|
||||
wire m_axis_dout_tvalid;
|
||||
CompMultIP CompMultIP1 (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_a_tvalid (nd), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata ({6'd0, din_q, 6'd0, din_i}), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (nd), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata ({6'd0, din_q, 6'd0, din_i}), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata
|
||||
);
|
||||
assign squareq = m_axis_dout_tdata[40:30];
|
||||
assign squarei = m_axis_dout_tdata[16:6];
|
||||
|
||||
wire [11:0] square2i;
|
||||
wire [11:0] square2q;
|
||||
wire [47:0] m_axis_dout_tdata2;
|
||||
wire m_axis_dout_tvalid2;
|
||||
CompMultIP2 CompMultIP2 (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_a_tvalid (m_axis_dout_tvalid), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata ({5'd0, squareq, 5'd0, squarei}), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (m_axis_dout_tvalid), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata ({5'd0, squareq, 5'd0, squarei}), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid(m_axis_dout_tvalid2), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (m_axis_dout_tdata2) // output wire [47 : 0] m_axis_dout_tdata
|
||||
);
|
||||
assign square2q = m_axis_dout_tdata2[41:30];
|
||||
assign square2i = m_axis_dout_tdata2[17:6];
|
||||
|
||||
|
||||
reg [19:0] sum256i = 20'd0;
|
||||
reg [19:0] sum256q = 20'd0;
|
||||
reg [ 9:0] addradelay = 10'd0;
|
||||
reg [ 3:0] state_phase;
|
||||
reg [ 9:0] cnt_phase;
|
||||
reg sum_rdy;
|
||||
reg rotate_nd;
|
||||
reg [ 9:0] phase_estm;
|
||||
reg [ 9:0] phase_shengyu;
|
||||
reg [ 9:0] phase_final;
|
||||
reg [ 9:0] phase_pi = 10'b0110010010;
|
||||
|
||||
|
||||
wire [ 9:0] phase_out;
|
||||
wire [ 5:0] phase_out_head;
|
||||
wire phaserdy;
|
||||
atan2_phase atan2_phase (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_cartesian_tvalid(sum_rdy), // input wire s_axis_cartesian_tvalid
|
||||
.s_axis_cartesian_tdata ({4'd0, sum256q, 4'd0, sum256i}), // input wire [47 : 0] s_axis_cartesian_tdata
|
||||
.m_axis_dout_tvalid (phaserdy), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata ({phase_out_head, phase_out}) // output wire [15 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
wire [5:0] rotate_headq;
|
||||
wire [5:0] rotate_headi;
|
||||
wire rotate_rdy;
|
||||
|
||||
|
||||
atan2_rotate atan2_rotate (
|
||||
.aclk (clk), // input wire aclk
|
||||
.s_axis_cartesian_tvalid(rotate_nd), // input wire s_axis_cartesian_tvalid
|
||||
.s_axis_cartesian_tdata ({6'd0, doutb[19:10], 6'd0, doutb[9:0]}), // input wire [47 : 0] s_axis_cartesian_tdata
|
||||
.s_axis_phase_tvalid (rotate_nd), // input wire s_axis_cartesian_tvalid
|
||||
.s_axis_phase_tdata ({6'd0, phase_final[9], phase_final[9], phase_final[9:2]}), // input wire [47 : 0] s_axis_cartesian_tdata
|
||||
.m_axis_dout_tvalid (rotate_rdy), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata ({rotate_headq, dout_q, rotate_headi, dout_i}) // output wire [15 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_phase <= 4'd0;
|
||||
addradelay <= 10'd0;
|
||||
sum256i <= 20'd0;
|
||||
sum256q <= 20'd0;
|
||||
cnt_phase <= 10'd0;
|
||||
sum_rdy <= 1'b0;
|
||||
phase_estm <= 10'd0;
|
||||
phase_shengyu <= 10'd0;
|
||||
phase_final <= 10'd0;
|
||||
rotate_nd <= 1'b0;
|
||||
rdy <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rdy <= rotate_rdy;
|
||||
case (state_phase)
|
||||
4'd0: begin
|
||||
if (framesync) begin
|
||||
state_phase <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
state_phase <= 4'd0;
|
||||
end
|
||||
end
|
||||
4'd1: begin
|
||||
if (nd) begin
|
||||
addradelay <= addradelay + 10'd1;
|
||||
dina <= {din_q, din_i};
|
||||
addra <= addradelay[7:0];
|
||||
if (addradelay == 10'd255) begin
|
||||
state_phase <= 4'd2;
|
||||
addradelay <= 10'd0;
|
||||
end
|
||||
else begin
|
||||
state_phase <= 4'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
state_phase <= 4'd1;
|
||||
addradelay <= addradelay;
|
||||
addra <= addra;
|
||||
dina <= dina;
|
||||
state_phase <= 2'd1;
|
||||
end
|
||||
|
||||
|
||||
if (m_axis_dout_tvalid2) begin
|
||||
cnt_phase <= cnt_phase + 10'd1;
|
||||
sum256i <= sum256i + {square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i};
|
||||
sum256q <= sum256q + {square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q};
|
||||
end
|
||||
else begin
|
||||
cnt_phase <= cnt_phase;
|
||||
sum256i <= sum256i;
|
||||
sum256q <= sum256q;
|
||||
end
|
||||
end
|
||||
4'd2: begin
|
||||
if (m_axis_dout_tvalid2) begin
|
||||
if (cnt_phase == 10'd255) begin
|
||||
cnt_phase <= 10'd0;
|
||||
state_phase <= 4'd3;
|
||||
sum_rdy <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_phase <= cnt_phase + 10'd1;
|
||||
sum_rdy <= 1'b0;
|
||||
state_phase <= 4'd2;
|
||||
end
|
||||
sum256i <= sum256i + {square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i[11], square2i};
|
||||
sum256q <= sum256q + {square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q[11], square2q};
|
||||
end
|
||||
else begin
|
||||
cnt_phase <= cnt_phase;
|
||||
state_phase <= 4'd2;
|
||||
sum256i <= sum256i;
|
||||
sum256q <= sum256q;
|
||||
end
|
||||
end
|
||||
4'd3: begin
|
||||
sum_rdy <= 1'b0;
|
||||
if (phaserdy) begin
|
||||
sum256i <= 20'd0;
|
||||
sum256q <= 20'd0;
|
||||
phase_estm <= phase_out;
|
||||
if (phase_out[9]) begin
|
||||
phase_shengyu <= phase_pi + phase_out;
|
||||
end
|
||||
else begin
|
||||
phase_shengyu <= phase_pi - phase_out;
|
||||
end
|
||||
state_phase <= 4'd4;
|
||||
end
|
||||
else begin
|
||||
phase_estm <= phase_estm;
|
||||
state_phase <= 4'd3;
|
||||
end
|
||||
end
|
||||
4'd4: begin
|
||||
if (phase_estm[9]) begin
|
||||
phase_final <= -phase_shengyu;
|
||||
end
|
||||
else begin
|
||||
phase_final <= phase_shengyu;
|
||||
end
|
||||
if (cnt_phase == 10'd0) begin
|
||||
cnt_phase <= cnt_phase + 10'd1;
|
||||
addrb <= 10'd0;
|
||||
rotate_nd <= 1'b1;
|
||||
end
|
||||
else if (cnt_phase == 10'd256) begin
|
||||
cnt_phase <= 10'd0;
|
||||
rotate_nd <= 1'b0;
|
||||
state_phase <= 4'd1;
|
||||
addrb <= 8'd0;
|
||||
end
|
||||
else begin
|
||||
cnt_phase <= cnt_phase + 10'd1;
|
||||
addrb <= addrb + 8'd1;
|
||||
rotate_nd <= 1'b1;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
if (framesync) begin
|
||||
state_phase <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
state_phase <= 4'd0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+50
-6
@@ -63,8 +63,20 @@ module phy_control #(
|
||||
// resetn (should synchronised with "clk")
|
||||
input rstn, // can be floating if ASYNC_CLK == 0
|
||||
|
||||
output wire phy_rst,
|
||||
output wire phy_tx_test_flag
|
||||
// control sigal
|
||||
output wire phy_rst,
|
||||
output wire phy_tx_test_flag,
|
||||
output wire phy_tx_iq_reverse,
|
||||
output wire phy_rx_iq_reverse,
|
||||
// tdma parameters
|
||||
output wire tdma_flag_is_master,
|
||||
output wire [31:0] tdma_slot_len,
|
||||
output wire [31:0] tdma_tic_2_ps,
|
||||
output wire [31:0] tdma_id_cfg,
|
||||
output wire tdma_recv_cur_slot_id_valid,
|
||||
output wire [ 7:0] tdma_recv_cur_slot_id,
|
||||
output wire [31:0] tdma_frame_sync_tic
|
||||
|
||||
//--- ADD YOUR OWN PORTS END
|
||||
);
|
||||
|
||||
@@ -329,10 +341,20 @@ module phy_control #(
|
||||
|
||||
localparam integer PHY_CR = 'h00000000 >> 2; // RW
|
||||
localparam integer PHY_SR = 'h00000004 >> 2; // RW
|
||||
localparam integer TDMA_SLOT_LEN = 'h0000_0008 >> 2;
|
||||
localparam integer TDMA_TIC_2_PS = 'h0000_000C >> 2;
|
||||
localparam integer TDMA_ID_CFG = 'h0000_0010 >> 2;
|
||||
localparam integer TDMA_RECV_ID = 'h0000_0014 >> 2;
|
||||
localparam integer TDMA_FRAME_SYNC_TIC = 'h0000_0018 >> 2;
|
||||
|
||||
// Register definitions
|
||||
reg [31:0] phy_cr_reg = 32'h0;
|
||||
reg [31:0] phy_sr_reg = 32'h0;
|
||||
reg [31:0] tdma_slot_len_reg = 32'h0;
|
||||
reg [31:0] tdma_tic_2_ps_reg = 32'h0;
|
||||
reg [31:0] tdma_id_cfg_reg = 32'h0; // 2B zero pad, 1B slot num, 1B local id
|
||||
reg [31:0] tdma_recv_id_reg = 32'h0;
|
||||
reg [31:0] tdma_frame_sync_tic_reg = 32'h0;
|
||||
|
||||
// Register Reading
|
||||
always @(posedge local_clk) begin
|
||||
@@ -355,21 +377,43 @@ module phy_control #(
|
||||
case (up_waddr_s)
|
||||
PHY_CR: phy_cr_reg <= up_wdata_s;
|
||||
PHY_SR: phy_sr_reg <= up_wdata_s;
|
||||
TDMA_SLOT_LEN: tdma_slot_len_reg <= up_wdata_s;
|
||||
TDMA_TIC_2_PS: tdma_tic_2_ps_reg <= up_wdata_s;
|
||||
TDMA_ID_CFG: tdma_id_cfg_reg <= up_wdata_s;
|
||||
TDMA_RECV_ID: tdma_recv_id_reg <= up_wdata_s;
|
||||
TDMA_FRAME_SYNC_TIC: tdma_frame_sync_tic_reg <= up_wdata_s;
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
// self logic
|
||||
if (tdma_recv_id_reg[8] == 1) begin
|
||||
tdma_recv_id_reg[8] <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// control reg definition
|
||||
assign phy_rst = ~phy_cr_reg[0];
|
||||
assign phy_tx_test_flag = phy_cr_reg[1];
|
||||
|
||||
|
||||
assign phy_rst = ~phy_cr_reg[0];
|
||||
assign phy_tx_test_flag = phy_cr_reg[1];
|
||||
assign phy_tx_iq_reverse = phy_cr_reg[2];
|
||||
assign phy_rx_iq_reverse = phy_cr_reg[3];
|
||||
assign tdma_flag_is_master = phy_cr_reg[4];
|
||||
// tdma
|
||||
assign tdma_slot_len = tdma_slot_len_reg;
|
||||
assign tdma_tic_2_ps = tdma_tic_2_ps_reg;
|
||||
assign tdma_id_cfg = tdma_id_cfg_reg;
|
||||
// received mac frame
|
||||
assign tdma_recv_cur_slot_id = tdma_recv_id_reg[7:0];
|
||||
assign tdma_recv_cur_slot_id_valid = tdma_recv_id_reg[8];
|
||||
// frame sync tic
|
||||
assign tdma_frame_sync_tic = tdma_frame_sync_tic_reg;
|
||||
|
||||
// vio_phy_param u_vio_phy_param (
|
||||
// .clk (local_clk),
|
||||
// .probe_in0(phy_cr_reg)
|
||||
// );
|
||||
|
||||
//--- ADD YOUR OWN LOGIC END
|
||||
|
||||
|
||||
+12
-2
@@ -25,11 +25,12 @@ module power_measure (
|
||||
input wire [11:0] data_i,
|
||||
input wire [11:0] data_q,
|
||||
output reg flag_too_high,
|
||||
output reg flag_too_low
|
||||
output reg flag_too_low,
|
||||
output reg power_measure_done_pulse
|
||||
);
|
||||
|
||||
localparam CNT_WAIT_9361_MAX = 80; //* 等待周期数
|
||||
localparam CNT_MEASURING_MAX = 512; // * 观察64个周期
|
||||
localparam CNT_MEASURING_MAX = 4096; // * 观察4096个周期
|
||||
localparam CNT_ADJUST_TIMES_MAX = 25;
|
||||
localparam CNT_AMP_TOO_HIGH_THRESHOLD = 6;
|
||||
// ******** Wire & Reg ********
|
||||
@@ -200,6 +201,15 @@ module power_measure (
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_MEASURE_ADJ && ns == S_MEASURE_IDLE) begin
|
||||
power_measure_done_pulse <= 1;
|
||||
end
|
||||
else begin
|
||||
power_measure_done_pulse <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// get the abs value
|
||||
always @(posedge clk) begin
|
||||
|
||||
+161
@@ -0,0 +1,161 @@
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
// * ╚══███╔╝██╔═══██╗██╔══██╗██╔═══██╗██╔════╝ ██║ ██║ *
|
||||
// * ███╔╝ ██║ ██║██████╔╝██║ ██║██║ ███╗███████║ *
|
||||
// * ███╔╝ ██║ ██║██╔══██╗██║ ██║██║ ██║██╔══██║ *
|
||||
// * ███████╗╚██████╔╝██║ ██║╚██████╔╝╚██████╔╝██║ ██║ *
|
||||
// * ╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═════╝ ╚═════╝ ╚═╝ ╚═╝ *
|
||||
// * *************************************************** *
|
||||
// * Update Date:
|
||||
// * NOTE :
|
||||
module scrambler #(
|
||||
parameter ILA_ON = 0
|
||||
) (
|
||||
input clk,
|
||||
input rst_n,
|
||||
// s_axis_stream
|
||||
input [31:0] s_axis_tdata,
|
||||
input s_axis_tvalid,
|
||||
output reg s_axis_tready,
|
||||
input s_axis_tlast,
|
||||
input [31:0] s_axis_rd_data_count,
|
||||
// m_axis_stream
|
||||
output reg [31:0] m_axis_tdata,
|
||||
output reg m_axis_tvalid,
|
||||
input m_axis_tready,
|
||||
output reg m_axis_tlast
|
||||
);
|
||||
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
wire rst;
|
||||
|
||||
reg [ 2:0] addr_scramble = 0;
|
||||
reg [ 2:0] addr_scramble_d1 = 0;
|
||||
reg [ 2:0] addr_scramble_d2 = 0;
|
||||
wire [31:0] data_scramble_mask;
|
||||
reg [ 3:0] cnt_in;
|
||||
|
||||
reg [31:0] s_axis_tdata_d1;
|
||||
reg [31:0] s_axis_tdata_d2;
|
||||
|
||||
reg s_axis_tready_d1;
|
||||
reg s_axis_tlast_d1;
|
||||
// fsm
|
||||
reg [ 1:0] cs = 0;
|
||||
reg [ 1:0] ns = 0;
|
||||
localparam S_IDLE = 0;
|
||||
localparam S_WORKING = 1;
|
||||
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign rst = ~rst_n;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
cs <= ns;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
ns = cs;
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
if (s_axis_tvalid && m_axis_tready && s_axis_rd_data_count >= 8) begin
|
||||
ns = S_WORKING;
|
||||
end
|
||||
end
|
||||
S_WORKING: begin
|
||||
if (addr_scramble_d2 == 3'h7) begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE) begin
|
||||
addr_scramble <= 0;
|
||||
end
|
||||
else begin
|
||||
addr_scramble <= addr_scramble + 1;
|
||||
end
|
||||
addr_scramble_d1 <= addr_scramble;
|
||||
addr_scramble_d2 <= addr_scramble_d1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_WORKING) begin
|
||||
m_axis_tdata <= s_axis_tdata_d1 ^ data_scramble_mask;
|
||||
end
|
||||
else begin
|
||||
m_axis_tdata <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_WORKING && s_axis_tvalid && cnt_in < 4'd8) begin
|
||||
s_axis_tready <= 1;
|
||||
end
|
||||
else begin
|
||||
s_axis_tready <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
s_axis_tdata_d1 <= s_axis_tdata;
|
||||
|
||||
s_axis_tready_d1 <= s_axis_tready;
|
||||
m_axis_tvalid <= s_axis_tready_d1;
|
||||
|
||||
s_axis_tlast_d1 <= s_axis_tlast;
|
||||
m_axis_tlast <= s_axis_tlast_d1;
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE) begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
else if (cs == S_WORKING && cnt_in < 4'd8) begin
|
||||
cnt_in <= cnt_in + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
bram_scramble u_bram_scramble (
|
||||
.clka (clk), // input wire clka
|
||||
.addra(addr_scramble), // input wire [2 : 0] addra
|
||||
.douta(data_scramble_mask) // output wire [31 : 0] douta
|
||||
);
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
generate
|
||||
if (ILA_ON)
|
||||
ila_scrambler u_ila_scrambler (
|
||||
.clk (clk), // input wire clk
|
||||
.probe0(s_axis_tvalid), // input wire [0:0] probe0
|
||||
.probe1(s_axis_tready), // input wire [0:0] probe1
|
||||
.probe2(s_axis_tdata), // input wire [31:0] probe2
|
||||
.probe3(s_axis_tlast), // input wire [0:0] probe3
|
||||
.probe4(m_axis_tvalid), // input wire [0:0] probe4
|
||||
.probe5(m_axis_tready), // input wire [0:0] probe5
|
||||
.probe6(m_axis_tdata), // input wire [31:0] probe6
|
||||
.probe7(m_axis_tlast), // input wire [0:0] probe7
|
||||
.probe8(data_scramble_mask) // input wire [31:0] probe8
|
||||
);
|
||||
|
||||
endgenerate
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,61 @@
|
||||
module ser2par #(
|
||||
parameter PAR_WIDTH = 32
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input wire ser,
|
||||
input wire ser_valid,
|
||||
output reg [PAR_WIDTH -1:0] par,
|
||||
output reg par_valid
|
||||
);
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
reg [$clog2(PAR_WIDTH):0] cnt_idx;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_idx <= 0;
|
||||
end
|
||||
else if (ser_valid) begin
|
||||
if (cnt_idx == PAR_WIDTH - 1) begin // force it return to 0
|
||||
cnt_idx <= 0;
|
||||
end
|
||||
else begin
|
||||
cnt_idx <= cnt_idx + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
par <= 0;
|
||||
end
|
||||
else if (ser_valid) begin
|
||||
par[cnt_idx] <= ser;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cnt_idx == PAR_WIDTH - 1) begin
|
||||
par_valid <= 1;
|
||||
end
|
||||
else begin
|
||||
par_valid <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
+202
-174
@@ -70,6 +70,8 @@ module system_top (
|
||||
wire clk_1x;
|
||||
wire clk_2x;
|
||||
wire clk_4x;
|
||||
wire clk_quarter;
|
||||
wire clk_half;
|
||||
|
||||
// emio
|
||||
wire [31:0] gpio_i;
|
||||
@@ -89,6 +91,12 @@ module system_top (
|
||||
wire tx_data_src_tvalid;
|
||||
// tx signal
|
||||
wire tx_test_flag;
|
||||
wire flag_mgc_done_pulse;
|
||||
// rx bus
|
||||
wire [31:0] rx_data_src_fifo_tdata;
|
||||
wire rx_data_src_fifo_tlast;
|
||||
wire rx_data_src_fifo_tready;
|
||||
wire rx_data_src_fifo_tvalid;
|
||||
|
||||
// baseband signal
|
||||
wire [11:0] ad9361_rx_data_i;
|
||||
@@ -98,29 +106,67 @@ module system_top (
|
||||
wire [11:0] ad9361_tx_data_i;
|
||||
wire [11:0] ad9361_tx_data_q;
|
||||
wire [ 2:0] speed_mode;
|
||||
// mux
|
||||
wire bb_tx_iq_reverse;
|
||||
wire bb_rx_iq_reverse;
|
||||
wire [11:0] bb_tx_i;
|
||||
wire [11:0] bb_tx_q;
|
||||
wire [11:0] bb_rx_i;
|
||||
wire [11:0] bb_rx_q;
|
||||
|
||||
// phy control signal
|
||||
wire phy_rst_vio;
|
||||
wire phy_rst_ps;
|
||||
wire phy_rst;
|
||||
wire phy_tx_test_flag_vio;
|
||||
wire phy_tx_test_flag;
|
||||
wire phy_tx_iq_reverse;
|
||||
wire phy_rx_iq_reverse;
|
||||
wire tdma_flag_is_master;
|
||||
wire [31:0] tdma_slot_len;
|
||||
wire [31:0] tdma_tic_2_ps;
|
||||
wire [31:0] tdma_id_cfg;
|
||||
wire tdma_recv_cur_slot_id_valid;
|
||||
wire [ 7:0] tdma_recv_cur_slot_id;
|
||||
wire [31:0] tdma_frame_sync_tic;
|
||||
|
||||
|
||||
// tx signal
|
||||
wire frame_sync_pulse;
|
||||
wire rx_rst;
|
||||
wire tx_done;
|
||||
wire intr_2ps_vio;
|
||||
reg intr_2ps_vio_d1;
|
||||
wire intr_2ps_vio_pos;
|
||||
|
||||
wire tx_start_vio;
|
||||
reg tx_start_vio_d1;
|
||||
wire tx_start_vio_pos;
|
||||
// rx
|
||||
wire rx_err_flag_pos;
|
||||
|
||||
// vio
|
||||
wire rst_manual;
|
||||
wire rx_rst_vio;
|
||||
wire [ 7:0] node_id;
|
||||
wire intr_2ps;
|
||||
wire [ 7:0] max_slot_num;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
// ad9361 control
|
||||
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
|
||||
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
|
||||
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
|
||||
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
|
||||
assign ad9361_enable = gpio_o[0]; // ad9361 enable state machine control
|
||||
assign ad9361_en_agc = gpio_o[1]; // ad9361 agc control
|
||||
assign ad9361_reset_b = gpio_o[2]; // ad9361 reset
|
||||
assign ad9361_txnrx = gpio_o[3]; // ad9361 txnrx
|
||||
|
||||
|
||||
assign ad9361_tx_data_i = phy_tx_iq_reverse ? bb_tx_q : bb_tx_i;
|
||||
assign ad9361_tx_data_q = phy_tx_iq_reverse ? bb_tx_i : bb_tx_q;
|
||||
assign bb_rx_i = phy_rx_iq_reverse ? ad9361_rx_data_q : ad9361_rx_data_i;
|
||||
assign bb_rx_q = phy_rx_iq_reverse ? ad9361_rx_data_i : ad9361_rx_data_q;
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ******** Inst ********
|
||||
@@ -137,138 +183,166 @@ module system_top (
|
||||
// clock domain - ad9361 rx & tx
|
||||
clk_wiz_baseband u_clk_wiz_baseband (
|
||||
// Clock out ports
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
.clk_quarter(clk_quarter),
|
||||
.clk_half (clk_half),
|
||||
// Status and control signals
|
||||
.locked (locked), // output locked
|
||||
.locked (locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_src(ad9361_rx_clk) // input clk_src
|
||||
.clk_src (ad9361_rx_clk) // input clk_src
|
||||
);
|
||||
|
||||
MM7020_BD_wrapper u_MM7020_BD_wrapper (
|
||||
.ad9361_spi_clk (ad9361_spi_clk),
|
||||
.ad9361_spi_csn (ad9361_spi_csn),
|
||||
.ad9361_spi_miso (ad9361_spi_miso),
|
||||
.ad9361_spi_mosi (ad9361_spi_mosi),
|
||||
.clk_ps (clk_poweron),
|
||||
.rst_ps (rst_sys),
|
||||
.ad9361_spi_clk (ad9361_spi_clk),
|
||||
.ad9361_spi_csn (ad9361_spi_csn),
|
||||
.ad9361_spi_miso (ad9361_spi_miso),
|
||||
.ad9361_spi_mosi (ad9361_spi_mosi),
|
||||
.clk_ps (clk_poweron),
|
||||
.rst_ps (rst_sys),
|
||||
// ddr
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
.ddr_ck_n (ddr_ck_n),
|
||||
.ddr_ck_p (ddr_ck_p),
|
||||
.ddr_cke (ddr_cke),
|
||||
.ddr_cs_n (ddr_cs_n),
|
||||
.ddr_dm (ddr_dm),
|
||||
.ddr_dq (ddr_dq),
|
||||
.ddr_dqs_n (ddr_dqs_n),
|
||||
.ddr_dqs_p (ddr_dqs_p),
|
||||
.ddr_odt (ddr_odt),
|
||||
.ddr_ras_n (ddr_ras_n),
|
||||
.ddr_reset_n (ddr_reset_n),
|
||||
.ddr_we_n (ddr_we_n),
|
||||
// fixed io
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
||||
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
||||
.fixed_io_mio (fixed_io_mio),
|
||||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
// gpio ps
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
// intr pl to ps
|
||||
.pl2ps_intr2 (intr_2ps),
|
||||
.pl2ps_intr3 (pl2ps_intr3),
|
||||
.pl_tx_intr (intr_2ps),
|
||||
.pl_rx_intr (rx_data_src_fifo_tlast),
|
||||
.pl_intr0 (rx_err_flag_pos),
|
||||
// tx fifo
|
||||
.tx_data_src_count (tx_data_src_count),
|
||||
.tx_data_src_tdata (tx_data_src_tdata),
|
||||
.tx_data_src_tready(tx_data_src_tready),
|
||||
.tx_data_src_tvalid(tx_data_src_tvalid),
|
||||
//phy control signal
|
||||
.phy_rst (phy_rst_ps),
|
||||
.phy_tx_test_flag (phy_tx_test_flag),
|
||||
.tx_data_src_count (tx_data_src_count),
|
||||
.tx_data_src_tdata (tx_data_src_tdata),
|
||||
.tx_data_src_tready (tx_data_src_tready),
|
||||
.tx_data_src_tvalid (tx_data_src_tvalid),
|
||||
// rx fifo
|
||||
.clk_rx_data_src_fifo (clk_half),
|
||||
.rst_rx_data_src_fifo (rx_rst),
|
||||
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
|
||||
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
|
||||
.rx_data_src_fifo_tready (rx_data_src_fifo_tready),
|
||||
.rx_data_src_fifo_tvalid (rx_data_src_fifo_tvalid),
|
||||
// phy clock and rst to ps
|
||||
.clk_phy (clk_1x),
|
||||
.rst_phy_n (~rst_sys),
|
||||
// phy control signal
|
||||
.phy_rst (phy_rst),
|
||||
.phy_tx_test_flag (phy_tx_test_flag),
|
||||
.phy_tx_iq_reverse (phy_tx_iq_reverse),
|
||||
.phy_rx_iq_reverse (phy_rx_iq_reverse),
|
||||
.tdma_flag_is_master (tdma_flag_is_master),
|
||||
.tdma_slot_len (tdma_slot_len),
|
||||
.tdma_tic_2_ps (tdma_tic_2_ps),
|
||||
.tdma_id_cfg (tdma_id_cfg),
|
||||
.tdma_recv_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
|
||||
.tdma_recv_cur_slot_id (tdma_recv_cur_slot_id),
|
||||
.tdma_frame_sync_tic (tdma_frame_sync_tic),
|
||||
// uart
|
||||
.uart_rx (uart_rx),
|
||||
.uart_tx (uart_tx)
|
||||
.uart_rx (uart_rx),
|
||||
.uart_tx (uart_tx)
|
||||
);
|
||||
|
||||
tdma u_tdma (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys),
|
||||
.flag_frame_sync (frame_sync_pulse),
|
||||
.tdma_slot_len (tdma_slot_len[23:0]),
|
||||
.tdma_tic_2_ps (tdma_tic_2_ps[23:0]),
|
||||
.tdma_slot_num (tdma_id_cfg[15:8]),
|
||||
.tdma_frame_sync_tic (tdma_frame_sync_tic[23:0]),
|
||||
.local_id (tdma_id_cfg[7:0]),
|
||||
.recevied_cur_slot_id_valid(tdma_recv_cur_slot_id_valid),
|
||||
.recevied_cur_slot_id (tdma_recv_cur_slot_id),
|
||||
.intr_2ps (intr_2ps),
|
||||
.tx_start (tx_start),
|
||||
.rx_rst (rx_rst)
|
||||
);
|
||||
|
||||
|
||||
|
||||
// ---- PHY layer logic start
|
||||
|
||||
// enc_control u_enc_control (
|
||||
// .clk (clk_poweron),
|
||||
// .rst (rst_sys | phy_rst_ps),
|
||||
// .s_axis_fifo_tvalid (tx_data_src_tvalid),
|
||||
// .s_axis_fifo_tready (tx_data_src_tready),
|
||||
// .s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
// .data_src_count (tx_data_src_count),
|
||||
// .fifo_enc_out_rd_clk (clk_1x),
|
||||
// .fifo_enc_out_rd_en (enc_fifo_rd_en),
|
||||
// .fifo_enc_out_dout_map(enc_fifo_dout_map),
|
||||
// .fifo_enc_out_empty (enc_fifo_empty)
|
||||
// );
|
||||
|
||||
|
||||
// tdma #(
|
||||
// .SLOT_LEN (1250000), // 50MHz--> 25ms
|
||||
// .TIC_TO_PS_LEN (1200000),
|
||||
// .TIC_FRAME_SYNC(42272)
|
||||
// ) u_tdma (
|
||||
// .clk (clk_1x),
|
||||
// .rst (rst_sys),
|
||||
// .flag_is_master (1'b0),
|
||||
// .flag_frame_sync(frame_sync_pulse),
|
||||
// .intr_2ps (intr_2ps),
|
||||
// .tx_start (tx_start)
|
||||
// );
|
||||
|
||||
|
||||
// Transmitter u_Transmitter (
|
||||
// .clk (clk_1x),
|
||||
// .rst (rst_sys | phy_rst | phy_rst_vio),
|
||||
// .speed_mode (speed_mode),
|
||||
// .send_data_ready (send_data_ready),
|
||||
// .send_start (send_start),
|
||||
// .send_over (send_over),
|
||||
// .clk_data_src (clk_data_src),
|
||||
// .tx_data_src_tdata (enc_fifo_dout_map),
|
||||
// .tx_data_src_tready(enc_fifo_rd_en),
|
||||
// .tx_data_src_tvalid(~enc_fifo_empty),
|
||||
// .hopping_freq (),
|
||||
// .ad9361_tx_data_i (ad9361_tx_data_i),
|
||||
// .ad9361_tx_data_q (ad9361_tx_data_q),
|
||||
// .test (tx_test_flag | phy_tx_test_flag_vio),
|
||||
// .hop_wait (100)
|
||||
// );
|
||||
|
||||
// Receiver u_Receiver (
|
||||
// .clk (clk_1x),
|
||||
// .clk_2x (clk_2x),
|
||||
// .clk_4x (clk_4x),
|
||||
// .rst (rst_sys | phy_rst | phy_rst_vio),
|
||||
// .speed_mode (speed_mode),
|
||||
// .ad9361_rx_data_i(ad9361_rx_data_i),
|
||||
// .ad9361_rx_data_q(ad9361_rx_data_q),
|
||||
// .frame_sync_pulse(frame_sync_pulse)
|
||||
// );
|
||||
|
||||
ad9361_mgc_pin_ctrl u_ad9361_mgc_pin_ctrl (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys | phy_rst),
|
||||
.rx_data_i (ad9361_rx_data_i),
|
||||
.rx_data_q (ad9361_rx_data_q),
|
||||
.ad9361_ctrl_in(ad9361_ctrl_in)
|
||||
enc_control u_enc_control (
|
||||
.clk (clk_poweron),
|
||||
.rst (rst_sys | phy_rst),
|
||||
.s_axis_fifo_tvalid (tx_data_src_tvalid),
|
||||
.s_axis_fifo_tready (tx_data_src_tready),
|
||||
.s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
.data_src_count (tx_data_src_count),
|
||||
.fifo_enc_out_rd_clk (clk_1x),
|
||||
.fifo_enc_out_rd_en (enc_fifo_rd_en),
|
||||
.fifo_enc_out_dout_map(enc_fifo_dout_map),
|
||||
.fifo_enc_out_empty (enc_fifo_empty)
|
||||
);
|
||||
|
||||
|
||||
Transmitter u_Transmitter (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys | phy_rst),
|
||||
.speed_mode (0),
|
||||
.send_data_ready (send_data_ready),
|
||||
.send_start (tx_start),
|
||||
.send_over (tx_done),
|
||||
.clk_data_src (clk_data_src),
|
||||
.tx_data_src_tdata (enc_fifo_dout_map),
|
||||
.tx_data_src_tready(enc_fifo_rd_en),
|
||||
.tx_data_src_tvalid(~enc_fifo_empty),
|
||||
.hopping_freq (),
|
||||
.ad9361_tx_data_i (bb_tx_i),
|
||||
.ad9361_tx_data_q (bb_tx_q),
|
||||
.test (phy_tx_test_flag),
|
||||
.hop_wait (100)
|
||||
);
|
||||
|
||||
|
||||
RecvTop u_RecvTop (
|
||||
.clk (clk_1x),
|
||||
.clk_2x (clk_2x),
|
||||
.clk_4x (clk_4x),
|
||||
.clk_half (clk_half),
|
||||
.clk_quarter (clk_quarter),
|
||||
.rst (rst_sys | rx_rst | phy_rst),
|
||||
.rst2 (rst_sys | phy_rst),
|
||||
.dini (bb_rx_i),
|
||||
.dinq (bb_rx_q),
|
||||
.ad9361_ctrl_in (ad9361_ctrl_in),
|
||||
.flag_mgc_done_pulse (flag_mgc_done_pulse),
|
||||
.frame_sync_pulse_1x (frame_sync_pulse),
|
||||
.vio_tsync_inter16 (1),
|
||||
.EQUenable_vio (1),
|
||||
.Zerozone_vio (8'd29),
|
||||
.vio_stopbit (7'd60),
|
||||
.flag_stop (flag_stop),
|
||||
.addr_stop (addr_stop),
|
||||
.recvNetData (recvNetData),
|
||||
.recvNetDataNd (recvNetDataNd),
|
||||
.rx_data_src_fifo_tdata (rx_data_src_fifo_tdata),
|
||||
.rx_data_src_fifo_tlast (rx_data_src_fifo_tlast),
|
||||
.rx_data_src_fifo_tready(rx_data_src_fifo_tready),
|
||||
.rx_data_src_fifo_tvalid(rx_data_src_fifo_tvalid),
|
||||
.err_flag_pos (rx_err_flag_pos)
|
||||
);
|
||||
|
||||
// ---- PHY layer logic end
|
||||
|
||||
@@ -293,66 +367,20 @@ module system_top (
|
||||
|
||||
// ******** CDC ********
|
||||
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) xpm_cdc_single_tx_test_flag_ps_inst (
|
||||
.dest_out(tx_test_flag), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk(clk_1x), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (clk_poweron), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (phy_tx_test_flag) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
xpm_cdc_sync_rst #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT (1), // DECIMAL; 0=initialize synchronization registers to 0, 1=initialize synchronization registers to 1
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK(0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) xpm_cdc_sync_rst_phy_rst_inst (
|
||||
.dest_rst(phy_rst), // 1-bit output: src_rst synchronized to the destination clock domain. This output is registered.
|
||||
.dest_clk(clk_1x), // 1-bit input: Destination clock.
|
||||
.src_rst (phy_rst_ps) // 1-bit input: Source reset signal.
|
||||
);
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
ila_ad9361_rx u_ila_ad9361_rx (
|
||||
.clk (ad9361_rx_clk),
|
||||
.probe0(ad9361_rx_data_i),
|
||||
.probe1(ad9361_rx_data_q),
|
||||
.probe2(u_ad9361_mgc_pin_ctrl.flag_adjust)
|
||||
);
|
||||
|
||||
ila_ad9361_tx u_ila_ad9361_tx (
|
||||
.clk (ad9361_tx_clk), // input wire clk
|
||||
.probe0(ad9361_tx_data_i), // input wire [11:0] probe0
|
||||
.probe1(ad9361_tx_data_q) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
|
||||
vio_phy_control u_vio_phy_control (
|
||||
.clk (clk_1x), // input wire clk
|
||||
.probe_out0(phy_rst_vio), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(phy_tx_test_flag_vio), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(send_start) // output wire [0 : 0] probe_out2
|
||||
);
|
||||
|
||||
|
||||
vio_gpio u_vio_gpio (
|
||||
.clk (clk_poweron),
|
||||
.probe_out0(rf_gpio),
|
||||
.probe_out1(led_red),
|
||||
.probe_out2(led_yellow),
|
||||
.probe_out3(led_blue)
|
||||
);
|
||||
|
||||
vio_tx_speed_mode u_vio_tx_speed_mode (
|
||||
.clk (clk_1x),
|
||||
.probe_out0(speed_mode)
|
||||
);
|
||||
|
||||
// ila_ad9361_rx u_ila_ad9361_rx (
|
||||
// .clk (ad9361_rx_clk),
|
||||
// .probe0(ad9361_rx_data_i),
|
||||
// .probe1(ad9361_rx_data_q),
|
||||
// .probe2(u_RecvTop.flag_mgc_done)
|
||||
// );
|
||||
|
||||
// ila_ad9361_tx u_ila_ad9361_tx (
|
||||
// .clk (ad9361_tx_clk), // input wire clk
|
||||
// .probe0(ad9361_tx_data_i), // input wire [11:0] probe0
|
||||
// .probe1(ad9361_tx_data_q) // input wire [11:0] probe1
|
||||
// );
|
||||
|
||||
endmodule
|
||||
|
||||
+149
-80
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
@@ -13,108 +13,177 @@
|
||||
|
||||
// ! PLEASE MAKE SURE THE PARAMETER ARE VALID
|
||||
// ! WHEN U INSTANTIATE THIS MODULE
|
||||
module tdma #(
|
||||
parameter SLOT_LEN = 1250000,
|
||||
parameter TIC_TO_PS_LEN = 1200000,
|
||||
parameter TIC_FRAME_SYNC = 42272
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input flag_is_master,
|
||||
input flag_frame_sync,
|
||||
output intr_2ps,
|
||||
// output tic_hop,
|
||||
output tx_start
|
||||
module tdma (
|
||||
input clk,
|
||||
input rst,
|
||||
// PHY parameter
|
||||
input flag_frame_sync,
|
||||
// general parameter, update only once
|
||||
input wire [23:0] tdma_slot_len,
|
||||
input wire [23:0] tdma_tic_2_ps,
|
||||
input wire [ 7:0] tdma_slot_num,
|
||||
input wire [23:0] tdma_frame_sync_tic,
|
||||
input wire [ 7:0] local_id, // ID number for this device
|
||||
// update while received valid
|
||||
input wire recevied_cur_slot_id_valid, // recevied ID number of the frame
|
||||
input wire [ 7:0] recevied_cur_slot_id,
|
||||
output intr_2ps,
|
||||
output tx_start,
|
||||
output reg rx_rst
|
||||
);
|
||||
|
||||
// TODO: 需要检查综合后电路是否会被优化
|
||||
// BUG: 需要修复bug，重构代码，把主从分开写，通过参数进行优化
|
||||
// ******** Wire & Reg ********
|
||||
reg flag_is_tx_slot;
|
||||
|
||||
reg flag_next_slot_is_tx_slot;
|
||||
reg [23:0] cnt_tdma_slot_len;
|
||||
reg [ 7:0] cur_slot_id;
|
||||
wire flag_end_of_one_slot; // the last period of the slot
|
||||
wire [23:0] tdma_tic_frame_sync_vio;
|
||||
|
||||
// fsm
|
||||
localparam S_IDLE = 0;
|
||||
localparam S_RX = 1;
|
||||
localparam S_TX = 2;
|
||||
reg [1:0] cs = 0;
|
||||
reg [1:0] ns = 0;
|
||||
|
||||
// ******** Assingment ********
|
||||
|
||||
assign flag_end_of_one_slot = (cnt_tdma_slot_len == tdma_slot_len - 1);
|
||||
assign tx_start = (cs == S_TX) & (cnt_tdma_slot_len == 16'd10);
|
||||
assign intr_2ps = flag_next_slot_is_tx_slot & (cnt_tdma_slot_len == tdma_tic_2_ps - 1);
|
||||
|
||||
// ******** Logic Block ********
|
||||
|
||||
generate
|
||||
if (SLOT_LEN <= 65535) begin // slot len is small
|
||||
reg [15:0] cnt;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 16'd0;
|
||||
|
||||
// fsm
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cs <= S_IDLE;
|
||||
end
|
||||
else begin
|
||||
cs <= ns;
|
||||
end
|
||||
end
|
||||
|
||||
// conditional transition
|
||||
always @(*) begin
|
||||
ns = cs;
|
||||
case (cs)
|
||||
S_IDLE: begin
|
||||
// if this device is master node, ps should first send one packet to the fifo
|
||||
if (local_id == 1) begin
|
||||
ns = S_TX;
|
||||
end
|
||||
else begin
|
||||
if (!flag_is_master && flag_frame_sync) begin
|
||||
// slave update cnt
|
||||
cnt <= TIC_FRAME_SYNC;
|
||||
end
|
||||
else if (cnt >= SLOT_LEN - 1) begin
|
||||
cnt <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt + 16'd1;
|
||||
end
|
||||
else if (recevied_cur_slot_id_valid) begin
|
||||
ns = S_RX;
|
||||
end
|
||||
end
|
||||
assign tx_start = flag_is_tx_slot & (cnt == 16'd10); // just a num for avoiding the zero,(cnt is also 0 in rst state)
|
||||
assign intr_2ps = ~flag_is_tx_slot & (cnt == TIC_TO_PS_LEN);
|
||||
S_RX: begin
|
||||
if (flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
|
||||
ns = S_TX;
|
||||
end
|
||||
end
|
||||
S_TX: begin
|
||||
if (~flag_next_slot_is_tx_slot && flag_end_of_one_slot) begin
|
||||
ns = S_RX;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
ns = S_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (!flag_is_master && flag_frame_sync) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (cnt == 16'd1) begin
|
||||
flag_is_tx_slot <= ~flag_is_tx_slot;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_tdma_slot_len <= 0;
|
||||
end
|
||||
else if (flag_frame_sync) begin
|
||||
cnt_tdma_slot_len <= tdma_frame_sync_tic;
|
||||
end
|
||||
else begin
|
||||
if (flag_end_of_one_slot) begin
|
||||
cnt_tdma_slot_len <= 0;
|
||||
end
|
||||
else begin
|
||||
cnt_tdma_slot_len <= cnt_tdma_slot_len + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(*) begin
|
||||
if (cs == S_TX || cnt_tdma_slot_len <= 10) begin
|
||||
rx_rst <= 1;
|
||||
end
|
||||
else begin
|
||||
rx_rst <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cs == S_IDLE) begin
|
||||
if (ns == S_TX) begin // indicating master node
|
||||
cur_slot_id <= 1;
|
||||
end
|
||||
else if (recevied_cur_slot_id_valid) begin // from ps update, first sync, indicating slave
|
||||
cur_slot_id <= recevied_cur_slot_id;
|
||||
end
|
||||
else begin
|
||||
cur_slot_id <= 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
reg [15:0] cnt_l;
|
||||
reg [ 7:0] cnt_h;
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_l <= 16'd0;
|
||||
cnt_h <= 8'd0;
|
||||
if (recevied_cur_slot_id_valid) begin // from ps update
|
||||
cur_slot_id <= recevied_cur_slot_id;
|
||||
end
|
||||
else if (flag_end_of_one_slot) begin // at the changing moment
|
||||
if (cur_slot_id == tdma_slot_num) begin
|
||||
cur_slot_id <= 1;
|
||||
end
|
||||
else begin
|
||||
if (!flag_is_master && flag_frame_sync) begin
|
||||
// slave update cnt
|
||||
{cnt_h, cnt_l} <= TIC_FRAME_SYNC;
|
||||
end
|
||||
else begin
|
||||
// master
|
||||
if ({cnt_h, cnt_l} >= SLOT_LEN) begin
|
||||
cnt_h <= 8'd0;
|
||||
cnt_l <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
{cnt_h, cnt_l} <= {cnt_h, cnt_l} + 24'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
assign tx_start = flag_is_tx_slot & ({cnt_h, cnt_l} == 16'd10);
|
||||
assign intr_2ps = ~flag_is_tx_slot & ({cnt_h, cnt_l} == TIC_TO_PS_LEN);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if (!flag_is_master && flag_frame_sync) begin
|
||||
flag_is_tx_slot <= 0;
|
||||
end
|
||||
else if ({cnt_h, cnt_l} == 16'd1) begin
|
||||
flag_is_tx_slot <= ~flag_is_tx_slot;
|
||||
cur_slot_id <= cur_slot_id + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
end
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (local_id == 1) begin
|
||||
flag_next_slot_is_tx_slot <= (cur_slot_id == tdma_slot_num);
|
||||
end
|
||||
else begin
|
||||
flag_next_slot_is_tx_slot <= (cur_slot_id + 1 == local_id);
|
||||
end
|
||||
end
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
// ******** Debug ********
|
||||
|
||||
vio_tdma u_vio_tdma (
|
||||
.clk (clk),
|
||||
.probe_in0(tdma_slot_len),
|
||||
.probe_in1(tdma_tic_2_ps),
|
||||
.probe_in2(tdma_slot_num),
|
||||
.probe_in3(local_id),
|
||||
.probe_in4(tdma_frame_sync_tic)
|
||||
);
|
||||
|
||||
ila_mac_layer u_ila_mac_layer (
|
||||
.clk (clk),
|
||||
.probe0(cnt_tdma_slot_len), // width: 24
|
||||
.probe1(tx_start), // width: 1
|
||||
.probe2(rx_rst), // width: 1
|
||||
.probe3(cur_slot_id), // width: 8
|
||||
.probe4(intr_2ps), // width: 1
|
||||
.probe5(flag_frame_sync), // width: 1
|
||||
.probe6(recevied_cur_slot_id), // width: 8
|
||||
.probe7(recevied_cur_slot_id_valid) // width: 1
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,75 @@
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2019/08/03 14:53:56
|
||||
// Design Name:
|
||||
// Module Name: trunc_25to12_2dly
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module trunc_25to12_2dly(
|
||||
clk,
|
||||
din_nd,
|
||||
din,
|
||||
ctrl,
|
||||
dout_nd,
|
||||
dout,
|
||||
ovrflw
|
||||
);
|
||||
//--------------------- IN/OUT ------------------------
|
||||
input clk;
|
||||
input din_nd;
|
||||
input [24:0] din;
|
||||
input ctrl;
|
||||
output reg dout_nd = 0;
|
||||
output reg [11:0] dout = 0;
|
||||
output reg ovrflw = 0;
|
||||
|
||||
//---------------------- delay -----------------------
|
||||
reg [24:0] din_dly = 0;
|
||||
always @(posedge clk)
|
||||
din_dly <= din;
|
||||
|
||||
reg sign_bit = 0;
|
||||
always @(posedge clk)
|
||||
sign_bit <= din[24];
|
||||
|
||||
//---------------------- flag -------------------------
|
||||
reg signbit3 = 0;
|
||||
always @(posedge clk)
|
||||
if(din[24:22] == 3'b000 || din[24:22] == 3'b111)
|
||||
signbit3 <= 1'b1;
|
||||
else
|
||||
signbit3 <= 1'b0;
|
||||
|
||||
//------------------------------------------------------
|
||||
always @(posedge clk)
|
||||
if(signbit3 == 1'b1)
|
||||
begin
|
||||
dout <= din_dly[22:11];
|
||||
ovrflw <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dout <= {sign_bit,{10{!sign_bit}}};
|
||||
ovrflw <= 1;
|
||||
end
|
||||
reg din_nd_d1 = 0;
|
||||
always @(posedge clk) begin
|
||||
din_nd_d1 <= din_nd;
|
||||
dout_nd <= din_nd_d1;
|
||||
end
|
||||
endmodule
|
||||
+4
-4
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
// * Engineer:
|
||||
// * *************************************************** *
|
||||
// * ███████╗ ██████╗ ██████╗ ██████╗ ██████╗ ██╗ ██╗ *
|
||||
@@ -12,13 +12,13 @@
|
||||
// * NOTE : this is the first version convert from wider bitwidth to narrower bitwidth
|
||||
|
||||
module width_convert #(
|
||||
parameter INPUT_WIDTH = 16,
|
||||
parameter OUTPUT_WIDTH = 2
|
||||
parameter INPUT_WIDTH = 32,
|
||||
parameter OUTPUT_WIDTH = 1
|
||||
) (
|
||||
input clk,
|
||||
input rst,
|
||||
input data_in_valid,
|
||||
input wire data_in_ready,
|
||||
output wire data_in_ready,
|
||||
input wire [INPUT_WIDTH - 1 : 0] data_in,
|
||||
output reg data_out_valid,
|
||||
output reg [OUTPUT_WIDTH -1 : 0] data_out
|
||||
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -0,0 +1,82 @@
|
||||
`timescale 1ns / 1ns
|
||||
|
||||
module tb_extract_mac_frame ();
|
||||
|
||||
reg clk = 0;
|
||||
always #1 clk <= ~clk;
|
||||
|
||||
reg [ 3:0] cnt_startup = 0;
|
||||
reg rst;
|
||||
|
||||
reg ldpc_in;
|
||||
reg [31:0] cnt_in = 0;
|
||||
reg [ 4:0] cnt_sleep = 0;
|
||||
reg sleep = 0;
|
||||
reg cnt_in_valid = 0;
|
||||
|
||||
|
||||
wire m_axis_mac_frame_tvalid;
|
||||
wire [31:0] m_axis_mac_frame_tdata;
|
||||
wire m_axis_mac_frame_tlast;
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
if (m_axis_mac_frame_tlast == 1) begin
|
||||
cnt_startup <= 0;
|
||||
end
|
||||
else if (cnt_startup < 4'hF) begin
|
||||
cnt_startup <= cnt_startup + 1;
|
||||
end
|
||||
rst <= cnt_startup <= 4'hC;
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_in <= 0;
|
||||
end
|
||||
|
||||
ldpc_in <= $random();
|
||||
|
||||
if (cnt_startup == 4'hF) begin
|
||||
if (sleep) begin
|
||||
cnt_in <= 0;
|
||||
cnt_in_valid <= 0;
|
||||
cnt_sleep <= cnt_sleep + 1;
|
||||
if (cnt_sleep == 5'b11111) begin
|
||||
sleep <= 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cnt_sleep <= 0;
|
||||
if (cnt_in < 1024) begin
|
||||
cnt_in <= cnt_in + 1;
|
||||
end
|
||||
|
||||
if (cnt_in == 1023) begin
|
||||
sleep <= 1;
|
||||
end
|
||||
|
||||
cnt_in_valid <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
extract_mac_frame u_extract_mac_frame (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.ldpc_dec_out_start (cnt_startup == 4'hD),
|
||||
.ldpc_dec_out_valid (cnt_in_valid),
|
||||
.ldpc_dec_out_data (ldpc_in),
|
||||
.m_axis_mac_frame_tvalid(m_axis_mac_frame_tvalid),
|
||||
.m_axis_mac_frame_tdata (m_axis_mac_frame_tdata),
|
||||
.m_axis_mac_frame_tready(1),
|
||||
.m_axis_mac_frame_tlast (m_axis_mac_frame_tlast)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+1
-1
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
`timescale 1ns / 1ns
|
||||
module tb_recv_top ();
|
||||
|
||||
reg clk = 0;
|
||||
reg clk_2x = 0;
|
||||
reg clk_4x = 0;
|
||||
reg rst = 1;
|
||||
|
||||
always #(4) clk = ~clk;
|
||||
always #(2) clk_2x = ~clk_2x;
|
||||
always #(1) clk_4x = ~clk_4x;
|
||||
|
||||
initial begin
|
||||
#20 rst <= 0;
|
||||
end
|
||||
|
||||
reg signed [11:0] ad9361_rx_data_i;
|
||||
reg signed [11:0] ad9361_rx_data_q;
|
||||
reg [ 9:0] k1;
|
||||
reg [ 9:0] k2;
|
||||
reg [11:0] mem_i [0:637049];
|
||||
reg [11:0] mem_q [0:637049];
|
||||
|
||||
initial begin
|
||||
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_i2_new2.txt", mem_i);
|
||||
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/frame_q2_new2.txt", mem_q);
|
||||
$display("Read mem done ");
|
||||
end
|
||||
|
||||
// reg [31:0] idx = 46500 - 8000;
|
||||
reg [31:0] idx = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
idx <= idx + 1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ad9361_rx_data_i <= 0;
|
||||
ad9361_rx_data_q <= 0;
|
||||
k1 <= 0;
|
||||
k2 <= 0;
|
||||
end
|
||||
else begin
|
||||
ad9361_rx_data_i <= $signed(k1);
|
||||
ad9361_rx_data_q <= $signed(k2);
|
||||
k1 <= mem_i[idx];
|
||||
k2 <= mem_q[idx];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
RecvTop u_RecvTop (
|
||||
.clk (clk),
|
||||
.clk_2x (clk_2x),
|
||||
.clk_4x (clk_4x),
|
||||
.rst (rst),
|
||||
.rst2 (rst),
|
||||
.dini (ad9361_rx_data_i),
|
||||
.dinq (ad9361_rx_data_q),
|
||||
.ad9361_ctrl_in (),
|
||||
.vio_tsync_inter16(1),
|
||||
.EQUenable_vio (1),
|
||||
.Zerozone_vio (8'd29),
|
||||
.vio_stopbit (7'd60),
|
||||
.flag_stop (flag_stop),
|
||||
.addr_stop (addr_stop),
|
||||
.recvNetData (recvNetData),
|
||||
.recvNetDataNd (recvNetDataNd)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,53 @@
|
||||
`timescale 1ns / 1ns
|
||||
module tb_scrambler ();
|
||||
|
||||
|
||||
reg clk = 0;
|
||||
always #1 clk <= ~clk;
|
||||
reg [3:0] cnt_startup = 0;
|
||||
reg rst;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cnt_startup < 4'hF) begin
|
||||
cnt_startup <= cnt_startup + 1;
|
||||
end
|
||||
rst <= cnt_startup <= 4'hC;
|
||||
end
|
||||
|
||||
|
||||
reg [31:0] s_axis_tdata;
|
||||
reg s_axis_tvalid;
|
||||
wire s_axis_tready;
|
||||
reg s_axis_tlast;
|
||||
wire [31:0] m_axis_tdata;
|
||||
wire m_axis_tvalid;
|
||||
// wire m_axis_tvalid;
|
||||
wire m_axis_tlast;
|
||||
reg [31:0] cnt = 0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
s_axis_tvalid <= (cnt_startup == 4'hF && cnt < 32);
|
||||
if (rst) begin
|
||||
s_axis_tdata <= 0;
|
||||
end
|
||||
else if (s_axis_tready && cnt < 32) begin
|
||||
s_axis_tdata <= cnt;
|
||||
cnt <= cnt + 1;
|
||||
end
|
||||
end
|
||||
|
||||
scrambler u_scrambler (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.s_axis_tdata (s_axis_tdata),
|
||||
.s_axis_tvalid(s_axis_tvalid),
|
||||
.s_axis_tready(s_axis_tready),
|
||||
.s_axis_tlast (s_axis_tlast),
|
||||
.m_axis_tdata (m_axis_tdata),
|
||||
.m_axis_tvalid(m_axis_tvalid),
|
||||
.m_axis_tready(1),
|
||||
.m_axis_tlast (m_axis_tlast)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,215 @@
|
||||
`timescale 1ns / 100ps
|
||||
module tb_sys_tx_rx_e_d ();
|
||||
|
||||
reg ad9361_rx_clk = 0; // 50MHz 20ns
|
||||
reg clk_crystal = 0; // 40MHz 25ns
|
||||
|
||||
always #(10) ad9361_rx_clk = ~ad9361_rx_clk;
|
||||
always #(12.5) clk_crystal = ~clk_crystal;
|
||||
|
||||
// ******** Wire & Reg ********
|
||||
|
||||
// power on clock domain
|
||||
wire clk_poweron;
|
||||
(*max_fanout = 256 *)
|
||||
wire rst_sys;
|
||||
wire poweron_locked;
|
||||
|
||||
// ad9361 clock domain
|
||||
wire locked;
|
||||
wire clk_1x;
|
||||
wire clk_2x;
|
||||
wire clk_4x;
|
||||
|
||||
// enc signal
|
||||
wire enc_fifo_rd_en;
|
||||
wire [31:0] enc_fifo_dout_map;
|
||||
wire enc_fifo_empty;
|
||||
|
||||
// tx bus
|
||||
wire clk_tx_data_src;
|
||||
reg [31:0] tx_data_src_count;
|
||||
reg [31:0] tx_data_src_tdata;
|
||||
wire tx_data_src_tready;
|
||||
reg tx_data_src_tvalid;
|
||||
// tx signal
|
||||
wire tx_test_flag;
|
||||
|
||||
// baseband signal
|
||||
wire [11:0] ad9361_rx_data_i;
|
||||
wire [11:0] ad9361_rx_data_q;
|
||||
wire ad9361_rx_frame_i;
|
||||
wire ad9361_rx_frame_q;
|
||||
wire [11:0] ad9361_tx_data_i;
|
||||
wire [11:0] ad9361_tx_data_q;
|
||||
wire [ 2:0] speed_mode;
|
||||
|
||||
// phy control signal
|
||||
wire phy_rst_vio;
|
||||
wire phy_rst_ps;
|
||||
wire phy_rst;
|
||||
wire phy_tx_test_flag_vio;
|
||||
wire phy_tx_test_flag;
|
||||
|
||||
|
||||
// ***** simulation *****
|
||||
reg [ 3:0] cnt_delay = 0;
|
||||
reg [31:0] idx = 0;
|
||||
reg send_start = 0;
|
||||
reg [31:0] mem [0:31]; // 1024 bit
|
||||
initial begin
|
||||
$readmemh("C:/Users/ZoroGH/dev/vivadoPrj/MM7020/source/sim/sim_data/enc_src.txt", mem);
|
||||
end
|
||||
always @(posedge clk_1x) send_start <= (cnt_delay >= 4'hA) && (cnt_delay <= 4'hE);
|
||||
|
||||
// ******** Assingment ********
|
||||
assign ad9361_tx_clk = clk_1x;
|
||||
assign rst_sys = ~poweron_locked;
|
||||
// ******** Logic Block ********
|
||||
|
||||
// ************************ ************************
|
||||
// ************************ simulation ************************
|
||||
// ************************ ************************
|
||||
|
||||
|
||||
|
||||
|
||||
always @(posedge clk_poweron) begin
|
||||
if (rst_sys) begin
|
||||
cnt_delay <= 0;
|
||||
end
|
||||
else if (cnt_delay < 4'hF) begin
|
||||
cnt_delay <= cnt_delay + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_poweron) begin
|
||||
if (rst_sys) begin
|
||||
idx <= 0;
|
||||
tx_data_src_tvalid <= 0;
|
||||
tx_data_src_tdata <= 0;
|
||||
tx_data_src_count <= 32;
|
||||
end
|
||||
else if (cnt_delay == 4'hF) begin
|
||||
tx_data_src_tvalid <= 1;
|
||||
tx_data_src_tdata <= mem[idx];
|
||||
if (tx_data_src_tready) begin
|
||||
if (idx < 31) begin
|
||||
idx <= idx + 1;
|
||||
tx_data_src_count <= tx_data_src_count - 1;
|
||||
end
|
||||
else begin
|
||||
idx <= 0;
|
||||
tx_data_src_count <= 32;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// ************************************************************
|
||||
// ************************ simulation ************************
|
||||
// ************************************************************
|
||||
|
||||
|
||||
// ******** Inst ********
|
||||
|
||||
clk_wiz_poweron u_clk_wiz_poweron (
|
||||
// Clock out ports
|
||||
.clk_poweron(clk_poweron), // output clk_poweron
|
||||
// Status and control signals
|
||||
.locked (poweron_locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_crystal(clk_crystal) // input clk_crystal
|
||||
);
|
||||
|
||||
// clock domain - ad9361 rx & tx
|
||||
clk_wiz_baseband u_clk_wiz_baseband (
|
||||
// Clock out ports
|
||||
.clk_1x (clk_1x), // output clk_1x
|
||||
.clk_2x (clk_2x), // output clk_2x
|
||||
.clk_4x (clk_4x), // output clk_4x
|
||||
// Status and control signals
|
||||
.locked (locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_src(ad9361_rx_clk) // input clk_src
|
||||
);
|
||||
|
||||
// ************************************************************
|
||||
// *************************** TX *****************************
|
||||
// ************************************************************
|
||||
|
||||
|
||||
enc_control u_enc_control (
|
||||
.clk (clk_poweron),
|
||||
.rst (rst_sys),
|
||||
.s_axis_fifo_tvalid (tx_data_src_tvalid),
|
||||
.s_axis_fifo_tready (tx_data_src_tready),
|
||||
.s_axis_fifo_tdata (tx_data_src_tdata),
|
||||
.data_src_count (tx_data_src_count),
|
||||
.fifo_enc_out_rd_clk (clk_1x),
|
||||
.fifo_enc_out_rd_en (enc_fifo_rd_en),
|
||||
.fifo_enc_out_dout_map(enc_fifo_dout_map),
|
||||
.fifo_enc_out_empty (enc_fifo_empty)
|
||||
);
|
||||
|
||||
Transmitter #(
|
||||
.AGC_HEADER_LEN(2500)
|
||||
) u_Transmitter (
|
||||
.clk (clk_1x),
|
||||
.rst (rst_sys),
|
||||
.speed_mode (2),
|
||||
.send_data_ready (send_data_ready),
|
||||
.send_start (send_start),
|
||||
.send_over (send_over),
|
||||
.clk_data_src (clk_data_src),
|
||||
.tx_data_src_tdata (enc_fifo_dout_map),
|
||||
.tx_data_src_tready(enc_fifo_rd_en),
|
||||
.tx_data_src_tvalid(~enc_fifo_empty),
|
||||
.hopping_freq (),
|
||||
.ad9361_tx_data_i (ad9361_tx_data_i),
|
||||
.ad9361_tx_data_q (ad9361_tx_data_q),
|
||||
.test (0),
|
||||
.hop_wait (100)
|
||||
);
|
||||
|
||||
|
||||
// ************************************************************
|
||||
// *************************** RX *****************************
|
||||
// ************************************************************
|
||||
|
||||
|
||||
RecvTop u_RecvTop (
|
||||
.clk (clk_1x),
|
||||
.clk_2x (clk_2x),
|
||||
.clk_4x (clk_4x),
|
||||
.rst (rst_sys),
|
||||
.rst2 (rst_sys),
|
||||
.dini (ad9361_tx_data_i),
|
||||
.dinq (ad9361_tx_data_q),
|
||||
.ad9361_ctrl_in (),
|
||||
.vio_tsync_inter16(1),
|
||||
.EQUenable_vio (1),
|
||||
.Zerozone_vio (8'd29),
|
||||
.vio_stopbit (7'd60),
|
||||
.flag_stop (flag_stop),
|
||||
.addr_stop (addr_stop),
|
||||
.recvNetData (recvNetData),
|
||||
.recvNetDataNd (recvNetDataNd)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+11
-46
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
@@ -22,60 +22,25 @@
|
||||
|
||||
module tb_tdma ();
|
||||
|
||||
|
||||
|
||||
reg clk = 1;
|
||||
reg clk_tx = 1;
|
||||
reg rst = 1;
|
||||
always #1 clk <= ~clk;
|
||||
initial begin
|
||||
#1000 rst <= 1'b0;
|
||||
#10 rst <= 1'b0;
|
||||
end
|
||||
|
||||
wire flag_frame_sync_m;
|
||||
reg flag_frame_sync_s = 0;
|
||||
wire intr_2ps_m;
|
||||
wire intr_2ps_s;
|
||||
wire tic_hop_m;
|
||||
wire tic_hop_s;
|
||||
wire tx_start_m;
|
||||
wire tx_start_s;
|
||||
|
||||
assign flag_frame_sync_m = 1'b0;
|
||||
|
||||
tdma #(
|
||||
.SLOT_LEN (1250000),
|
||||
.TIC_TO_PS_LEN (1200000),
|
||||
.TIC_FRAME_SYNC(42272)
|
||||
) u_tdma_master (
|
||||
.SLOT_LEN (625000), // 50MHz--> 15ms
|
||||
.TIC_TO_PS_LEN (575000),
|
||||
.TIC_FRAME_SYNC(42344)
|
||||
) u_tdma (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.flag_is_master (1'b1),
|
||||
.flag_frame_sync(flag_frame_sync_m),
|
||||
.intr_2ps (intr_2ps_m),
|
||||
// .tic_hop (tic_hop_m),
|
||||
.tx_start (tx_start_m)
|
||||
.flag_is_master (1),
|
||||
.flag_frame_sync(0),
|
||||
.intr_2ps (intr_2ps),
|
||||
.tx_start (tx_start),
|
||||
.rx_rst (rx_rst)
|
||||
);
|
||||
|
||||
|
||||
tdma #(
|
||||
.SLOT_LEN (20000),
|
||||
.TIC_TO_PS_LEN (18000),
|
||||
.TIC_FRAME_SYNC(2000)
|
||||
) u_tdma_slave (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.flag_is_master (1'b0),
|
||||
.flag_frame_sync(flag_frame_sync_s),
|
||||
.intr_2ps (intr_2ps_s),
|
||||
// .tic_hop (tic_hop_s),
|
||||
.tx_start (tx_start_s)
|
||||
);
|
||||
|
||||
|
||||
initial begin
|
||||
#12000 flag_frame_sync_s <= 1'b1;
|
||||
#3 flag_frame_sync_s <= 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
`timescale 1ns / 1ps
|
||||
`timescale 1ns / 1ns
|
||||
module tb_width_convert ();
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
# this is a demo create ip using tcl script
|
||||
|
||||
# create a new ip ila named ila_rx2, if the ip already exists, skip create_ip step
|
||||
create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_tdma
|
||||
# set the ip property
|
||||
set_property -dict {
|
||||
CONFIG.C_EN_STRG_QUAL 1
|
||||
CONFIG.C_NUM_OF_PROBES {18}
|
||||
CONFIG.C_PROBE0_WIDTH {12}
|
||||
CONFIG.C_PROBE1_WIDTH {12}
|
||||
CONFIG.C_PROBE2_WIDTH {1}
|
||||
CONFIG.C_PROBE3_WIDTH {1}
|
||||
CONFIG.C_PROBE4_WIDTH {1}
|
||||
CONFIG.C_PROBE5_WIDTH {10}
|
||||
CONFIG.C_PROBE6_WIDTH {10}
|
||||
CONFIG.C_PROBE7_WIDTH {1}
|
||||
CONFIG.C_PROBE8_WIDTH {10}
|
||||
CONFIG.C_PROBE9_WIDTH {10}
|
||||
CONFIG.C_PROBE10_WIDTH {1}
|
||||
CONFIG.C_PROBE11_WIDTH {10}
|
||||
CONFIG.C_PROBE12_WIDTH {10}
|
||||
CONFIG.C_PROBE13_WIDTH {1}
|
||||
CONFIG.C_PROBE14_WIDTH {10}
|
||||
CONFIG.C_PROBE15_WIDTH {10}
|
||||
CONFIG.C_PROBE16_WIDTH {9}
|
||||
CONFIG.C_PROBE17_WIDTH {9}
|
||||
} [get_ips ila_recv_top]
|
||||
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C_NUM_OF_PROBES {6} \
|
||||
CONFIG.C_PROBE0_WIDTH {24} \
|
||||
] [get_ips ila_tdma]
|
||||
Reference in New Issue
Block a user